2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
18 config RWSEM_GENERIC_SPINLOCK
21 config RWSEM_XCHGADD_ALGORITHM
26 select HAVE_FUNCTION_GRAPH_TRACER
27 select HAVE_FUNCTION_TRACER
29 select HAVE_KERNEL_GZIP if RAMKERNEL
30 select HAVE_KERNEL_BZIP2 if RAMKERNEL
31 select HAVE_KERNEL_LZMA if RAMKERNEL
33 select ARCH_WANT_OPTIONAL_GPIOLIB
45 config GENERIC_FIND_NEXT_BIT
48 config GENERIC_HARDIRQS
51 config GENERIC_IRQ_PROBE
54 config GENERIC_HARDIRQS_NO__DO_IRQ
60 config FORCE_MAX_ZONEORDER
64 config GENERIC_CALIBRATE_DELAY
67 config LOCKDEP_SUPPORT
70 config STACKTRACE_SUPPORT
73 config TRACE_IRQFLAGS_SUPPORT
78 source "kernel/Kconfig.preempt"
80 source "kernel/Kconfig.freezer"
82 menu "Blackfin Processor Options"
84 comment "Processor and Board Settings"
93 BF512 Processor Support.
98 BF514 Processor Support.
103 BF516 Processor Support.
108 BF518 Processor Support.
113 BF522 Processor Support.
118 BF523 Processor Support.
123 BF524 Processor Support.
128 BF525 Processor Support.
133 BF526 Processor Support.
138 BF527 Processor Support.
143 BF531 Processor Support.
148 BF532 Processor Support.
153 BF533 Processor Support.
158 BF534 Processor Support.
163 BF536 Processor Support.
168 BF537 Processor Support.
173 BF538 Processor Support.
178 BF539 Processor Support.
183 BF542 Processor Support.
188 BF542 Processor Support.
193 BF544 Processor Support.
198 BF544 Processor Support.
203 BF547 Processor Support.
208 BF547 Processor Support.
213 BF548 Processor Support.
218 BF548 Processor Support.
223 BF549 Processor Support.
228 BF549 Processor Support.
233 BF561 Processor Support.
239 select TICKSOURCE_CORETMR
240 bool "Symmetric multi-processing support"
242 This enables support for systems with more than one CPU,
243 like the dual core BF561. If you have a system with only one
244 CPU, say N. If you have a system with more than one CPU, say Y.
246 If you don't know what to do here, say N.
254 bool "Support for hot-pluggable CPUs"
255 depends on SMP && HOTPLUG
263 config HAVE_LEGACY_PER_CPU_AREA
269 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
270 default 2 if (BF537 || BF536 || BF534)
271 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
272 default 4 if (BF538 || BF539)
276 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
277 default 3 if (BF537 || BF536 || BF534 || BF54xM)
278 default 5 if (BF561 || BF538 || BF539)
279 default 6 if (BF533 || BF532 || BF531)
283 default BF_REV_0_0 if (BF51x || BF52x)
284 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
285 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
289 depends on (BF51x || BF52x || (BF54x && !BF54xM))
293 depends on (BF51x || BF52x || (BF54x && !BF54xM))
297 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
301 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
305 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
309 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
313 depends on (BF533 || BF532 || BF531)
325 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
328 config MEM_GENERIC_BOARD
330 depends on GENERIC_BOARD
333 config MEM_MT48LC64M4A2FB_7E
335 depends on (BFIN533_STAMP)
338 config MEM_MT48LC16M16A2TG_75
340 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
341 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
342 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
343 || BFIN527_BLUETECHNIX_CM)
346 config MEM_MT48LC32M8A2_75
348 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
351 config MEM_MT48LC8M32B2B5_7
353 depends on (BFIN561_BLUETECHNIX_CM)
356 config MEM_MT48LC32M16A2TG_75
358 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
361 config MEM_MT48LC32M8A2_75
363 depends on (BFIN518F_EZBRD)
366 config MEM_MT48H32M16LFCJ_75
368 depends on (BFIN526_EZBRD)
371 source "arch/blackfin/mach-bf518/Kconfig"
372 source "arch/blackfin/mach-bf527/Kconfig"
373 source "arch/blackfin/mach-bf533/Kconfig"
374 source "arch/blackfin/mach-bf561/Kconfig"
375 source "arch/blackfin/mach-bf537/Kconfig"
376 source "arch/blackfin/mach-bf538/Kconfig"
377 source "arch/blackfin/mach-bf548/Kconfig"
379 menu "Board customizations"
382 bool "Default bootloader kernel arguments"
385 string "Initial kernel command string"
386 depends on CMDLINE_BOOL
387 default "console=ttyBF0,57600"
389 If you don't have a boot loader capable of passing a command line string
390 to the kernel, you may specify one here. As a minimum, you should specify
391 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
394 hex "Kernel load address for booting"
396 range 0x1000 0x20000000
398 This option allows you to set the load address of the kernel.
399 This can be useful if you are on a board which has a small amount
400 of memory or you wish to reserve some memory at the beginning of
403 Note that you need to keep this value above 4k (0x1000) as this
404 memory region is used to capture NULL pointer references as well
405 as some core kernel functions.
408 hex "Kernel ROM Base"
411 range 0x20000000 0x20400000 if !(BF54x || BF561)
412 range 0x20000000 0x30000000 if (BF54x || BF561)
414 Make sure your ROM base does not include any file-header
415 information that is prepended to the kernel.
417 For example, the bootable U-Boot format (created with
418 mkimage) has a 64 byte header (0x40). So while the image
419 you write to flash might start at say 0x20080000, you have
420 to add 0x40 to get the kernel's ROM base as it will come
423 comment "Clock/PLL Setup"
426 int "Frequency of the crystal on the board in Hz"
427 default "10000000" if BFIN532_IP0X
428 default "11059200" if BFIN533_STAMP
429 default "24576000" if PNAV10
430 default "25000000" # most people use this
431 default "27000000" if BFIN533_EZKIT
432 default "30000000" if BFIN561_EZKIT
434 The frequency of CLKIN crystal oscillator on the board in Hz.
435 Warning: This value should match the crystal on the board. Otherwise,
436 peripherals won't work properly.
438 config BFIN_KERNEL_CLOCK
439 bool "Re-program Clocks while Kernel boots?"
442 This option decides if kernel clocks are re-programed from the
443 bootloader settings. If the clocks are not set, the SDRAM settings
444 are also not changed, and the Bootloader does 100% of the hardware
449 depends on BFIN_KERNEL_CLOCK
454 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
457 If this is set the clock will be divided by 2, before it goes to the PLL.
461 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
463 default "22" if BFIN533_EZKIT
464 default "45" if BFIN533_STAMP
465 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
466 default "22" if BFIN533_BLUETECHNIX_CM
467 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
468 default "20" if BFIN561_EZKIT
469 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
471 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
472 PLL Frequency = (Crystal Frequency) * (this setting)
475 prompt "Core Clock Divider"
476 depends on BFIN_KERNEL_CLOCK
479 This sets the frequency of the core. It can be 1, 2, 4 or 8
480 Core Frequency = (PLL frequency) / (this setting)
496 int "System Clock Divider"
497 depends on BFIN_KERNEL_CLOCK
501 This sets the frequency of the system clock (including SDRAM or DDR).
502 This can be between 1 and 15
503 System Clock = (PLL frequency) / (this setting)
506 prompt "DDR SDRAM Chip Type"
507 depends on BFIN_KERNEL_CLOCK
509 default MEM_MT46V32M16_5B
511 config MEM_MT46V32M16_6T
514 config MEM_MT46V32M16_5B
519 prompt "DDR/SDRAM Timing"
520 depends on BFIN_KERNEL_CLOCK
521 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
523 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
524 The calculated SDRAM timing parameters may not be 100%
525 accurate - This option is therefore marked experimental.
527 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
528 bool "Calculate Timings (EXPERIMENTAL)"
529 depends on EXPERIMENTAL
531 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
532 bool "Provide accurate Timings based on target SCLK"
534 Please consult the Blackfin Hardware Reference Manuals as well
535 as the memory device datasheet.
536 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
539 menu "Memory Init Control"
540 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
557 config MEM_EBIU_DDRQUE
574 # Max & Min Speeds for various Chips
578 default 400000000 if BF512
579 default 400000000 if BF514
580 default 400000000 if BF516
581 default 400000000 if BF518
582 default 400000000 if BF522
583 default 600000000 if BF523
584 default 400000000 if BF524
585 default 600000000 if BF525
586 default 400000000 if BF526
587 default 600000000 if BF527
588 default 400000000 if BF531
589 default 400000000 if BF532
590 default 750000000 if BF533
591 default 500000000 if BF534
592 default 400000000 if BF536
593 default 600000000 if BF537
594 default 533333333 if BF538
595 default 533333333 if BF539
596 default 600000000 if BF542
597 default 533333333 if BF544
598 default 600000000 if BF547
599 default 600000000 if BF548
600 default 533333333 if BF549
601 default 600000000 if BF561
615 comment "Kernel Timer/Scheduler"
617 source kernel/Kconfig.hz
622 config GENERIC_CLOCKEVENTS
623 bool "Generic clock events"
626 menu "Clock event device"
627 depends on GENERIC_CLOCKEVENTS
628 config TICKSOURCE_GPTMR0
633 config TICKSOURCE_CORETMR
639 depends on GENERIC_CLOCKEVENTS
640 config CYCLES_CLOCKSOURCE
643 depends on !BFIN_SCRATCH_REG_CYCLES
646 If you say Y here, you will enable support for using the 'cycles'
647 registers as a clock source. Doing so means you will be unable to
648 safely write to the 'cycles' register during runtime. You will
649 still be able to read it (such as for performance monitoring), but
650 writing the registers will most likely crash the kernel.
652 config GPTMR0_CLOCKSOURCE
655 depends on !TICKSOURCE_GPTMR0
658 config ARCH_USES_GETTIMEOFFSET
659 depends on !GENERIC_CLOCKEVENTS
662 source kernel/time/Kconfig
667 prompt "Blackfin Exception Scratch Register"
668 default BFIN_SCRATCH_REG_RETN
670 Select the resource to reserve for the Exception handler:
671 - RETN: Non-Maskable Interrupt (NMI)
672 - RETE: Exception Return (JTAG/ICE)
673 - CYCLES: Performance counter
675 If you are unsure, please select "RETN".
677 config BFIN_SCRATCH_REG_RETN
680 Use the RETN register in the Blackfin exception handler
681 as a stack scratch register. This means you cannot
682 safely use NMI on the Blackfin while running Linux, but
683 you can debug the system with a JTAG ICE and use the
684 CYCLES performance registers.
686 If you are unsure, please select "RETN".
688 config BFIN_SCRATCH_REG_RETE
691 Use the RETE register in the Blackfin exception handler
692 as a stack scratch register. This means you cannot
693 safely use a JTAG ICE while debugging a Blackfin board,
694 but you can safely use the CYCLES performance registers
697 If you are unsure, please select "RETN".
699 config BFIN_SCRATCH_REG_CYCLES
702 Use the CYCLES register in the Blackfin exception handler
703 as a stack scratch register. This means you cannot
704 safely use the CYCLES performance registers on a Blackfin
705 board at anytime, but you can debug the system with a JTAG
708 If you are unsure, please select "RETN".
715 menu "Blackfin Kernel Optimizations"
718 comment "Memory Optimizations"
721 bool "Locate interrupt entry code in L1 Memory"
724 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
725 into L1 instruction memory. (less latency)
727 config EXCPT_IRQ_SYSC_L1
728 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
731 If enabled, the entire ASM lowlevel exception and interrupt entry code
732 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
736 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
739 If enabled, the frequently called do_irq dispatcher function is linked
740 into L1 instruction memory. (less latency)
742 config CORE_TIMER_IRQ_L1
743 bool "Locate frequently called timer_interrupt() function in L1 Memory"
746 If enabled, the frequently called timer_interrupt() function is linked
747 into L1 instruction memory. (less latency)
750 bool "Locate frequently idle function in L1 Memory"
753 If enabled, the frequently called idle function is linked
754 into L1 instruction memory. (less latency)
757 bool "Locate kernel schedule function in L1 Memory"
760 If enabled, the frequently called kernel schedule is linked
761 into L1 instruction memory. (less latency)
763 config ARITHMETIC_OPS_L1
764 bool "Locate kernel owned arithmetic functions in L1 Memory"
767 If enabled, arithmetic functions are linked
768 into L1 instruction memory. (less latency)
771 bool "Locate access_ok function in L1 Memory"
774 If enabled, the access_ok function is linked
775 into L1 instruction memory. (less latency)
778 bool "Locate memset function in L1 Memory"
781 If enabled, the memset function is linked
782 into L1 instruction memory. (less latency)
785 bool "Locate memcpy function in L1 Memory"
788 If enabled, the memcpy function is linked
789 into L1 instruction memory. (less latency)
791 config SYS_BFIN_SPINLOCK_L1
792 bool "Locate sys_bfin_spinlock function in L1 Memory"
795 If enabled, sys_bfin_spinlock function is linked
796 into L1 instruction memory. (less latency)
798 config IP_CHECKSUM_L1
799 bool "Locate IP Checksum function in L1 Memory"
802 If enabled, the IP Checksum function is linked
803 into L1 instruction memory. (less latency)
805 config CACHELINE_ALIGNED_L1
806 bool "Locate cacheline_aligned data to L1 Data Memory"
811 If enabled, cacheline_aligned data is linked
812 into L1 data memory. (less latency)
814 config SYSCALL_TAB_L1
815 bool "Locate Syscall Table L1 Data Memory"
819 If enabled, the Syscall LUT is linked
820 into L1 data memory. (less latency)
822 config CPLB_SWITCH_TAB_L1
823 bool "Locate CPLB Switch Tables L1 Data Memory"
827 If enabled, the CPLB Switch Tables are linked
828 into L1 data memory. (less latency)
831 bool "Support locating application stack in L1 Scratch Memory"
834 If enabled the application stack can be located in L1
835 scratch memory (less latency).
837 Currently only works with FLAT binaries.
839 config EXCEPTION_L1_SCRATCH
840 bool "Locate exception stack in L1 Scratch Memory"
842 depends on !APP_STACK_L1
844 Whenever an exception occurs, use the L1 Scratch memory for
845 stack storage. You cannot place the stacks of FLAT binaries
846 in L1 when using this option.
848 If you don't use L1 Scratch, then you should say Y here.
850 comment "Speed Optimizations"
851 config BFIN_INS_LOWOVERHEAD
852 bool "ins[bwl] low overhead, higher interrupt latency"
855 Reads on the Blackfin are speculative. In Blackfin terms, this means
856 they can be interrupted at any time (even after they have been issued
857 on to the external bus), and re-issued after the interrupt occurs.
858 For memory - this is not a big deal, since memory does not change if
861 If a FIFO is sitting on the end of the read, it will see two reads,
862 when the core only sees one since the FIFO receives both the read
863 which is cancelled (and not delivered to the core) and the one which
864 is re-issued (which is delivered to the core).
866 To solve this, interrupts are turned off before reads occur to
867 I/O space. This option controls which the overhead/latency of
868 controlling interrupts during this time
869 "n" turns interrupts off every read
870 (higher overhead, but lower interrupt latency)
871 "y" turns interrupts off every loop
872 (low overhead, but longer interrupt latency)
874 default behavior is to leave this set to on (type "Y"). If you are experiencing
875 interrupt latency issues, it is safe and OK to turn this off.
880 prompt "Kernel executes from"
882 Choose the memory type that the kernel will be running in.
887 The kernel will be resident in RAM when running.
892 The kernel will be resident in FLASH/ROM when running.
899 tristate "Enable Blackfin General Purpose Timers API"
902 Enable support for the General Purpose Timers API. If you
905 To compile this driver as a module, choose M here: the module
906 will be called gptimers.
909 prompt "Uncached DMA region"
910 default DMA_UNCACHED_1M
911 config DMA_UNCACHED_4M
912 bool "Enable 4M DMA region"
913 config DMA_UNCACHED_2M
914 bool "Enable 2M DMA region"
915 config DMA_UNCACHED_1M
916 bool "Enable 1M DMA region"
917 config DMA_UNCACHED_512K
918 bool "Enable 512K DMA region"
919 config DMA_UNCACHED_256K
920 bool "Enable 256K DMA region"
921 config DMA_UNCACHED_128K
922 bool "Enable 128K DMA region"
923 config DMA_UNCACHED_NONE
924 bool "Disable DMA region"
928 comment "Cache Support"
933 config BFIN_EXTMEM_ICACHEABLE
934 bool "Enable ICACHE for external memory"
935 depends on BFIN_ICACHE
937 config BFIN_L2_ICACHEABLE
938 bool "Enable ICACHE for L2 SRAM"
939 depends on BFIN_ICACHE
940 depends on BF54x || BF561
946 config BFIN_DCACHE_BANKA
947 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
948 depends on BFIN_DCACHE && !BF531
950 config BFIN_EXTMEM_DCACHEABLE
951 bool "Enable DCACHE for external memory"
952 depends on BFIN_DCACHE
955 prompt "External memory DCACHE policy"
956 depends on BFIN_EXTMEM_DCACHEABLE
957 default BFIN_EXTMEM_WRITEBACK if !SMP
958 default BFIN_EXTMEM_WRITETHROUGH if SMP
959 config BFIN_EXTMEM_WRITEBACK
964 Cached data will be written back to SDRAM only when needed.
965 This can give a nice increase in performance, but beware of
966 broken drivers that do not properly invalidate/flush their
969 Write Through Policy:
970 Cached data will always be written back to SDRAM when the
971 cache is updated. This is a completely safe setting, but
972 performance is worse than Write Back.
974 If you are unsure of the options and you want to be safe,
975 then go with Write Through.
977 config BFIN_EXTMEM_WRITETHROUGH
981 Cached data will be written back to SDRAM only when needed.
982 This can give a nice increase in performance, but beware of
983 broken drivers that do not properly invalidate/flush their
986 Write Through Policy:
987 Cached data will always be written back to SDRAM when the
988 cache is updated. This is a completely safe setting, but
989 performance is worse than Write Back.
991 If you are unsure of the options and you want to be safe,
992 then go with Write Through.
996 config BFIN_L2_DCACHEABLE
997 bool "Enable DCACHE for L2 SRAM"
998 depends on BFIN_DCACHE
999 depends on (BF54x || BF561) && !SMP
1002 prompt "L2 SRAM DCACHE policy"
1003 depends on BFIN_L2_DCACHEABLE
1004 default BFIN_L2_WRITEBACK
1005 config BFIN_L2_WRITEBACK
1008 config BFIN_L2_WRITETHROUGH
1009 bool "Write through"
1013 comment "Memory Protection Unit"
1015 bool "Enable the memory protection unit (EXPERIMENTAL)"
1018 Use the processor's MPU to protect applications from accessing
1019 memory they do not own. This comes at a performance penalty
1020 and is recommended only for debugging.
1022 comment "Asynchronous Memory Configuration"
1024 menu "EBIU_AMGCTL Global Control"
1026 bool "Enable CLKOUT"
1030 bool "DMA has priority over core for ext. accesses"
1035 bool "Bank 0 16 bit packing enable"
1040 bool "Bank 1 16 bit packing enable"
1045 bool "Bank 2 16 bit packing enable"
1050 bool "Bank 3 16 bit packing enable"
1054 prompt "Enable Asynchronous Memory Banks"
1058 bool "Disable All Banks"
1061 bool "Enable Bank 0"
1063 config C_AMBEN_B0_B1
1064 bool "Enable Bank 0 & 1"
1066 config C_AMBEN_B0_B1_B2
1067 bool "Enable Bank 0 & 1 & 2"
1070 bool "Enable All Banks"
1074 menu "EBIU_AMBCTL Control"
1076 hex "Bank 0 (AMBCTL0.L)"
1079 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1080 used to control the Asynchronous Memory Bank 0 settings.
1083 hex "Bank 1 (AMBCTL0.H)"
1085 default 0x5558 if BF54x
1087 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1088 used to control the Asynchronous Memory Bank 1 settings.
1091 hex "Bank 2 (AMBCTL1.L)"
1094 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1095 used to control the Asynchronous Memory Bank 2 settings.
1098 hex "Bank 3 (AMBCTL1.H)"
1101 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1102 used to control the Asynchronous Memory Bank 3 settings.
1106 config EBIU_MBSCTLVAL
1107 hex "EBIU Bank Select Control Register"
1112 hex "Flash Memory Mode Control Register"
1117 hex "Flash Memory Bank Control Register"
1122 #############################################################################
1123 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1129 Support for PCI bus.
1131 source "drivers/pci/Kconfig"
1133 source "drivers/pcmcia/Kconfig"
1135 source "drivers/pci/hotplug/Kconfig"
1139 menu "Executable file formats"
1141 source "fs/Kconfig.binfmt"
1145 menu "Power management options"
1147 source "kernel/power/Kconfig"
1149 config ARCH_SUSPEND_POSSIBLE
1153 prompt "Standby Power Saving Mode"
1155 default PM_BFIN_SLEEP_DEEPER
1156 config PM_BFIN_SLEEP_DEEPER
1159 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1160 power dissipation by disabling the clock to the processor core (CCLK).
1161 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1162 to 0.85 V to provide the greatest power savings, while preserving the
1164 The PLL and system clock (SCLK) continue to operate at a very low
1165 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1166 the SDRAM is put into Self Refresh Mode. Typically an external event
1167 such as GPIO interrupt or RTC activity wakes up the processor.
1168 Various Peripherals such as UART, SPORT, PPI may not function as
1169 normal during Sleep Deeper, due to the reduced SCLK frequency.
1170 When in the sleep mode, system DMA access to L1 memory is not supported.
1172 If unsure, select "Sleep Deeper".
1174 config PM_BFIN_SLEEP
1177 Sleep Mode (High Power Savings) - The sleep mode reduces power
1178 dissipation by disabling the clock to the processor core (CCLK).
1179 The PLL and system clock (SCLK), however, continue to operate in
1180 this mode. Typically an external event or RTC activity will wake
1181 up the processor. When in the sleep mode, system DMA access to L1
1182 memory is not supported.
1184 If unsure, select "Sleep Deeper".
1187 config PM_WAKEUP_BY_GPIO
1188 bool "Allow Wakeup from Standby by GPIO"
1189 depends on PM && !BF54x
1191 config PM_WAKEUP_GPIO_NUMBER
1194 depends on PM_WAKEUP_BY_GPIO
1198 prompt "GPIO Polarity"
1199 depends on PM_WAKEUP_BY_GPIO
1200 default PM_WAKEUP_GPIO_POLAR_H
1201 config PM_WAKEUP_GPIO_POLAR_H
1203 config PM_WAKEUP_GPIO_POLAR_L
1205 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1207 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1209 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1213 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1216 config PM_BFIN_WAKE_PH6
1217 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1218 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1221 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1223 config PM_BFIN_WAKE_GP
1224 bool "Allow Wake-Up from GPIOs"
1225 depends on PM && BF54x
1228 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1229 (all processors, except ADSP-BF549). This option sets
1230 the general-purpose wake-up enable (GPWE) control bit to enable
1231 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1232 On ADSP-BF549 this option enables the the same functionality on the
1233 /MRXON pin also PH7.
1237 menu "CPU Frequency scaling"
1240 source "drivers/cpufreq/Kconfig"
1242 config BFIN_CPU_FREQ
1245 select CPU_FREQ_TABLE
1249 bool "CPU Voltage scaling"
1250 depends on EXPERIMENTAL
1254 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1255 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1256 manuals. There is a theoretical risk that during VDDINT transitions
1261 source "net/Kconfig"
1263 source "drivers/Kconfig"
1265 source "drivers/firmware/Kconfig"
1269 source "arch/blackfin/Kconfig.debug"
1271 source "security/Kconfig"
1273 source "crypto/Kconfig"
1275 source "lib/Kconfig"