11 config RWSEM_GENERIC_SPINLOCK
14 config RWSEM_XCHGADD_ALGORITHM
20 select HAVE_ARCH_TRACEHOOK
21 select HAVE_DYNAMIC_FTRACE
22 select HAVE_FTRACE_MCOUNT_RECORD
23 select HAVE_FUNCTION_GRAPH_TRACER
24 select HAVE_FUNCTION_TRACER
25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
27 select HAVE_KERNEL_GZIP if RAMKERNEL
28 select HAVE_KERNEL_BZIP2 if RAMKERNEL
29 select HAVE_KERNEL_LZMA if RAMKERNEL
30 select HAVE_KERNEL_LZO if RAMKERNEL
32 select ARCH_WANT_OPTIONAL_GPIOLIB
44 config GENERIC_FIND_NEXT_BIT
47 config GENERIC_HARDIRQS
50 config GENERIC_IRQ_PROBE
53 config GENERIC_HARDIRQS_NO__DO_IRQ
59 config FORCE_MAX_ZONEORDER
63 config GENERIC_CALIBRATE_DELAY
66 config LOCKDEP_SUPPORT
69 config STACKTRACE_SUPPORT
72 config TRACE_IRQFLAGS_SUPPORT
77 source "kernel/Kconfig.preempt"
79 source "kernel/Kconfig.freezer"
81 menu "Blackfin Processor Options"
83 comment "Processor and Board Settings"
92 BF512 Processor Support.
97 BF514 Processor Support.
102 BF516 Processor Support.
107 BF518 Processor Support.
112 BF522 Processor Support.
117 BF523 Processor Support.
122 BF524 Processor Support.
127 BF525 Processor Support.
132 BF526 Processor Support.
137 BF527 Processor Support.
142 BF531 Processor Support.
147 BF532 Processor Support.
152 BF533 Processor Support.
157 BF534 Processor Support.
162 BF536 Processor Support.
167 BF537 Processor Support.
172 BF538 Processor Support.
177 BF539 Processor Support.
182 BF542 Processor Support.
187 BF542 Processor Support.
192 BF544 Processor Support.
197 BF544 Processor Support.
202 BF547 Processor Support.
207 BF547 Processor Support.
212 BF548 Processor Support.
217 BF548 Processor Support.
222 BF549 Processor Support.
227 BF549 Processor Support.
232 BF561 Processor Support.
238 select TICKSOURCE_CORETMR
239 bool "Symmetric multi-processing support"
241 This enables support for systems with more than one CPU,
242 like the dual core BF561. If you have a system with only one
243 CPU, say N. If you have a system with more than one CPU, say Y.
245 If you don't know what to do here, say N.
253 bool "Support for hot-pluggable CPUs"
254 depends on SMP && HOTPLUG
262 config HAVE_LEGACY_PER_CPU_AREA
268 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
269 default 2 if (BF537 || BF536 || BF534)
270 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
271 default 4 if (BF538 || BF539)
275 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
276 default 3 if (BF537 || BF536 || BF534 || BF54xM)
277 default 5 if (BF561 || BF538 || BF539)
278 default 6 if (BF533 || BF532 || BF531)
282 default BF_REV_0_0 if (BF51x || BF52x)
283 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
284 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
288 depends on (BF51x || BF52x || (BF54x && !BF54xM))
292 depends on (BF51x || BF52x || (BF54x && !BF54xM))
296 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
300 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
304 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
308 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
312 depends on (BF533 || BF532 || BF531)
324 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
327 config MEM_MT48LC64M4A2FB_7E
329 depends on (BFIN533_STAMP)
332 config MEM_MT48LC16M16A2TG_75
334 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
335 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
336 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
337 || BFIN527_BLUETECHNIX_CM)
340 config MEM_MT48LC32M8A2_75
342 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
345 config MEM_MT48LC8M32B2B5_7
347 depends on (BFIN561_BLUETECHNIX_CM)
350 config MEM_MT48LC32M16A2TG_75
352 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
355 config MEM_MT48H32M16LFCJ_75
357 depends on (BFIN526_EZBRD)
360 source "arch/blackfin/mach-bf518/Kconfig"
361 source "arch/blackfin/mach-bf527/Kconfig"
362 source "arch/blackfin/mach-bf533/Kconfig"
363 source "arch/blackfin/mach-bf561/Kconfig"
364 source "arch/blackfin/mach-bf537/Kconfig"
365 source "arch/blackfin/mach-bf538/Kconfig"
366 source "arch/blackfin/mach-bf548/Kconfig"
368 menu "Board customizations"
371 bool "Default bootloader kernel arguments"
374 string "Initial kernel command string"
375 depends on CMDLINE_BOOL
376 default "console=ttyBF0,57600"
378 If you don't have a boot loader capable of passing a command line string
379 to the kernel, you may specify one here. As a minimum, you should specify
380 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
383 hex "Kernel load address for booting"
385 range 0x1000 0x20000000
387 This option allows you to set the load address of the kernel.
388 This can be useful if you are on a board which has a small amount
389 of memory or you wish to reserve some memory at the beginning of
392 Note that you need to keep this value above 4k (0x1000) as this
393 memory region is used to capture NULL pointer references as well
394 as some core kernel functions.
397 hex "Kernel ROM Base"
400 range 0x20000000 0x20400000 if !(BF54x || BF561)
401 range 0x20000000 0x30000000 if (BF54x || BF561)
403 Make sure your ROM base does not include any file-header
404 information that is prepended to the kernel.
406 For example, the bootable U-Boot format (created with
407 mkimage) has a 64 byte header (0x40). So while the image
408 you write to flash might start at say 0x20080000, you have
409 to add 0x40 to get the kernel's ROM base as it will come
412 comment "Clock/PLL Setup"
415 int "Frequency of the crystal on the board in Hz"
416 default "10000000" if BFIN532_IP0X
417 default "11059200" if BFIN533_STAMP
418 default "24576000" if PNAV10
419 default "25000000" # most people use this
420 default "27000000" if BFIN533_EZKIT
421 default "30000000" if BFIN561_EZKIT
423 The frequency of CLKIN crystal oscillator on the board in Hz.
424 Warning: This value should match the crystal on the board. Otherwise,
425 peripherals won't work properly.
427 config BFIN_KERNEL_CLOCK
428 bool "Re-program Clocks while Kernel boots?"
431 This option decides if kernel clocks are re-programed from the
432 bootloader settings. If the clocks are not set, the SDRAM settings
433 are also not changed, and the Bootloader does 100% of the hardware
438 depends on BFIN_KERNEL_CLOCK
443 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
446 If this is set the clock will be divided by 2, before it goes to the PLL.
450 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
452 default "22" if BFIN533_EZKIT
453 default "45" if BFIN533_STAMP
454 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
455 default "22" if BFIN533_BLUETECHNIX_CM
456 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
457 default "20" if BFIN561_EZKIT
458 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
460 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
461 PLL Frequency = (Crystal Frequency) * (this setting)
464 prompt "Core Clock Divider"
465 depends on BFIN_KERNEL_CLOCK
468 This sets the frequency of the core. It can be 1, 2, 4 or 8
469 Core Frequency = (PLL frequency) / (this setting)
485 int "System Clock Divider"
486 depends on BFIN_KERNEL_CLOCK
490 This sets the frequency of the system clock (including SDRAM or DDR).
491 This can be between 1 and 15
492 System Clock = (PLL frequency) / (this setting)
495 prompt "DDR SDRAM Chip Type"
496 depends on BFIN_KERNEL_CLOCK
498 default MEM_MT46V32M16_5B
500 config MEM_MT46V32M16_6T
503 config MEM_MT46V32M16_5B
508 prompt "DDR/SDRAM Timing"
509 depends on BFIN_KERNEL_CLOCK
510 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
512 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
513 The calculated SDRAM timing parameters may not be 100%
514 accurate - This option is therefore marked experimental.
516 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
517 bool "Calculate Timings (EXPERIMENTAL)"
518 depends on EXPERIMENTAL
520 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
521 bool "Provide accurate Timings based on target SCLK"
523 Please consult the Blackfin Hardware Reference Manuals as well
524 as the memory device datasheet.
525 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
528 menu "Memory Init Control"
529 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
546 config MEM_EBIU_DDRQUE
563 # Max & Min Speeds for various Chips
567 default 400000000 if BF512
568 default 400000000 if BF514
569 default 400000000 if BF516
570 default 400000000 if BF518
571 default 400000000 if BF522
572 default 600000000 if BF523
573 default 400000000 if BF524
574 default 600000000 if BF525
575 default 400000000 if BF526
576 default 600000000 if BF527
577 default 400000000 if BF531
578 default 400000000 if BF532
579 default 750000000 if BF533
580 default 500000000 if BF534
581 default 400000000 if BF536
582 default 600000000 if BF537
583 default 533333333 if BF538
584 default 533333333 if BF539
585 default 600000000 if BF542
586 default 533333333 if BF544
587 default 600000000 if BF547
588 default 600000000 if BF548
589 default 533333333 if BF549
590 default 600000000 if BF561
604 comment "Kernel Timer/Scheduler"
606 source kernel/Kconfig.hz
608 config GENERIC_CLOCKEVENTS
609 bool "Generic clock events"
612 menu "Clock event device"
613 depends on GENERIC_CLOCKEVENTS
614 config TICKSOURCE_GPTMR0
619 config TICKSOURCE_CORETMR
625 depends on GENERIC_CLOCKEVENTS
626 config CYCLES_CLOCKSOURCE
629 depends on !BFIN_SCRATCH_REG_CYCLES
632 If you say Y here, you will enable support for using the 'cycles'
633 registers as a clock source. Doing so means you will be unable to
634 safely write to the 'cycles' register during runtime. You will
635 still be able to read it (such as for performance monitoring), but
636 writing the registers will most likely crash the kernel.
638 config GPTMR0_CLOCKSOURCE
641 depends on !TICKSOURCE_GPTMR0
644 config ARCH_USES_GETTIMEOFFSET
645 depends on !GENERIC_CLOCKEVENTS
648 source kernel/time/Kconfig
653 prompt "Blackfin Exception Scratch Register"
654 default BFIN_SCRATCH_REG_RETN
656 Select the resource to reserve for the Exception handler:
657 - RETN: Non-Maskable Interrupt (NMI)
658 - RETE: Exception Return (JTAG/ICE)
659 - CYCLES: Performance counter
661 If you are unsure, please select "RETN".
663 config BFIN_SCRATCH_REG_RETN
666 Use the RETN register in the Blackfin exception handler
667 as a stack scratch register. This means you cannot
668 safely use NMI on the Blackfin while running Linux, but
669 you can debug the system with a JTAG ICE and use the
670 CYCLES performance registers.
672 If you are unsure, please select "RETN".
674 config BFIN_SCRATCH_REG_RETE
677 Use the RETE register in the Blackfin exception handler
678 as a stack scratch register. This means you cannot
679 safely use a JTAG ICE while debugging a Blackfin board,
680 but you can safely use the CYCLES performance registers
683 If you are unsure, please select "RETN".
685 config BFIN_SCRATCH_REG_CYCLES
688 Use the CYCLES register in the Blackfin exception handler
689 as a stack scratch register. This means you cannot
690 safely use the CYCLES performance registers on a Blackfin
691 board at anytime, but you can debug the system with a JTAG
694 If you are unsure, please select "RETN".
701 menu "Blackfin Kernel Optimizations"
704 comment "Memory Optimizations"
707 bool "Locate interrupt entry code in L1 Memory"
710 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
711 into L1 instruction memory. (less latency)
713 config EXCPT_IRQ_SYSC_L1
714 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
717 If enabled, the entire ASM lowlevel exception and interrupt entry code
718 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
722 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
725 If enabled, the frequently called do_irq dispatcher function is linked
726 into L1 instruction memory. (less latency)
728 config CORE_TIMER_IRQ_L1
729 bool "Locate frequently called timer_interrupt() function in L1 Memory"
732 If enabled, the frequently called timer_interrupt() function is linked
733 into L1 instruction memory. (less latency)
736 bool "Locate frequently idle function in L1 Memory"
739 If enabled, the frequently called idle function is linked
740 into L1 instruction memory. (less latency)
743 bool "Locate kernel schedule function in L1 Memory"
746 If enabled, the frequently called kernel schedule is linked
747 into L1 instruction memory. (less latency)
749 config ARITHMETIC_OPS_L1
750 bool "Locate kernel owned arithmetic functions in L1 Memory"
753 If enabled, arithmetic functions are linked
754 into L1 instruction memory. (less latency)
757 bool "Locate access_ok function in L1 Memory"
760 If enabled, the access_ok function is linked
761 into L1 instruction memory. (less latency)
764 bool "Locate memset function in L1 Memory"
767 If enabled, the memset function is linked
768 into L1 instruction memory. (less latency)
771 bool "Locate memcpy function in L1 Memory"
774 If enabled, the memcpy function is linked
775 into L1 instruction memory. (less latency)
778 bool "locate strcmp function in L1 Memory"
781 If enabled, the strcmp function is linked
782 into L1 instruction memory (less latency).
785 bool "locate strncmp function in L1 Memory"
788 If enabled, the strncmp function is linked
789 into L1 instruction memory (less latency).
792 bool "locate strcpy function in L1 Memory"
795 If enabled, the strcpy function is linked
796 into L1 instruction memory (less latency).
799 bool "locate strncpy function in L1 Memory"
802 If enabled, the strncpy function is linked
803 into L1 instruction memory (less latency).
805 config SYS_BFIN_SPINLOCK_L1
806 bool "Locate sys_bfin_spinlock function in L1 Memory"
809 If enabled, sys_bfin_spinlock function is linked
810 into L1 instruction memory. (less latency)
812 config IP_CHECKSUM_L1
813 bool "Locate IP Checksum function in L1 Memory"
816 If enabled, the IP Checksum function is linked
817 into L1 instruction memory. (less latency)
819 config CACHELINE_ALIGNED_L1
820 bool "Locate cacheline_aligned data to L1 Data Memory"
825 If enabled, cacheline_aligned data is linked
826 into L1 data memory. (less latency)
828 config SYSCALL_TAB_L1
829 bool "Locate Syscall Table L1 Data Memory"
833 If enabled, the Syscall LUT is linked
834 into L1 data memory. (less latency)
836 config CPLB_SWITCH_TAB_L1
837 bool "Locate CPLB Switch Tables L1 Data Memory"
841 If enabled, the CPLB Switch Tables are linked
842 into L1 data memory. (less latency)
844 config CACHE_FLUSH_L1
845 bool "Locate cache flush funcs in L1 Inst Memory"
848 If enabled, the Blackfin cache flushing functions are linked
849 into L1 instruction memory.
851 Note that this might be required to address anomalies, but
852 these functions are pretty small, so it shouldn't be too bad.
853 If you are using a processor affected by an anomaly, the build
854 system will double check for you and prevent it.
857 bool "Support locating application stack in L1 Scratch Memory"
860 If enabled the application stack can be located in L1
861 scratch memory (less latency).
863 Currently only works with FLAT binaries.
865 config EXCEPTION_L1_SCRATCH
866 bool "Locate exception stack in L1 Scratch Memory"
868 depends on !APP_STACK_L1
870 Whenever an exception occurs, use the L1 Scratch memory for
871 stack storage. You cannot place the stacks of FLAT binaries
872 in L1 when using this option.
874 If you don't use L1 Scratch, then you should say Y here.
876 comment "Speed Optimizations"
877 config BFIN_INS_LOWOVERHEAD
878 bool "ins[bwl] low overhead, higher interrupt latency"
881 Reads on the Blackfin are speculative. In Blackfin terms, this means
882 they can be interrupted at any time (even after they have been issued
883 on to the external bus), and re-issued after the interrupt occurs.
884 For memory - this is not a big deal, since memory does not change if
887 If a FIFO is sitting on the end of the read, it will see two reads,
888 when the core only sees one since the FIFO receives both the read
889 which is cancelled (and not delivered to the core) and the one which
890 is re-issued (which is delivered to the core).
892 To solve this, interrupts are turned off before reads occur to
893 I/O space. This option controls which the overhead/latency of
894 controlling interrupts during this time
895 "n" turns interrupts off every read
896 (higher overhead, but lower interrupt latency)
897 "y" turns interrupts off every loop
898 (low overhead, but longer interrupt latency)
900 default behavior is to leave this set to on (type "Y"). If you are experiencing
901 interrupt latency issues, it is safe and OK to turn this off.
906 prompt "Kernel executes from"
908 Choose the memory type that the kernel will be running in.
913 The kernel will be resident in RAM when running.
918 The kernel will be resident in FLASH/ROM when running.
925 tristate "Enable Blackfin General Purpose Timers API"
928 Enable support for the General Purpose Timers API. If you
931 To compile this driver as a module, choose M here: the module
932 will be called gptimers.
935 prompt "Uncached DMA region"
936 default DMA_UNCACHED_1M
937 config DMA_UNCACHED_4M
938 bool "Enable 4M DMA region"
939 config DMA_UNCACHED_2M
940 bool "Enable 2M DMA region"
941 config DMA_UNCACHED_1M
942 bool "Enable 1M DMA region"
943 config DMA_UNCACHED_512K
944 bool "Enable 512K DMA region"
945 config DMA_UNCACHED_256K
946 bool "Enable 256K DMA region"
947 config DMA_UNCACHED_128K
948 bool "Enable 128K DMA region"
949 config DMA_UNCACHED_NONE
950 bool "Disable DMA region"
954 comment "Cache Support"
959 config BFIN_EXTMEM_ICACHEABLE
960 bool "Enable ICACHE for external memory"
961 depends on BFIN_ICACHE
963 config BFIN_L2_ICACHEABLE
964 bool "Enable ICACHE for L2 SRAM"
965 depends on BFIN_ICACHE
966 depends on BF54x || BF561
972 config BFIN_DCACHE_BANKA
973 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
974 depends on BFIN_DCACHE && !BF531
976 config BFIN_EXTMEM_DCACHEABLE
977 bool "Enable DCACHE for external memory"
978 depends on BFIN_DCACHE
981 prompt "External memory DCACHE policy"
982 depends on BFIN_EXTMEM_DCACHEABLE
983 default BFIN_EXTMEM_WRITEBACK if !SMP
984 default BFIN_EXTMEM_WRITETHROUGH if SMP
985 config BFIN_EXTMEM_WRITEBACK
990 Cached data will be written back to SDRAM only when needed.
991 This can give a nice increase in performance, but beware of
992 broken drivers that do not properly invalidate/flush their
995 Write Through Policy:
996 Cached data will always be written back to SDRAM when the
997 cache is updated. This is a completely safe setting, but
998 performance is worse than Write Back.
1000 If you are unsure of the options and you want to be safe,
1001 then go with Write Through.
1003 config BFIN_EXTMEM_WRITETHROUGH
1004 bool "Write through"
1007 Cached data will be written back to SDRAM only when needed.
1008 This can give a nice increase in performance, but beware of
1009 broken drivers that do not properly invalidate/flush their
1012 Write Through Policy:
1013 Cached data will always be written back to SDRAM when the
1014 cache is updated. This is a completely safe setting, but
1015 performance is worse than Write Back.
1017 If you are unsure of the options and you want to be safe,
1018 then go with Write Through.
1022 config BFIN_L2_DCACHEABLE
1023 bool "Enable DCACHE for L2 SRAM"
1024 depends on BFIN_DCACHE
1025 depends on (BF54x || BF561) && !SMP
1028 prompt "L2 SRAM DCACHE policy"
1029 depends on BFIN_L2_DCACHEABLE
1030 default BFIN_L2_WRITEBACK
1031 config BFIN_L2_WRITEBACK
1034 config BFIN_L2_WRITETHROUGH
1035 bool "Write through"
1039 comment "Memory Protection Unit"
1041 bool "Enable the memory protection unit (EXPERIMENTAL)"
1044 Use the processor's MPU to protect applications from accessing
1045 memory they do not own. This comes at a performance penalty
1046 and is recommended only for debugging.
1048 comment "Asynchronous Memory Configuration"
1050 menu "EBIU_AMGCTL Global Control"
1052 bool "Enable CLKOUT"
1056 bool "DMA has priority over core for ext. accesses"
1061 bool "Bank 0 16 bit packing enable"
1066 bool "Bank 1 16 bit packing enable"
1071 bool "Bank 2 16 bit packing enable"
1076 bool "Bank 3 16 bit packing enable"
1080 prompt "Enable Asynchronous Memory Banks"
1084 bool "Disable All Banks"
1087 bool "Enable Bank 0"
1089 config C_AMBEN_B0_B1
1090 bool "Enable Bank 0 & 1"
1092 config C_AMBEN_B0_B1_B2
1093 bool "Enable Bank 0 & 1 & 2"
1096 bool "Enable All Banks"
1100 menu "EBIU_AMBCTL Control"
1102 hex "Bank 0 (AMBCTL0.L)"
1105 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1106 used to control the Asynchronous Memory Bank 0 settings.
1109 hex "Bank 1 (AMBCTL0.H)"
1111 default 0x5558 if BF54x
1113 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1114 used to control the Asynchronous Memory Bank 1 settings.
1117 hex "Bank 2 (AMBCTL1.L)"
1120 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1121 used to control the Asynchronous Memory Bank 2 settings.
1124 hex "Bank 3 (AMBCTL1.H)"
1127 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1128 used to control the Asynchronous Memory Bank 3 settings.
1132 config EBIU_MBSCTLVAL
1133 hex "EBIU Bank Select Control Register"
1138 hex "Flash Memory Mode Control Register"
1143 hex "Flash Memory Bank Control Register"
1148 #############################################################################
1149 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1155 Support for PCI bus.
1157 source "drivers/pci/Kconfig"
1159 source "drivers/pcmcia/Kconfig"
1161 source "drivers/pci/hotplug/Kconfig"
1165 menu "Executable file formats"
1167 source "fs/Kconfig.binfmt"
1171 menu "Power management options"
1173 source "kernel/power/Kconfig"
1175 config ARCH_SUSPEND_POSSIBLE
1179 prompt "Standby Power Saving Mode"
1181 default PM_BFIN_SLEEP_DEEPER
1182 config PM_BFIN_SLEEP_DEEPER
1185 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1186 power dissipation by disabling the clock to the processor core (CCLK).
1187 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1188 to 0.85 V to provide the greatest power savings, while preserving the
1190 The PLL and system clock (SCLK) continue to operate at a very low
1191 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1192 the SDRAM is put into Self Refresh Mode. Typically an external event
1193 such as GPIO interrupt or RTC activity wakes up the processor.
1194 Various Peripherals such as UART, SPORT, PPI may not function as
1195 normal during Sleep Deeper, due to the reduced SCLK frequency.
1196 When in the sleep mode, system DMA access to L1 memory is not supported.
1198 If unsure, select "Sleep Deeper".
1200 config PM_BFIN_SLEEP
1203 Sleep Mode (High Power Savings) - The sleep mode reduces power
1204 dissipation by disabling the clock to the processor core (CCLK).
1205 The PLL and system clock (SCLK), however, continue to operate in
1206 this mode. Typically an external event or RTC activity will wake
1207 up the processor. When in the sleep mode, system DMA access to L1
1208 memory is not supported.
1210 If unsure, select "Sleep Deeper".
1213 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1216 config PM_BFIN_WAKE_PH6
1217 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1218 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1221 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1223 config PM_BFIN_WAKE_GP
1224 bool "Allow Wake-Up from GPIOs"
1225 depends on PM && BF54x
1228 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1229 (all processors, except ADSP-BF549). This option sets
1230 the general-purpose wake-up enable (GPWE) control bit to enable
1231 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1232 On ADSP-BF549 this option enables the the same functionality on the
1233 /MRXON pin also PH7.
1237 menu "CPU Frequency scaling"
1239 source "drivers/cpufreq/Kconfig"
1241 config BFIN_CPU_FREQ
1244 select CPU_FREQ_TABLE
1248 bool "CPU Voltage scaling"
1249 depends on EXPERIMENTAL
1253 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1254 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1255 manuals. There is a theoretical risk that during VDDINT transitions
1260 source "net/Kconfig"
1262 source "drivers/Kconfig"
1264 source "drivers/firmware/Kconfig"
1268 source "arch/blackfin/Kconfig.debug"
1270 source "security/Kconfig"
1272 source "crypto/Kconfig"
1274 source "lib/Kconfig"