2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
18 config RWSEM_GENERIC_SPINLOCK
21 config RWSEM_XCHGADD_ALGORITHM
27 select HAVE_ARCH_TRACEHOOK
28 select HAVE_DYNAMIC_FTRACE
29 select HAVE_FTRACE_MCOUNT_RECORD
30 select HAVE_FUNCTION_GRAPH_TRACER
31 select HAVE_FUNCTION_TRACER
32 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
34 select HAVE_KERNEL_GZIP if RAMKERNEL
35 select HAVE_KERNEL_BZIP2 if RAMKERNEL
36 select HAVE_KERNEL_LZMA if RAMKERNEL
37 select HAVE_KERNEL_LZO if RAMKERNEL
39 select ARCH_WANT_OPTIONAL_GPIOLIB
51 config GENERIC_FIND_NEXT_BIT
54 config GENERIC_HARDIRQS
57 config GENERIC_IRQ_PROBE
60 config GENERIC_HARDIRQS_NO__DO_IRQ
66 config FORCE_MAX_ZONEORDER
70 config GENERIC_CALIBRATE_DELAY
73 config LOCKDEP_SUPPORT
76 config STACKTRACE_SUPPORT
79 config TRACE_IRQFLAGS_SUPPORT
84 source "kernel/Kconfig.preempt"
86 source "kernel/Kconfig.freezer"
88 menu "Blackfin Processor Options"
90 comment "Processor and Board Settings"
99 BF512 Processor Support.
104 BF514 Processor Support.
109 BF516 Processor Support.
114 BF518 Processor Support.
119 BF522 Processor Support.
124 BF523 Processor Support.
129 BF524 Processor Support.
134 BF525 Processor Support.
139 BF526 Processor Support.
144 BF527 Processor Support.
149 BF531 Processor Support.
154 BF532 Processor Support.
159 BF533 Processor Support.
164 BF534 Processor Support.
169 BF536 Processor Support.
174 BF537 Processor Support.
179 BF538 Processor Support.
184 BF539 Processor Support.
189 BF542 Processor Support.
194 BF542 Processor Support.
199 BF544 Processor Support.
204 BF544 Processor Support.
209 BF547 Processor Support.
214 BF547 Processor Support.
219 BF548 Processor Support.
224 BF548 Processor Support.
229 BF549 Processor Support.
234 BF549 Processor Support.
239 BF561 Processor Support.
245 select TICKSOURCE_CORETMR
246 bool "Symmetric multi-processing support"
248 This enables support for systems with more than one CPU,
249 like the dual core BF561. If you have a system with only one
250 CPU, say N. If you have a system with more than one CPU, say Y.
252 If you don't know what to do here, say N.
260 bool "Support for hot-pluggable CPUs"
261 depends on SMP && HOTPLUG
269 config HAVE_LEGACY_PER_CPU_AREA
275 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
276 default 2 if (BF537 || BF536 || BF534)
277 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
278 default 4 if (BF538 || BF539)
282 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
283 default 3 if (BF537 || BF536 || BF534 || BF54xM)
284 default 5 if (BF561 || BF538 || BF539)
285 default 6 if (BF533 || BF532 || BF531)
289 default BF_REV_0_0 if (BF51x || BF52x)
290 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
291 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
295 depends on (BF51x || BF52x || (BF54x && !BF54xM))
299 depends on (BF51x || BF52x || (BF54x && !BF54xM))
303 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
307 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
311 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
315 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
319 depends on (BF533 || BF532 || BF531)
331 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
334 config MEM_MT48LC64M4A2FB_7E
336 depends on (BFIN533_STAMP)
339 config MEM_MT48LC16M16A2TG_75
341 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
342 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
343 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
344 || BFIN527_BLUETECHNIX_CM)
347 config MEM_MT48LC32M8A2_75
349 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
352 config MEM_MT48LC8M32B2B5_7
354 depends on (BFIN561_BLUETECHNIX_CM)
357 config MEM_MT48LC32M16A2TG_75
359 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
362 config MEM_MT48H32M16LFCJ_75
364 depends on (BFIN526_EZBRD)
367 source "arch/blackfin/mach-bf518/Kconfig"
368 source "arch/blackfin/mach-bf527/Kconfig"
369 source "arch/blackfin/mach-bf533/Kconfig"
370 source "arch/blackfin/mach-bf561/Kconfig"
371 source "arch/blackfin/mach-bf537/Kconfig"
372 source "arch/blackfin/mach-bf538/Kconfig"
373 source "arch/blackfin/mach-bf548/Kconfig"
375 menu "Board customizations"
378 bool "Default bootloader kernel arguments"
381 string "Initial kernel command string"
382 depends on CMDLINE_BOOL
383 default "console=ttyBF0,57600"
385 If you don't have a boot loader capable of passing a command line string
386 to the kernel, you may specify one here. As a minimum, you should specify
387 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
390 hex "Kernel load address for booting"
392 range 0x1000 0x20000000
394 This option allows you to set the load address of the kernel.
395 This can be useful if you are on a board which has a small amount
396 of memory or you wish to reserve some memory at the beginning of
399 Note that you need to keep this value above 4k (0x1000) as this
400 memory region is used to capture NULL pointer references as well
401 as some core kernel functions.
404 hex "Kernel ROM Base"
407 range 0x20000000 0x20400000 if !(BF54x || BF561)
408 range 0x20000000 0x30000000 if (BF54x || BF561)
410 Make sure your ROM base does not include any file-header
411 information that is prepended to the kernel.
413 For example, the bootable U-Boot format (created with
414 mkimage) has a 64 byte header (0x40). So while the image
415 you write to flash might start at say 0x20080000, you have
416 to add 0x40 to get the kernel's ROM base as it will come
419 comment "Clock/PLL Setup"
422 int "Frequency of the crystal on the board in Hz"
423 default "10000000" if BFIN532_IP0X
424 default "11059200" if BFIN533_STAMP
425 default "24576000" if PNAV10
426 default "25000000" # most people use this
427 default "27000000" if BFIN533_EZKIT
428 default "30000000" if BFIN561_EZKIT
429 default "24000000" if BFIN527_AD7160EVAL
431 The frequency of CLKIN crystal oscillator on the board in Hz.
432 Warning: This value should match the crystal on the board. Otherwise,
433 peripherals won't work properly.
435 config BFIN_KERNEL_CLOCK
436 bool "Re-program Clocks while Kernel boots?"
439 This option decides if kernel clocks are re-programed from the
440 bootloader settings. If the clocks are not set, the SDRAM settings
441 are also not changed, and the Bootloader does 100% of the hardware
446 depends on BFIN_KERNEL_CLOCK
451 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
454 If this is set the clock will be divided by 2, before it goes to the PLL.
458 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
460 default "22" if BFIN533_EZKIT
461 default "45" if BFIN533_STAMP
462 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
463 default "22" if BFIN533_BLUETECHNIX_CM
464 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
465 default "20" if BFIN561_EZKIT
466 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
467 default "25" if BFIN527_AD7160EVAL
469 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
470 PLL Frequency = (Crystal Frequency) * (this setting)
473 prompt "Core Clock Divider"
474 depends on BFIN_KERNEL_CLOCK
477 This sets the frequency of the core. It can be 1, 2, 4 or 8
478 Core Frequency = (PLL frequency) / (this setting)
494 int "System Clock Divider"
495 depends on BFIN_KERNEL_CLOCK
499 This sets the frequency of the system clock (including SDRAM or DDR).
500 This can be between 1 and 15
501 System Clock = (PLL frequency) / (this setting)
504 prompt "DDR SDRAM Chip Type"
505 depends on BFIN_KERNEL_CLOCK
507 default MEM_MT46V32M16_5B
509 config MEM_MT46V32M16_6T
512 config MEM_MT46V32M16_5B
517 prompt "DDR/SDRAM Timing"
518 depends on BFIN_KERNEL_CLOCK
519 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
521 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
522 The calculated SDRAM timing parameters may not be 100%
523 accurate - This option is therefore marked experimental.
525 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
526 bool "Calculate Timings (EXPERIMENTAL)"
527 depends on EXPERIMENTAL
529 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
530 bool "Provide accurate Timings based on target SCLK"
532 Please consult the Blackfin Hardware Reference Manuals as well
533 as the memory device datasheet.
534 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
537 menu "Memory Init Control"
538 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
555 config MEM_EBIU_DDRQUE
572 # Max & Min Speeds for various Chips
576 default 400000000 if BF512
577 default 400000000 if BF514
578 default 400000000 if BF516
579 default 400000000 if BF518
580 default 400000000 if BF522
581 default 600000000 if BF523
582 default 400000000 if BF524
583 default 600000000 if BF525
584 default 400000000 if BF526
585 default 600000000 if BF527
586 default 400000000 if BF531
587 default 400000000 if BF532
588 default 750000000 if BF533
589 default 500000000 if BF534
590 default 400000000 if BF536
591 default 600000000 if BF537
592 default 533333333 if BF538
593 default 533333333 if BF539
594 default 600000000 if BF542
595 default 533333333 if BF544
596 default 600000000 if BF547
597 default 600000000 if BF548
598 default 533333333 if BF549
599 default 600000000 if BF561
613 comment "Kernel Timer/Scheduler"
615 source kernel/Kconfig.hz
617 config GENERIC_CLOCKEVENTS
618 bool "Generic clock events"
621 menu "Clock event device"
622 depends on GENERIC_CLOCKEVENTS
623 config TICKSOURCE_GPTMR0
628 config TICKSOURCE_CORETMR
634 depends on GENERIC_CLOCKEVENTS
635 config CYCLES_CLOCKSOURCE
638 depends on !BFIN_SCRATCH_REG_CYCLES
641 If you say Y here, you will enable support for using the 'cycles'
642 registers as a clock source. Doing so means you will be unable to
643 safely write to the 'cycles' register during runtime. You will
644 still be able to read it (such as for performance monitoring), but
645 writing the registers will most likely crash the kernel.
647 config GPTMR0_CLOCKSOURCE
650 depends on !TICKSOURCE_GPTMR0
653 config ARCH_USES_GETTIMEOFFSET
654 depends on !GENERIC_CLOCKEVENTS
657 source kernel/time/Kconfig
662 prompt "Blackfin Exception Scratch Register"
663 default BFIN_SCRATCH_REG_RETN
665 Select the resource to reserve for the Exception handler:
666 - RETN: Non-Maskable Interrupt (NMI)
667 - RETE: Exception Return (JTAG/ICE)
668 - CYCLES: Performance counter
670 If you are unsure, please select "RETN".
672 config BFIN_SCRATCH_REG_RETN
675 Use the RETN register in the Blackfin exception handler
676 as a stack scratch register. This means you cannot
677 safely use NMI on the Blackfin while running Linux, but
678 you can debug the system with a JTAG ICE and use the
679 CYCLES performance registers.
681 If you are unsure, please select "RETN".
683 config BFIN_SCRATCH_REG_RETE
686 Use the RETE register in the Blackfin exception handler
687 as a stack scratch register. This means you cannot
688 safely use a JTAG ICE while debugging a Blackfin board,
689 but you can safely use the CYCLES performance registers
692 If you are unsure, please select "RETN".
694 config BFIN_SCRATCH_REG_CYCLES
697 Use the CYCLES register in the Blackfin exception handler
698 as a stack scratch register. This means you cannot
699 safely use the CYCLES performance registers on a Blackfin
700 board at anytime, but you can debug the system with a JTAG
703 If you are unsure, please select "RETN".
710 menu "Blackfin Kernel Optimizations"
713 comment "Memory Optimizations"
716 bool "Locate interrupt entry code in L1 Memory"
719 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
720 into L1 instruction memory. (less latency)
722 config EXCPT_IRQ_SYSC_L1
723 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
726 If enabled, the entire ASM lowlevel exception and interrupt entry code
727 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
731 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
734 If enabled, the frequently called do_irq dispatcher function is linked
735 into L1 instruction memory. (less latency)
737 config CORE_TIMER_IRQ_L1
738 bool "Locate frequently called timer_interrupt() function in L1 Memory"
741 If enabled, the frequently called timer_interrupt() function is linked
742 into L1 instruction memory. (less latency)
745 bool "Locate frequently idle function in L1 Memory"
748 If enabled, the frequently called idle function is linked
749 into L1 instruction memory. (less latency)
752 bool "Locate kernel schedule function in L1 Memory"
755 If enabled, the frequently called kernel schedule is linked
756 into L1 instruction memory. (less latency)
758 config ARITHMETIC_OPS_L1
759 bool "Locate kernel owned arithmetic functions in L1 Memory"
762 If enabled, arithmetic functions are linked
763 into L1 instruction memory. (less latency)
766 bool "Locate access_ok function in L1 Memory"
769 If enabled, the access_ok function is linked
770 into L1 instruction memory. (less latency)
773 bool "Locate memset function in L1 Memory"
776 If enabled, the memset function is linked
777 into L1 instruction memory. (less latency)
780 bool "Locate memcpy function in L1 Memory"
783 If enabled, the memcpy function is linked
784 into L1 instruction memory. (less latency)
787 bool "locate strcmp function in L1 Memory"
790 If enabled, the strcmp function is linked
791 into L1 instruction memory (less latency).
794 bool "locate strncmp function in L1 Memory"
797 If enabled, the strncmp function is linked
798 into L1 instruction memory (less latency).
801 bool "locate strcpy function in L1 Memory"
804 If enabled, the strcpy function is linked
805 into L1 instruction memory (less latency).
808 bool "locate strncpy function in L1 Memory"
811 If enabled, the strncpy function is linked
812 into L1 instruction memory (less latency).
814 config SYS_BFIN_SPINLOCK_L1
815 bool "Locate sys_bfin_spinlock function in L1 Memory"
818 If enabled, sys_bfin_spinlock function is linked
819 into L1 instruction memory. (less latency)
821 config IP_CHECKSUM_L1
822 bool "Locate IP Checksum function in L1 Memory"
825 If enabled, the IP Checksum function is linked
826 into L1 instruction memory. (less latency)
828 config CACHELINE_ALIGNED_L1
829 bool "Locate cacheline_aligned data to L1 Data Memory"
834 If enabled, cacheline_aligned data is linked
835 into L1 data memory. (less latency)
837 config SYSCALL_TAB_L1
838 bool "Locate Syscall Table L1 Data Memory"
842 If enabled, the Syscall LUT is linked
843 into L1 data memory. (less latency)
845 config CPLB_SWITCH_TAB_L1
846 bool "Locate CPLB Switch Tables L1 Data Memory"
850 If enabled, the CPLB Switch Tables are linked
851 into L1 data memory. (less latency)
853 config CACHE_FLUSH_L1
854 bool "Locate cache flush funcs in L1 Inst Memory"
857 If enabled, the Blackfin cache flushing functions are linked
858 into L1 instruction memory.
860 Note that this might be required to address anomalies, but
861 these functions are pretty small, so it shouldn't be too bad.
862 If you are using a processor affected by an anomaly, the build
863 system will double check for you and prevent it.
866 bool "Support locating application stack in L1 Scratch Memory"
869 If enabled the application stack can be located in L1
870 scratch memory (less latency).
872 Currently only works with FLAT binaries.
874 config EXCEPTION_L1_SCRATCH
875 bool "Locate exception stack in L1 Scratch Memory"
877 depends on !APP_STACK_L1
879 Whenever an exception occurs, use the L1 Scratch memory for
880 stack storage. You cannot place the stacks of FLAT binaries
881 in L1 when using this option.
883 If you don't use L1 Scratch, then you should say Y here.
885 comment "Speed Optimizations"
886 config BFIN_INS_LOWOVERHEAD
887 bool "ins[bwl] low overhead, higher interrupt latency"
890 Reads on the Blackfin are speculative. In Blackfin terms, this means
891 they can be interrupted at any time (even after they have been issued
892 on to the external bus), and re-issued after the interrupt occurs.
893 For memory - this is not a big deal, since memory does not change if
896 If a FIFO is sitting on the end of the read, it will see two reads,
897 when the core only sees one since the FIFO receives both the read
898 which is cancelled (and not delivered to the core) and the one which
899 is re-issued (which is delivered to the core).
901 To solve this, interrupts are turned off before reads occur to
902 I/O space. This option controls which the overhead/latency of
903 controlling interrupts during this time
904 "n" turns interrupts off every read
905 (higher overhead, but lower interrupt latency)
906 "y" turns interrupts off every loop
907 (low overhead, but longer interrupt latency)
909 default behavior is to leave this set to on (type "Y"). If you are experiencing
910 interrupt latency issues, it is safe and OK to turn this off.
915 prompt "Kernel executes from"
917 Choose the memory type that the kernel will be running in.
922 The kernel will be resident in RAM when running.
927 The kernel will be resident in FLASH/ROM when running.
931 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
940 tristate "Enable Blackfin General Purpose Timers API"
943 Enable support for the General Purpose Timers API. If you
946 To compile this driver as a module, choose M here: the module
947 will be called gptimers.
950 prompt "Uncached DMA region"
951 default DMA_UNCACHED_1M
952 config DMA_UNCACHED_4M
953 bool "Enable 4M DMA region"
954 config DMA_UNCACHED_2M
955 bool "Enable 2M DMA region"
956 config DMA_UNCACHED_1M
957 bool "Enable 1M DMA region"
958 config DMA_UNCACHED_512K
959 bool "Enable 512K DMA region"
960 config DMA_UNCACHED_256K
961 bool "Enable 256K DMA region"
962 config DMA_UNCACHED_128K
963 bool "Enable 128K DMA region"
964 config DMA_UNCACHED_NONE
965 bool "Disable DMA region"
969 comment "Cache Support"
974 config BFIN_EXTMEM_ICACHEABLE
975 bool "Enable ICACHE for external memory"
976 depends on BFIN_ICACHE
978 config BFIN_L2_ICACHEABLE
979 bool "Enable ICACHE for L2 SRAM"
980 depends on BFIN_ICACHE
981 depends on BF54x || BF561
987 config BFIN_DCACHE_BANKA
988 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
989 depends on BFIN_DCACHE && !BF531
991 config BFIN_EXTMEM_DCACHEABLE
992 bool "Enable DCACHE for external memory"
993 depends on BFIN_DCACHE
996 prompt "External memory DCACHE policy"
997 depends on BFIN_EXTMEM_DCACHEABLE
998 default BFIN_EXTMEM_WRITEBACK if !SMP
999 default BFIN_EXTMEM_WRITETHROUGH if SMP
1000 config BFIN_EXTMEM_WRITEBACK
1005 Cached data will be written back to SDRAM only when needed.
1006 This can give a nice increase in performance, but beware of
1007 broken drivers that do not properly invalidate/flush their
1010 Write Through Policy:
1011 Cached data will always be written back to SDRAM when the
1012 cache is updated. This is a completely safe setting, but
1013 performance is worse than Write Back.
1015 If you are unsure of the options and you want to be safe,
1016 then go with Write Through.
1018 config BFIN_EXTMEM_WRITETHROUGH
1019 bool "Write through"
1022 Cached data will be written back to SDRAM only when needed.
1023 This can give a nice increase in performance, but beware of
1024 broken drivers that do not properly invalidate/flush their
1027 Write Through Policy:
1028 Cached data will always be written back to SDRAM when the
1029 cache is updated. This is a completely safe setting, but
1030 performance is worse than Write Back.
1032 If you are unsure of the options and you want to be safe,
1033 then go with Write Through.
1037 config BFIN_L2_DCACHEABLE
1038 bool "Enable DCACHE for L2 SRAM"
1039 depends on BFIN_DCACHE
1040 depends on (BF54x || BF561) && !SMP
1043 prompt "L2 SRAM DCACHE policy"
1044 depends on BFIN_L2_DCACHEABLE
1045 default BFIN_L2_WRITEBACK
1046 config BFIN_L2_WRITEBACK
1049 config BFIN_L2_WRITETHROUGH
1050 bool "Write through"
1054 comment "Memory Protection Unit"
1056 bool "Enable the memory protection unit (EXPERIMENTAL)"
1059 Use the processor's MPU to protect applications from accessing
1060 memory they do not own. This comes at a performance penalty
1061 and is recommended only for debugging.
1063 comment "Asynchronous Memory Configuration"
1065 menu "EBIU_AMGCTL Global Control"
1067 bool "Enable CLKOUT"
1071 bool "DMA has priority over core for ext. accesses"
1076 bool "Bank 0 16 bit packing enable"
1081 bool "Bank 1 16 bit packing enable"
1086 bool "Bank 2 16 bit packing enable"
1091 bool "Bank 3 16 bit packing enable"
1095 prompt "Enable Asynchronous Memory Banks"
1099 bool "Disable All Banks"
1102 bool "Enable Bank 0"
1104 config C_AMBEN_B0_B1
1105 bool "Enable Bank 0 & 1"
1107 config C_AMBEN_B0_B1_B2
1108 bool "Enable Bank 0 & 1 & 2"
1111 bool "Enable All Banks"
1115 menu "EBIU_AMBCTL Control"
1117 hex "Bank 0 (AMBCTL0.L)"
1120 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1121 used to control the Asynchronous Memory Bank 0 settings.
1124 hex "Bank 1 (AMBCTL0.H)"
1126 default 0x5558 if BF54x
1128 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1129 used to control the Asynchronous Memory Bank 1 settings.
1132 hex "Bank 2 (AMBCTL1.L)"
1135 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1136 used to control the Asynchronous Memory Bank 2 settings.
1139 hex "Bank 3 (AMBCTL1.H)"
1142 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1143 used to control the Asynchronous Memory Bank 3 settings.
1147 config EBIU_MBSCTLVAL
1148 hex "EBIU Bank Select Control Register"
1153 hex "Flash Memory Mode Control Register"
1158 hex "Flash Memory Bank Control Register"
1163 #############################################################################
1164 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1170 Support for PCI bus.
1172 source "drivers/pci/Kconfig"
1174 source "drivers/pcmcia/Kconfig"
1176 source "drivers/pci/hotplug/Kconfig"
1180 menu "Executable file formats"
1182 source "fs/Kconfig.binfmt"
1186 menu "Power management options"
1188 source "kernel/power/Kconfig"
1190 config ARCH_SUSPEND_POSSIBLE
1194 prompt "Standby Power Saving Mode"
1196 default PM_BFIN_SLEEP_DEEPER
1197 config PM_BFIN_SLEEP_DEEPER
1200 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1201 power dissipation by disabling the clock to the processor core (CCLK).
1202 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1203 to 0.85 V to provide the greatest power savings, while preserving the
1205 The PLL and system clock (SCLK) continue to operate at a very low
1206 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1207 the SDRAM is put into Self Refresh Mode. Typically an external event
1208 such as GPIO interrupt or RTC activity wakes up the processor.
1209 Various Peripherals such as UART, SPORT, PPI may not function as
1210 normal during Sleep Deeper, due to the reduced SCLK frequency.
1211 When in the sleep mode, system DMA access to L1 memory is not supported.
1213 If unsure, select "Sleep Deeper".
1215 config PM_BFIN_SLEEP
1218 Sleep Mode (High Power Savings) - The sleep mode reduces power
1219 dissipation by disabling the clock to the processor core (CCLK).
1220 The PLL and system clock (SCLK), however, continue to operate in
1221 this mode. Typically an external event or RTC activity will wake
1222 up the processor. When in the sleep mode, system DMA access to L1
1223 memory is not supported.
1225 If unsure, select "Sleep Deeper".
1228 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1231 config PM_BFIN_WAKE_PH6
1232 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1233 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1236 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1238 config PM_BFIN_WAKE_GP
1239 bool "Allow Wake-Up from GPIOs"
1240 depends on PM && BF54x
1243 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1244 (all processors, except ADSP-BF549). This option sets
1245 the general-purpose wake-up enable (GPWE) control bit to enable
1246 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1247 On ADSP-BF549 this option enables the the same functionality on the
1248 /MRXON pin also PH7.
1252 menu "CPU Frequency scaling"
1254 source "drivers/cpufreq/Kconfig"
1256 config BFIN_CPU_FREQ
1259 select CPU_FREQ_TABLE
1263 bool "CPU Voltage scaling"
1264 depends on EXPERIMENTAL
1268 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1269 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1270 manuals. There is a theoretical risk that during VDDINT transitions
1275 source "net/Kconfig"
1277 source "drivers/Kconfig"
1279 source "drivers/firmware/Kconfig"
1283 source "arch/blackfin/Kconfig.debug"
1285 source "security/Kconfig"
1287 source "crypto/Kconfig"
1289 source "lib/Kconfig"