11 config RWSEM_GENERIC_SPINLOCK
14 config RWSEM_XCHGADD_ALGORITHM
20 select HAVE_ARCH_TRACEHOOK
21 select HAVE_DYNAMIC_FTRACE
22 select HAVE_FTRACE_MCOUNT_RECORD
23 select HAVE_FUNCTION_GRAPH_TRACER
24 select HAVE_FUNCTION_TRACER
25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
28 select HAVE_KERNEL_GZIP if RAMKERNEL
29 select HAVE_KERNEL_BZIP2 if RAMKERNEL
30 select HAVE_KERNEL_LZMA if RAMKERNEL
31 select HAVE_KERNEL_LZO if RAMKERNEL
33 select HAVE_PERF_EVENTS
34 select ARCH_WANT_OPTIONAL_GPIOLIB
35 select HAVE_GENERIC_HARDIRQS
36 select GENERIC_ATOMIC64
37 select GENERIC_IRQ_PROBE
38 select IRQ_PER_CPU if SMP
50 config GENERIC_FIND_NEXT_BIT
56 config FORCE_MAX_ZONEORDER
60 config GENERIC_CALIBRATE_DELAY
63 config LOCKDEP_SUPPORT
66 config STACKTRACE_SUPPORT
69 config TRACE_IRQFLAGS_SUPPORT
74 source "kernel/Kconfig.preempt"
76 source "kernel/Kconfig.freezer"
78 menu "Blackfin Processor Options"
80 comment "Processor and Board Settings"
89 BF512 Processor Support.
94 BF514 Processor Support.
99 BF516 Processor Support.
104 BF518 Processor Support.
109 BF522 Processor Support.
114 BF523 Processor Support.
119 BF524 Processor Support.
124 BF525 Processor Support.
129 BF526 Processor Support.
134 BF527 Processor Support.
139 BF531 Processor Support.
144 BF532 Processor Support.
149 BF533 Processor Support.
154 BF534 Processor Support.
159 BF536 Processor Support.
164 BF537 Processor Support.
169 BF538 Processor Support.
174 BF539 Processor Support.
179 BF542 Processor Support.
184 BF542 Processor Support.
189 BF544 Processor Support.
194 BF544 Processor Support.
199 BF547 Processor Support.
204 BF547 Processor Support.
209 BF548 Processor Support.
214 BF548 Processor Support.
219 BF549 Processor Support.
224 BF549 Processor Support.
229 BF561 Processor Support.
235 select TICKSOURCE_CORETMR
236 bool "Symmetric multi-processing support"
238 This enables support for systems with more than one CPU,
239 like the dual core BF561. If you have a system with only one
240 CPU, say N. If you have a system with more than one CPU, say Y.
242 If you don't know what to do here, say N.
250 bool "Support for hot-pluggable CPUs"
251 depends on SMP && HOTPLUG
254 config HAVE_LEGACY_PER_CPU_AREA
260 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
261 default 2 if (BF537 || BF536 || BF534)
262 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
263 default 4 if (BF538 || BF539)
267 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
268 default 3 if (BF537 || BF536 || BF534 || BF54xM)
269 default 5 if (BF561 || BF538 || BF539)
270 default 6 if (BF533 || BF532 || BF531)
274 default BF_REV_0_0 if (BF51x || BF52x)
275 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
276 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
280 depends on (BF51x || BF52x || (BF54x && !BF54xM))
284 depends on (BF51x || BF52x || (BF54x && !BF54xM))
288 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
292 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
296 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
300 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
304 depends on (BF533 || BF532 || BF531)
316 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
319 config MEM_MT48LC64M4A2FB_7E
321 depends on (BFIN533_STAMP)
324 config MEM_MT48LC16M16A2TG_75
326 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
327 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
328 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
329 || BFIN527_BLUETECHNIX_CM)
332 config MEM_MT48LC32M8A2_75
334 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
337 config MEM_MT48LC8M32B2B5_7
339 depends on (BFIN561_BLUETECHNIX_CM)
342 config MEM_MT48LC32M16A2TG_75
344 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
347 config MEM_MT48H32M16LFCJ_75
349 depends on (BFIN526_EZBRD)
352 source "arch/blackfin/mach-bf518/Kconfig"
353 source "arch/blackfin/mach-bf527/Kconfig"
354 source "arch/blackfin/mach-bf533/Kconfig"
355 source "arch/blackfin/mach-bf561/Kconfig"
356 source "arch/blackfin/mach-bf537/Kconfig"
357 source "arch/blackfin/mach-bf538/Kconfig"
358 source "arch/blackfin/mach-bf548/Kconfig"
360 menu "Board customizations"
363 bool "Default bootloader kernel arguments"
366 string "Initial kernel command string"
367 depends on CMDLINE_BOOL
368 default "console=ttyBF0,57600"
370 If you don't have a boot loader capable of passing a command line string
371 to the kernel, you may specify one here. As a minimum, you should specify
372 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
375 hex "Kernel load address for booting"
377 range 0x1000 0x20000000
379 This option allows you to set the load address of the kernel.
380 This can be useful if you are on a board which has a small amount
381 of memory or you wish to reserve some memory at the beginning of
384 Note that you need to keep this value above 4k (0x1000) as this
385 memory region is used to capture NULL pointer references as well
386 as some core kernel functions.
389 hex "Kernel ROM Base"
392 range 0x20000000 0x20400000 if !(BF54x || BF561)
393 range 0x20000000 0x30000000 if (BF54x || BF561)
395 Make sure your ROM base does not include any file-header
396 information that is prepended to the kernel.
398 For example, the bootable U-Boot format (created with
399 mkimage) has a 64 byte header (0x40). So while the image
400 you write to flash might start at say 0x20080000, you have
401 to add 0x40 to get the kernel's ROM base as it will come
404 comment "Clock/PLL Setup"
407 int "Frequency of the crystal on the board in Hz"
408 default "10000000" if BFIN532_IP0X
409 default "11059200" if BFIN533_STAMP
410 default "24576000" if PNAV10
411 default "25000000" # most people use this
412 default "27000000" if BFIN533_EZKIT
413 default "30000000" if BFIN561_EZKIT
414 default "24000000" if BFIN527_AD7160EVAL
416 The frequency of CLKIN crystal oscillator on the board in Hz.
417 Warning: This value should match the crystal on the board. Otherwise,
418 peripherals won't work properly.
420 config BFIN_KERNEL_CLOCK
421 bool "Re-program Clocks while Kernel boots?"
424 This option decides if kernel clocks are re-programed from the
425 bootloader settings. If the clocks are not set, the SDRAM settings
426 are also not changed, and the Bootloader does 100% of the hardware
431 depends on BFIN_KERNEL_CLOCK
436 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
439 If this is set the clock will be divided by 2, before it goes to the PLL.
443 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
445 default "22" if BFIN533_EZKIT
446 default "45" if BFIN533_STAMP
447 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
448 default "22" if BFIN533_BLUETECHNIX_CM
449 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
450 default "20" if BFIN561_EZKIT
451 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
452 default "25" if BFIN527_AD7160EVAL
454 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
455 PLL Frequency = (Crystal Frequency) * (this setting)
458 prompt "Core Clock Divider"
459 depends on BFIN_KERNEL_CLOCK
462 This sets the frequency of the core. It can be 1, 2, 4 or 8
463 Core Frequency = (PLL frequency) / (this setting)
479 int "System Clock Divider"
480 depends on BFIN_KERNEL_CLOCK
484 This sets the frequency of the system clock (including SDRAM or DDR).
485 This can be between 1 and 15
486 System Clock = (PLL frequency) / (this setting)
489 prompt "DDR SDRAM Chip Type"
490 depends on BFIN_KERNEL_CLOCK
492 default MEM_MT46V32M16_5B
494 config MEM_MT46V32M16_6T
497 config MEM_MT46V32M16_5B
502 prompt "DDR/SDRAM Timing"
503 depends on BFIN_KERNEL_CLOCK
504 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
506 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
507 The calculated SDRAM timing parameters may not be 100%
508 accurate - This option is therefore marked experimental.
510 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
511 bool "Calculate Timings (EXPERIMENTAL)"
512 depends on EXPERIMENTAL
514 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
515 bool "Provide accurate Timings based on target SCLK"
517 Please consult the Blackfin Hardware Reference Manuals as well
518 as the memory device datasheet.
519 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
522 menu "Memory Init Control"
523 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
540 config MEM_EBIU_DDRQUE
557 # Max & Min Speeds for various Chips
561 default 400000000 if BF512
562 default 400000000 if BF514
563 default 400000000 if BF516
564 default 400000000 if BF518
565 default 400000000 if BF522
566 default 600000000 if BF523
567 default 400000000 if BF524
568 default 600000000 if BF525
569 default 400000000 if BF526
570 default 600000000 if BF527
571 default 400000000 if BF531
572 default 400000000 if BF532
573 default 750000000 if BF533
574 default 500000000 if BF534
575 default 400000000 if BF536
576 default 600000000 if BF537
577 default 533333333 if BF538
578 default 533333333 if BF539
579 default 600000000 if BF542
580 default 533333333 if BF544
581 default 600000000 if BF547
582 default 600000000 if BF548
583 default 533333333 if BF549
584 default 600000000 if BF561
598 comment "Kernel Timer/Scheduler"
600 source kernel/Kconfig.hz
602 config GENERIC_CLOCKEVENTS
603 bool "Generic clock events"
606 menu "Clock event device"
607 depends on GENERIC_CLOCKEVENTS
608 config TICKSOURCE_GPTMR0
613 config TICKSOURCE_CORETMR
619 depends on GENERIC_CLOCKEVENTS
620 config CYCLES_CLOCKSOURCE
623 depends on !BFIN_SCRATCH_REG_CYCLES
626 If you say Y here, you will enable support for using the 'cycles'
627 registers as a clock source. Doing so means you will be unable to
628 safely write to the 'cycles' register during runtime. You will
629 still be able to read it (such as for performance monitoring), but
630 writing the registers will most likely crash the kernel.
632 config GPTMR0_CLOCKSOURCE
635 depends on !TICKSOURCE_GPTMR0
638 config ARCH_USES_GETTIMEOFFSET
639 depends on !GENERIC_CLOCKEVENTS
642 source kernel/time/Kconfig
647 prompt "Blackfin Exception Scratch Register"
648 default BFIN_SCRATCH_REG_RETN
650 Select the resource to reserve for the Exception handler:
651 - RETN: Non-Maskable Interrupt (NMI)
652 - RETE: Exception Return (JTAG/ICE)
653 - CYCLES: Performance counter
655 If you are unsure, please select "RETN".
657 config BFIN_SCRATCH_REG_RETN
660 Use the RETN register in the Blackfin exception handler
661 as a stack scratch register. This means you cannot
662 safely use NMI on the Blackfin while running Linux, but
663 you can debug the system with a JTAG ICE and use the
664 CYCLES performance registers.
666 If you are unsure, please select "RETN".
668 config BFIN_SCRATCH_REG_RETE
671 Use the RETE register in the Blackfin exception handler
672 as a stack scratch register. This means you cannot
673 safely use a JTAG ICE while debugging a Blackfin board,
674 but you can safely use the CYCLES performance registers
677 If you are unsure, please select "RETN".
679 config BFIN_SCRATCH_REG_CYCLES
682 Use the CYCLES register in the Blackfin exception handler
683 as a stack scratch register. This means you cannot
684 safely use the CYCLES performance registers on a Blackfin
685 board at anytime, but you can debug the system with a JTAG
688 If you are unsure, please select "RETN".
695 menu "Blackfin Kernel Optimizations"
697 comment "Memory Optimizations"
700 bool "Locate interrupt entry code in L1 Memory"
704 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
705 into L1 instruction memory. (less latency)
707 config EXCPT_IRQ_SYSC_L1
708 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
712 If enabled, the entire ASM lowlevel exception and interrupt entry code
713 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
717 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
721 If enabled, the frequently called do_irq dispatcher function is linked
722 into L1 instruction memory. (less latency)
724 config CORE_TIMER_IRQ_L1
725 bool "Locate frequently called timer_interrupt() function in L1 Memory"
729 If enabled, the frequently called timer_interrupt() function is linked
730 into L1 instruction memory. (less latency)
733 bool "Locate frequently idle function in L1 Memory"
737 If enabled, the frequently called idle function is linked
738 into L1 instruction memory. (less latency)
741 bool "Locate kernel schedule function in L1 Memory"
745 If enabled, the frequently called kernel schedule is linked
746 into L1 instruction memory. (less latency)
748 config ARITHMETIC_OPS_L1
749 bool "Locate kernel owned arithmetic functions in L1 Memory"
753 If enabled, arithmetic functions are linked
754 into L1 instruction memory. (less latency)
757 bool "Locate access_ok function in L1 Memory"
761 If enabled, the access_ok function is linked
762 into L1 instruction memory. (less latency)
765 bool "Locate memset function in L1 Memory"
769 If enabled, the memset function is linked
770 into L1 instruction memory. (less latency)
773 bool "Locate memcpy function in L1 Memory"
777 If enabled, the memcpy function is linked
778 into L1 instruction memory. (less latency)
781 bool "locate strcmp function in L1 Memory"
785 If enabled, the strcmp function is linked
786 into L1 instruction memory (less latency).
789 bool "locate strncmp function in L1 Memory"
793 If enabled, the strncmp function is linked
794 into L1 instruction memory (less latency).
797 bool "locate strcpy function in L1 Memory"
801 If enabled, the strcpy function is linked
802 into L1 instruction memory (less latency).
805 bool "locate strncpy function in L1 Memory"
809 If enabled, the strncpy function is linked
810 into L1 instruction memory (less latency).
812 config SYS_BFIN_SPINLOCK_L1
813 bool "Locate sys_bfin_spinlock function in L1 Memory"
817 If enabled, sys_bfin_spinlock function is linked
818 into L1 instruction memory. (less latency)
820 config IP_CHECKSUM_L1
821 bool "Locate IP Checksum function in L1 Memory"
825 If enabled, the IP Checksum function is linked
826 into L1 instruction memory. (less latency)
828 config CACHELINE_ALIGNED_L1
829 bool "Locate cacheline_aligned data to L1 Data Memory"
832 depends on !SMP && !BF531
834 If enabled, cacheline_aligned data is linked
835 into L1 data memory. (less latency)
837 config SYSCALL_TAB_L1
838 bool "Locate Syscall Table L1 Data Memory"
840 depends on !SMP && !BF531
842 If enabled, the Syscall LUT is linked
843 into L1 data memory. (less latency)
845 config CPLB_SWITCH_TAB_L1
846 bool "Locate CPLB Switch Tables L1 Data Memory"
848 depends on !SMP && !BF531
850 If enabled, the CPLB Switch Tables are linked
851 into L1 data memory. (less latency)
853 config ICACHE_FLUSH_L1
854 bool "Locate icache flush funcs in L1 Inst Memory"
857 If enabled, the Blackfin icache flushing functions are linked
858 into L1 instruction memory.
860 Note that this might be required to address anomalies, but
861 these functions are pretty small, so it shouldn't be too bad.
862 If you are using a processor affected by an anomaly, the build
863 system will double check for you and prevent it.
865 config DCACHE_FLUSH_L1
866 bool "Locate dcache flush funcs in L1 Inst Memory"
870 If enabled, the Blackfin dcache flushing functions are linked
871 into L1 instruction memory.
874 bool "Support locating application stack in L1 Scratch Memory"
878 If enabled the application stack can be located in L1
879 scratch memory (less latency).
881 Currently only works with FLAT binaries.
883 config EXCEPTION_L1_SCRATCH
884 bool "Locate exception stack in L1 Scratch Memory"
886 depends on !SMP && !APP_STACK_L1
888 Whenever an exception occurs, use the L1 Scratch memory for
889 stack storage. You cannot place the stacks of FLAT binaries
890 in L1 when using this option.
892 If you don't use L1 Scratch, then you should say Y here.
894 comment "Speed Optimizations"
895 config BFIN_INS_LOWOVERHEAD
896 bool "ins[bwl] low overhead, higher interrupt latency"
900 Reads on the Blackfin are speculative. In Blackfin terms, this means
901 they can be interrupted at any time (even after they have been issued
902 on to the external bus), and re-issued after the interrupt occurs.
903 For memory - this is not a big deal, since memory does not change if
906 If a FIFO is sitting on the end of the read, it will see two reads,
907 when the core only sees one since the FIFO receives both the read
908 which is cancelled (and not delivered to the core) and the one which
909 is re-issued (which is delivered to the core).
911 To solve this, interrupts are turned off before reads occur to
912 I/O space. This option controls which the overhead/latency of
913 controlling interrupts during this time
914 "n" turns interrupts off every read
915 (higher overhead, but lower interrupt latency)
916 "y" turns interrupts off every loop
917 (low overhead, but longer interrupt latency)
919 default behavior is to leave this set to on (type "Y"). If you are experiencing
920 interrupt latency issues, it is safe and OK to turn this off.
925 prompt "Kernel executes from"
927 Choose the memory type that the kernel will be running in.
932 The kernel will be resident in RAM when running.
937 The kernel will be resident in FLASH/ROM when running.
941 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
950 tristate "Enable Blackfin General Purpose Timers API"
953 Enable support for the General Purpose Timers API. If you
956 To compile this driver as a module, choose M here: the module
957 will be called gptimers.
960 prompt "Uncached DMA region"
961 default DMA_UNCACHED_1M
962 config DMA_UNCACHED_4M
963 bool "Enable 4M DMA region"
964 config DMA_UNCACHED_2M
965 bool "Enable 2M DMA region"
966 config DMA_UNCACHED_1M
967 bool "Enable 1M DMA region"
968 config DMA_UNCACHED_512K
969 bool "Enable 512K DMA region"
970 config DMA_UNCACHED_256K
971 bool "Enable 256K DMA region"
972 config DMA_UNCACHED_128K
973 bool "Enable 128K DMA region"
974 config DMA_UNCACHED_NONE
975 bool "Disable DMA region"
979 comment "Cache Support"
984 config BFIN_EXTMEM_ICACHEABLE
985 bool "Enable ICACHE for external memory"
986 depends on BFIN_ICACHE
988 config BFIN_L2_ICACHEABLE
989 bool "Enable ICACHE for L2 SRAM"
990 depends on BFIN_ICACHE
991 depends on BF54x || BF561
997 config BFIN_DCACHE_BANKA
998 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
999 depends on BFIN_DCACHE && !BF531
1001 config BFIN_EXTMEM_DCACHEABLE
1002 bool "Enable DCACHE for external memory"
1003 depends on BFIN_DCACHE
1006 prompt "External memory DCACHE policy"
1007 depends on BFIN_EXTMEM_DCACHEABLE
1008 default BFIN_EXTMEM_WRITEBACK if !SMP
1009 default BFIN_EXTMEM_WRITETHROUGH if SMP
1010 config BFIN_EXTMEM_WRITEBACK
1015 Cached data will be written back to SDRAM only when needed.
1016 This can give a nice increase in performance, but beware of
1017 broken drivers that do not properly invalidate/flush their
1020 Write Through Policy:
1021 Cached data will always be written back to SDRAM when the
1022 cache is updated. This is a completely safe setting, but
1023 performance is worse than Write Back.
1025 If you are unsure of the options and you want to be safe,
1026 then go with Write Through.
1028 config BFIN_EXTMEM_WRITETHROUGH
1029 bool "Write through"
1032 Cached data will be written back to SDRAM only when needed.
1033 This can give a nice increase in performance, but beware of
1034 broken drivers that do not properly invalidate/flush their
1037 Write Through Policy:
1038 Cached data will always be written back to SDRAM when the
1039 cache is updated. This is a completely safe setting, but
1040 performance is worse than Write Back.
1042 If you are unsure of the options and you want to be safe,
1043 then go with Write Through.
1047 config BFIN_L2_DCACHEABLE
1048 bool "Enable DCACHE for L2 SRAM"
1049 depends on BFIN_DCACHE
1050 depends on (BF54x || BF561) && !SMP
1053 prompt "L2 SRAM DCACHE policy"
1054 depends on BFIN_L2_DCACHEABLE
1055 default BFIN_L2_WRITEBACK
1056 config BFIN_L2_WRITEBACK
1059 config BFIN_L2_WRITETHROUGH
1060 bool "Write through"
1064 comment "Memory Protection Unit"
1066 bool "Enable the memory protection unit (EXPERIMENTAL)"
1069 Use the processor's MPU to protect applications from accessing
1070 memory they do not own. This comes at a performance penalty
1071 and is recommended only for debugging.
1073 comment "Asynchronous Memory Configuration"
1075 menu "EBIU_AMGCTL Global Control"
1077 bool "Enable CLKOUT"
1081 bool "DMA has priority over core for ext. accesses"
1086 bool "Bank 0 16 bit packing enable"
1091 bool "Bank 1 16 bit packing enable"
1096 bool "Bank 2 16 bit packing enable"
1101 bool "Bank 3 16 bit packing enable"
1105 prompt "Enable Asynchronous Memory Banks"
1109 bool "Disable All Banks"
1112 bool "Enable Bank 0"
1114 config C_AMBEN_B0_B1
1115 bool "Enable Bank 0 & 1"
1117 config C_AMBEN_B0_B1_B2
1118 bool "Enable Bank 0 & 1 & 2"
1121 bool "Enable All Banks"
1125 menu "EBIU_AMBCTL Control"
1127 hex "Bank 0 (AMBCTL0.L)"
1130 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1131 used to control the Asynchronous Memory Bank 0 settings.
1134 hex "Bank 1 (AMBCTL0.H)"
1136 default 0x5558 if BF54x
1138 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1139 used to control the Asynchronous Memory Bank 1 settings.
1142 hex "Bank 2 (AMBCTL1.L)"
1145 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1146 used to control the Asynchronous Memory Bank 2 settings.
1149 hex "Bank 3 (AMBCTL1.H)"
1152 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1153 used to control the Asynchronous Memory Bank 3 settings.
1157 config EBIU_MBSCTLVAL
1158 hex "EBIU Bank Select Control Register"
1163 hex "Flash Memory Mode Control Register"
1168 hex "Flash Memory Bank Control Register"
1173 #############################################################################
1174 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1180 Support for PCI bus.
1182 source "drivers/pci/Kconfig"
1184 source "drivers/pcmcia/Kconfig"
1186 source "drivers/pci/hotplug/Kconfig"
1190 menu "Executable file formats"
1192 source "fs/Kconfig.binfmt"
1196 menu "Power management options"
1198 source "kernel/power/Kconfig"
1200 config ARCH_SUSPEND_POSSIBLE
1204 prompt "Standby Power Saving Mode"
1206 default PM_BFIN_SLEEP_DEEPER
1207 config PM_BFIN_SLEEP_DEEPER
1210 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1211 power dissipation by disabling the clock to the processor core (CCLK).
1212 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1213 to 0.85 V to provide the greatest power savings, while preserving the
1215 The PLL and system clock (SCLK) continue to operate at a very low
1216 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1217 the SDRAM is put into Self Refresh Mode. Typically an external event
1218 such as GPIO interrupt or RTC activity wakes up the processor.
1219 Various Peripherals such as UART, SPORT, PPI may not function as
1220 normal during Sleep Deeper, due to the reduced SCLK frequency.
1221 When in the sleep mode, system DMA access to L1 memory is not supported.
1223 If unsure, select "Sleep Deeper".
1225 config PM_BFIN_SLEEP
1228 Sleep Mode (High Power Savings) - The sleep mode reduces power
1229 dissipation by disabling the clock to the processor core (CCLK).
1230 The PLL and system clock (SCLK), however, continue to operate in
1231 this mode. Typically an external event or RTC activity will wake
1232 up the processor. When in the sleep mode, system DMA access to L1
1233 memory is not supported.
1235 If unsure, select "Sleep Deeper".
1238 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1241 config PM_BFIN_WAKE_PH6
1242 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1243 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1246 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1248 config PM_BFIN_WAKE_GP
1249 bool "Allow Wake-Up from GPIOs"
1250 depends on PM && BF54x
1253 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1254 (all processors, except ADSP-BF549). This option sets
1255 the general-purpose wake-up enable (GPWE) control bit to enable
1256 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1257 On ADSP-BF549 this option enables the the same functionality on the
1258 /MRXON pin also PH7.
1262 menu "CPU Frequency scaling"
1264 source "drivers/cpufreq/Kconfig"
1266 config BFIN_CPU_FREQ
1269 select CPU_FREQ_TABLE
1273 bool "CPU Voltage scaling"
1274 depends on EXPERIMENTAL
1278 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1279 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1280 manuals. There is a theoretical risk that during VDDINT transitions
1285 source "net/Kconfig"
1287 source "drivers/Kconfig"
1289 source "drivers/firmware/Kconfig"
1293 source "arch/blackfin/Kconfig.debug"
1295 source "security/Kconfig"
1297 source "crypto/Kconfig"
1299 source "lib/Kconfig"