2 * Blackfin core register bit & address definitions
4 * Copyright 2005-2008 Analog Devices Inc.
6 * Licensed under the ADI BSD license or GPL-2 (or later).
9 #ifndef _DEF_LPBLACKFIN_H
10 #define _DEF_LPBLACKFIN_H
12 #include <mach/anomaly.h>
14 #define MK_BMSK_(x) (1<<x)
15 #define BFIN_DEPOSIT(mask, x) (((x) << __ffs(mask)) & (mask))
16 #define BFIN_EXTRACT(mask, x) (((x) & (mask)) >> __ffs(mask))
20 #include <linux/types.h>
23 # define NOP_PAD_ANOMALY_05000198 "nop;"
25 # define NOP_PAD_ANOMALY_05000198
28 #define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
30 __asm__ __volatile__( \
31 NOP_PAD_ANOMALY_05000198 \
32 "%0 = " #asm_size "[%1]" #asm_ext ";" \
37 #define _bfin_writeX(addr, val, size, asm_size) \
38 __asm__ __volatile__( \
39 NOP_PAD_ANOMALY_05000198 \
40 #asm_size "[%0] = %1;" \
42 : "a" (addr), "d" ((u##size)(val)) \
46 #define bfin_read8(addr) _bfin_readX(addr, 8, b, (z))
47 #define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
48 #define bfin_read32(addr) _bfin_readX(addr, 32, , )
49 #define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b)
50 #define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
51 #define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
53 #define bfin_read(addr) \
55 sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
56 sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
57 sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
60 #define bfin_write(addr, val) \
62 switch (sizeof(*(addr))) { \
63 case 1: bfin_write8(addr, val); break; \
64 case 2: bfin_write16(addr, val); break; \
65 case 4: bfin_write32(addr, val); break; \
70 #endif /* __ASSEMBLY__ */
72 /**************************************************
73 * System Register Bits
74 **************************************************/
76 /**************************************************
78 **************************************************/
80 /* definitions of ASTAT bit positions*/
82 /*Result of last ALU0 or shifter operation is zero*/
83 #define ASTAT_AZ_P 0x00000000
84 /*Result of last ALU0 or shifter operation is negative*/
85 #define ASTAT_AN_P 0x00000001
86 /*Condition Code, used for holding comparison results*/
87 #define ASTAT_CC_P 0x00000005
89 #define ASTAT_AQ_P 0x00000006
90 /*Rounding mode, set for biased, clear for unbiased*/
91 #define ASTAT_RND_MOD_P 0x00000008
92 /*Result of last ALU0 operation generated a carry*/
93 #define ASTAT_AC0_P 0x0000000C
94 /*Result of last ALU0 operation generated a carry*/
95 #define ASTAT_AC0_COPY_P 0x00000002
96 /*Result of last ALU1 operation generated a carry*/
97 #define ASTAT_AC1_P 0x0000000D
98 /*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
99 #define ASTAT_AV0_P 0x00000010
100 /*Sticky version of ASTAT_AV0 */
101 #define ASTAT_AV0S_P 0x00000011
102 /*Result of last MAC1 operation overflowed, sticky for MAC*/
103 #define ASTAT_AV1_P 0x00000012
104 /*Sticky version of ASTAT_AV1 */
105 #define ASTAT_AV1S_P 0x00000013
106 /*Result of last ALU0 or MAC0 operation overflowed*/
107 #define ASTAT_V_P 0x00000018
108 /*Result of last ALU0 or MAC0 operation overflowed*/
109 #define ASTAT_V_COPY_P 0x00000003
110 /*Sticky version of ASTAT_V*/
111 #define ASTAT_VS_P 0x00000019
115 /*Result of last ALU0 or shifter operation is zero*/
116 #define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
117 /*Result of last ALU0 or shifter operation is negative*/
118 #define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
119 /*Result of last ALU0 operation generated a carry*/
120 #define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
121 /*Result of last ALU0 operation generated a carry*/
122 #define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
123 /*Result of last ALU0 operation generated a carry*/
124 #define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
125 /*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
126 #define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
127 /*Result of last MAC1 operation overflowed, sticky for MAC*/
128 #define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
129 /*Condition Code, used for holding comparison results*/
130 #define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
132 #define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
133 /*Rounding mode, set for biased, clear for unbiased*/
134 #define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
136 #define ASTAT_V MK_BMSK_(ASTAT_V_P)
138 #define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
140 /**************************************************
142 **************************************************/
145 #define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
146 #define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
147 #define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
148 #define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
149 #define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
150 #define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
151 #define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
152 * set by IDLE instruction.
154 #define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
155 * reset was a software reset
158 #define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
159 #define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
160 #define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
161 #define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
162 #define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
164 /* Exception cause */
165 #define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
166 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
167 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
168 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
169 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
170 MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
173 /* Indicates whether the last reset was a software reset (=1) */
174 #define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
176 /* Last hw error cause */
177 #define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
178 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
179 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
180 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
181 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
184 /* Translate bits to something useful */
186 /* Last hw error cause */
187 #define SEQSTAT_HWERRCAUSE_SHIFT (14)
188 #define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
189 #define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
190 #define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
191 #define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
193 /**************************************************
195 **************************************************/
198 #define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
199 * set it forces an exception
200 * for each instruction executed
202 #define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
203 #define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
207 /* Supervisor single step, when set it forces an exception for each
208 *instruction executed
210 #define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
211 /* Enable cycle counter (=1) */
212 #define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
213 /* Self Nesting Interrupt Enable */
214 #define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
215 /* Backward-compatibility for typos in prior releases */
216 #define SYSCFG_SSSSTEP SYSCFG_SSSTEP
217 #define SYSCFG_CCCEN SYSCFG_CCEN
219 /****************************************************
220 * Core MMR Register Map
221 ****************************************************/
223 /* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
225 #define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
226 #define DMEM_CONTROL 0xFFE00004 /* Data memory control */
227 #define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
230 #define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
231 #define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
232 * Buffer Fault Address
234 #define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
237 #define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
240 #define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
243 #define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
246 #define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
249 #define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
252 #define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
255 #define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
258 #define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
261 #define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
264 #define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
265 * Lookaside Buffer 10
267 #define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
268 * Lookaside Buffer 11
270 #define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
271 * Lookaside Buffer 12
273 #define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
274 * Lookaside Buffer 13
276 #define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
277 * Lookaside Buffer 14
279 #define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
280 * Lookaside Buffer 15
282 #define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
283 #define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
284 #define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
285 #define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
286 #define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
287 #define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
288 #define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
289 #define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
290 #define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
291 #define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
292 #define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
293 #define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
294 #define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
295 #define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
296 #define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
297 #define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
298 #define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
300 #define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
301 #define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
302 #define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
304 /* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
306 #define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
307 #define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
308 #define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
309 #define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
310 #define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
311 #define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
312 * Protection Lookaside Buffer 0
314 #define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
315 * Protection Lookaside Buffer 1
317 #define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
318 * Protection Lookaside Buffer 2
320 #define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
321 * Protection Lookaside Buffer 3
323 #define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
324 * Protection Lookaside Buffer 4
326 #define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
327 * Protection Lookaside Buffer 5
329 #define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
330 * Protection Lookaside Buffer 6
332 #define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
333 * Protection Lookaside Buffer 7
335 #define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
336 * Protection Lookaside Buffer 8
338 #define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
339 * Protection Lookaside Buffer 9
341 #define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
342 * Protection Lookaside Buffer 10
344 #define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
345 * Protection Lookaside Buffer 11
347 #define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
348 * Protection Lookaside Buffer 12
350 #define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
351 * Protection Lookaside Buffer 13
353 #define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
354 * Protection Lookaside Buffer 14
356 #define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
357 * Protection Lookaside Buffer 15
359 #define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
360 #define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
361 #define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
362 #define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
363 #define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
364 #define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
365 #define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
366 #define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
367 #define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
368 #define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
369 #define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
370 #define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
371 #define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
372 #define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
373 #define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
374 #define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
375 #define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
376 #define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
377 #define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
379 /* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
381 #define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
382 #define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
383 #define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
384 #define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
385 #define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
386 #define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
387 #define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
388 #define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
389 #define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
390 #define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
391 #define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
392 #define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
393 #define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
394 #define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
395 #define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
396 #define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
397 #define IMASK 0xFFE02104 /* Interrupt Mask Register */
398 #define IPEND 0xFFE02108 /* Interrupt Pending Register */
399 #define ILAT 0xFFE0210C /* Interrupt Latch Register */
400 #define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
402 /* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
404 #define TCNTL 0xFFE03000 /* Core Timer Control Register */
405 #define TPERIOD 0xFFE03004 /* Core Timer Period Register */
406 #define TSCALE 0xFFE03008 /* Core Timer Scale Register */
407 #define TCOUNT 0xFFE0300C /* Core Timer Count Register */
409 /* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
410 #define DSPID 0xFFE05000 /* DSP Processor ID Register for
414 #define DBGSTAT 0xFFE05008 /* Debug Status Register */
416 /* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
418 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
419 #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
420 #define TBUF 0xFFE06100 /* Trace Buffer */
422 /* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
424 /* Watchpoint Instruction Address Control Register */
425 #define WPIACTL 0xFFE07000
426 /* Watchpoint Instruction Address Register 0 */
427 #define WPIA0 0xFFE07040
428 /* Watchpoint Instruction Address Register 1 */
429 #define WPIA1 0xFFE07044
430 /* Watchpoint Instruction Address Register 2 */
431 #define WPIA2 0xFFE07048
432 /* Watchpoint Instruction Address Register 3 */
433 #define WPIA3 0xFFE0704C
434 /* Watchpoint Instruction Address Register 4 */
435 #define WPIA4 0xFFE07050
436 /* Watchpoint Instruction Address Register 5 */
437 #define WPIA5 0xFFE07054
438 /* Watchpoint Instruction Address Count Register 0 */
439 #define WPIACNT0 0xFFE07080
440 /* Watchpoint Instruction Address Count Register 1 */
441 #define WPIACNT1 0xFFE07084
442 /* Watchpoint Instruction Address Count Register 2 */
443 #define WPIACNT2 0xFFE07088
444 /* Watchpoint Instruction Address Count Register 3 */
445 #define WPIACNT3 0xFFE0708C
446 /* Watchpoint Instruction Address Count Register 4 */
447 #define WPIACNT4 0xFFE07090
448 /* Watchpoint Instruction Address Count Register 5 */
449 #define WPIACNT5 0xFFE07094
450 /* Watchpoint Data Address Control Register */
451 #define WPDACTL 0xFFE07100
452 /* Watchpoint Data Address Register 0 */
453 #define WPDA0 0xFFE07140
454 /* Watchpoint Data Address Register 1 */
455 #define WPDA1 0xFFE07144
456 /* Watchpoint Data Address Count Value Register 0 */
457 #define WPDACNT0 0xFFE07180
458 /* Watchpoint Data Address Count Value Register 1 */
459 #define WPDACNT1 0xFFE07184
460 /* Watchpoint Status Register */
461 #define WPSTAT 0xFFE07200
463 /* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
465 /* Performance Monitor Control Register */
466 #define PFCTL 0xFFE08000
467 /* Performance Monitor Counter Register 0 */
468 #define PFCNTR0 0xFFE08100
469 /* Performance Monitor Counter Register 1 */
470 #define PFCNTR1 0xFFE08104
472 /****************************************************
473 * Core MMR Register Bits
474 ****************************************************/
476 /**************************************************
477 * EVT registers (ILAT, IMASK, and IPEND).
478 **************************************************/
481 #define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
482 #define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
483 #define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
484 #define EVT_EVX_P 0x00000003 /* Exception bit position */
485 #define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
486 #define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
487 #define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
488 #define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
489 #define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
490 #define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
491 #define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
492 #define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
493 #define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
494 #define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
495 #define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
496 #define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
499 #define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
500 #define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
501 #define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
502 #define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
503 #define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
504 #define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
505 #define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
506 #define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
507 #define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
508 #define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
509 #define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
510 #define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
511 #define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
512 #define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
513 #define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
514 #define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
516 /**************************************************
517 * DMEM_CONTROL Register
518 **************************************************/
520 #define ENDM_P 0x00 /* (doesn't really exist) Enable
523 #define DMCTL_ENDM_P ENDM_P /* "" (older define) */
525 #define ENDCPLB_P 0x01 /* Enable DCPLBS */
526 #define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
527 #define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
528 #define DMCTL_DMC0_P DMC0_P /* "" (older define) */
529 #define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
530 #define DMCTL_DMC1_P DMC1_P /* "" (older define) */
531 #define DCBS_P 0x04 /* L1 Data Cache Bank Select */
532 #define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
533 #define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
536 #define ENDM 0x00000001 /* (doesn't really exist) Enable
539 #define ENDCPLB 0x00000002 /* Enable DCPLB */
540 #define ASRAM_BSRAM 0x00000000
541 #define ACACHE_BSRAM 0x00000008
542 #define ACACHE_BCACHE 0x0000000C
543 #define DCBS 0x00000010 /* L1 Data Cache Bank Select */
544 #define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
545 #define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
547 /* IMEM_CONTROL Register */
549 #define ENIM_P 0x00 /* Enable L1 Code Memory */
550 #define IMCTL_ENIM_P 0x00 /* "" (older define) */
551 #define ENICPLB_P 0x01 /* Enable ICPLB */
552 #define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
553 #define IMC_P 0x02 /* Enable */
554 #define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
557 #define ILOC0_P 0x03 /* Lock Way 0 */
558 #define ILOC1_P 0x04 /* Lock Way 1 */
559 #define ILOC2_P 0x05 /* Lock Way 2 */
560 #define ILOC3_P 0x06 /* Lock Way 3 */
561 #define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
565 #define ENIM 0x00000001 /* Enable L1 Code Memory */
566 #define ENICPLB 0x00000002 /* Enable ICPLB */
567 #define IMC 0x00000004 /* Configure L1 code memory as
570 #define ILOC0 0x00000008 /* Lock Way 0 */
571 #define ILOC1 0x00000010 /* Lock Way 1 */
572 #define ILOC2 0x00000020 /* Lock Way 2 */
573 #define ILOC3 0x00000040 /* Lock Way 3 */
574 #define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
579 #define TMPWR 0x00000001 /* Timer Low Power Control,
580 * 0=low power mode, 1=active state
582 #define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
583 #define TAUTORLD 0x00000004 /* Timer auto reload */
584 #define TINT 0x00000008 /* Timer generated interrupt 0=no
585 * interrupt has been generated,
586 * 1=interrupt has been generated
590 /* DCPLB_DATA and ICPLB_DATA Registers */
592 #define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
593 #define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
596 #define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
597 * allowed (user mode)
600 #define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
601 #define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
604 #define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
605 * allowed (user mode)
608 #define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
609 #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
610 #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
611 #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
612 #define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
615 #define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
618 #define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
621 /* ICPLB_DATA only */
622 #define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
623 * 1=priority for non-replacement
625 /* DCPLB_DATA only */
626 #define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
627 * access allowed (user mode)
629 #define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
630 * access allowed (supervisor mode)
632 #define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
633 #define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
634 * write-through writes,
635 * 1= allocate cache lines on
636 * write-through writes.
638 #define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
640 #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
643 #define TBUFPWR 0x0001
644 #define TBUFEN 0x0002
645 #define TBUFOVF 0x0004
646 #define TBUFCMPLP_SINGLE 0x0008
647 #define TBUFCMPLP_DOUBLE 0x0010
648 #define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
651 #define TBUFCNT 0x001F
653 /* ITEST_COMMAND and DTEST_COMMAND Registers */
655 #define TEST_READ 0x00000000 /* Read Access */
656 #define TEST_WRITE 0x00000002 /* Write Access */
657 #define TEST_TAG 0x00000000 /* Access TAG */
658 #define TEST_DATA 0x00000004 /* Access DATA */
659 #define TEST_DW0 0x00000000 /* Select Double Word 0 */
660 #define TEST_DW1 0x00000008 /* Select Double Word 1 */
661 #define TEST_DW2 0x00000010 /* Select Double Word 2 */
662 #define TEST_DW3 0x00000018 /* Select Double Word 3 */
663 #define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
664 #define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
665 #define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
666 #define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
667 #define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
668 #define TEST_WAY0 0x00000000 /* Access Way0 */
669 #define TEST_WAY1 0x04000000 /* Access Way1 */
670 /* ITEST_COMMAND only */
671 #define TEST_WAY2 0x08000000 /* Access Way2 */
672 #define TEST_WAY3 0x0C000000 /* Access Way3 */
673 /* DTEST_COMMAND only */
674 #define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
675 #define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
677 #endif /* _DEF_LPBLACKFIN_H */