2 * Blackfin CPLB exception handling for when MPU in on
4 * Copyright 2008-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #include <linux/module.h>
12 #include <asm/blackfin.h>
13 #include <asm/cacheflush.h>
15 #include <asm/cplbinit.h>
16 #include <asm/mmu_context.h>
21 * This file is compiled with certain -ffixed-reg options. We have to
22 * make sure not to call any functions here that could clobber these
28 unsigned long *current_rwx_mask[NR_CPUS];
30 int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
31 int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
32 int nr_cplb_flush[NR_CPUS];
35 * Given the contents of the status register, return the index of the
36 * CPLB that caused the fault.
38 static inline int faulting_cplb_index(int status)
40 int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
45 * Given the contents of the status register and the DCPLB_DATA contents,
46 * return true if a write access should be permitted.
48 static inline int write_permitted(int status, unsigned long data)
50 if (status & FAULT_USERSUPV)
51 return !!(data & CPLB_SUPV_WR);
53 return !!(data & CPLB_USER_WR);
56 /* Counters to implement round-robin replacement. */
57 static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
60 * Find an ICPLB entry to be evicted and return its index.
62 static int evict_one_icplb(unsigned int cpu)
65 for (i = first_switched_icplb; i < MAX_CPLBS; i++)
66 if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
68 i = first_switched_icplb + icplb_rr_index[cpu];
70 i -= MAX_CPLBS - first_switched_icplb;
71 icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
73 icplb_rr_index[cpu]++;
77 static int evict_one_dcplb(unsigned int cpu)
80 for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
81 if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
83 i = first_switched_dcplb + dcplb_rr_index[cpu];
85 i -= MAX_CPLBS - first_switched_dcplb;
86 dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
88 dcplb_rr_index[cpu]++;
92 static noinline int dcplb_miss(unsigned int cpu)
94 unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
95 int status = bfin_read_DCPLB_STATUS();
100 nr_dcplb_miss[cpu]++;
102 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
103 #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
104 if (bfin_addr_dcacheable(addr)) {
105 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
106 # ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
107 d_data |= CPLB_L1_AOW | CPLB_WT;
112 if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
115 } else if (addr >= physical_mem_end) {
116 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
117 mask = current_rwx_mask[cpu];
119 int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
121 int bit = 1 << (page & 31);
124 d_data |= CPLB_USER_RD;
126 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
127 && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
128 addr &= ~(1 * 1024 * 1024 - 1);
129 d_data &= ~PAGE_SIZE_4KB;
130 d_data |= PAGE_SIZE_1MB;
132 return CPLB_PROT_VIOL;
133 } else if (addr >= _ramend) {
134 d_data |= CPLB_USER_RD | CPLB_USER_WR;
136 mask = current_rwx_mask[cpu];
138 int page = addr >> PAGE_SHIFT;
140 int bit = 1 << (page & 31);
143 d_data |= CPLB_USER_RD;
145 mask += page_mask_nelts;
147 d_data |= CPLB_USER_WR;
150 idx = evict_one_dcplb(cpu);
153 dcplb_tbl[cpu][idx].addr = addr;
154 dcplb_tbl[cpu][idx].data = d_data;
157 bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
158 bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
164 static noinline int icplb_miss(unsigned int cpu)
166 unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
167 int status = bfin_read_ICPLB_STATUS();
169 unsigned long i_data;
171 nr_icplb_miss[cpu]++;
173 /* If inside the uncached DMA region, fault. */
174 if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
175 return CPLB_PROT_VIOL;
177 if (status & FAULT_USERSUPV)
178 nr_icplb_supv_miss[cpu]++;
181 * First, try to find a CPLB that matches this address. If we
182 * find one, then the fact that we're in the miss handler means
183 * that the instruction crosses a page boundary.
185 for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
186 if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
187 unsigned long this_addr = icplb_tbl[cpu][idx].addr;
188 if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
195 i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
197 #ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
199 * Normal RAM, and possibly the reserved memory area, are
202 if (addr < _ramend ||
203 (addr < physical_mem_end && reserved_mem_icache_on))
204 i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
207 if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
210 } else if (addr >= physical_mem_end) {
211 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
212 if (!(status & FAULT_USERSUPV)) {
213 unsigned long *mask = current_rwx_mask[cpu];
216 int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
218 int bit = 1 << (page & 31);
220 mask += 2 * page_mask_nelts;
222 i_data |= CPLB_USER_RD;
225 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
226 && (status & FAULT_USERSUPV)) {
227 addr &= ~(1 * 1024 * 1024 - 1);
228 i_data &= ~PAGE_SIZE_4KB;
229 i_data |= PAGE_SIZE_1MB;
231 return CPLB_PROT_VIOL;
232 } else if (addr >= _ramend) {
233 i_data |= CPLB_USER_RD;
236 * Two cases to distinguish - a supervisor access must
237 * necessarily be for a module page; we grant it
238 * unconditionally (could do better here in the future).
239 * Otherwise, check the x bitmap of the current process.
241 if (!(status & FAULT_USERSUPV)) {
242 unsigned long *mask = current_rwx_mask[cpu];
245 int page = addr >> PAGE_SHIFT;
247 int bit = 1 << (page & 31);
249 mask += 2 * page_mask_nelts;
251 i_data |= CPLB_USER_RD;
255 idx = evict_one_icplb(cpu);
257 icplb_tbl[cpu][idx].addr = addr;
258 icplb_tbl[cpu][idx].data = i_data;
261 bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
262 bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
268 static noinline int dcplb_protection_fault(unsigned int cpu)
270 int status = bfin_read_DCPLB_STATUS();
272 nr_dcplb_prot[cpu]++;
274 if (status & FAULT_RW) {
275 int idx = faulting_cplb_index(status);
276 unsigned long data = dcplb_tbl[cpu][idx].data;
277 if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
278 write_permitted(status, data)) {
280 dcplb_tbl[cpu][idx].data = data;
281 bfin_write32(DCPLB_DATA0 + idx * 4, data);
285 return CPLB_PROT_VIOL;
288 int cplb_hdr(int seqstat, struct pt_regs *regs)
290 int cause = seqstat & 0x3f;
291 unsigned int cpu = raw_smp_processor_id();
294 return dcplb_protection_fault(cpu);
296 return icplb_miss(cpu);
298 return dcplb_miss(cpu);
304 void flush_switched_cplbs(unsigned int cpu)
309 nr_cplb_flush[cpu]++;
311 local_irq_save_hw(flags);
313 for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
314 icplb_tbl[cpu][i].data = 0;
315 bfin_write32(ICPLB_DATA0 + i * 4, 0);
320 for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
321 dcplb_tbl[cpu][i].data = 0;
322 bfin_write32(DCPLB_DATA0 + i * 4, 0);
325 local_irq_restore_hw(flags);
329 void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
332 unsigned long addr = (unsigned long)masks;
333 unsigned long d_data;
337 current_rwx_mask[cpu] = masks;
341 local_irq_save_hw(flags);
342 current_rwx_mask[cpu] = masks;
344 if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
348 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
349 #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
350 d_data |= CPLB_L1_CHBL;
351 # ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
352 d_data |= CPLB_L1_AOW | CPLB_WT;
358 for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
359 dcplb_tbl[cpu][i].addr = addr;
360 dcplb_tbl[cpu][i].data = d_data;
361 bfin_write32(DCPLB_DATA0 + i * 4, d_data);
362 bfin_write32(DCPLB_ADDR0 + i * 4, addr);
366 local_irq_restore_hw(flags);