arch/blackfin/kernel/debug-mmrs.c

   1 /*
   2  * debugfs interface to core/system MMRs
   3  *
   4  * Copyright 2007-2011 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later
   7  */
   8
   9 #include <linux/debugfs.h>
  10 #include <linux/fs.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13
  14 #include <asm/blackfin.h>
  15 #include <asm/gpio.h>
  16 #include <asm/gptimers.h>
  17 #include <asm/bfin_can.h>
  18 #include <asm/bfin_dma.h>
  19 #include <asm/bfin_ppi.h>
  20 #include <asm/bfin_serial.h>
  21 #include <asm/bfin5xx_spi.h>
  22 #include <asm/bfin_twi.h>
  23
  24 /* Common code defines PORT_MUX on us, so redirect the MMR back locally */
  25 #ifdef BFIN_PORT_MUX
  26 #undef PORT_MUX
  27 #define PORT_MUX BFIN_PORT_MUX
  28 #endif
  29
  30 #define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)addr)
  31 #define d(name, bits, addr)         _d(name, bits, addr, S_IRUSR|S_IWUSR)
  32 #define d_RO(name, bits, addr)      _d(name, bits, addr, S_IRUSR)
  33 #define d_WO(name, bits, addr)      _d(name, bits, addr, S_IWUSR)
  34
  35 #define D_RO(name, bits) d_RO(#name, bits, name)
  36 #define D_WO(name, bits) d_WO(#name, bits, name)
  37 #define D32(name)        d(#name, 32, name)
  38 #define D16(name)        d(#name, 16, name)
  39
  40 #define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
  41 #define __REGS(peri, sname, rname) \
  42         do { \
  43                 struct bfin_##peri##_regs r; \
  44                 void *addr = (void *)(base + REGS_OFF(peri, rname)); \
  45                 strcpy(_buf, sname); \
  46                 if (sizeof(r.rname) == 2) \
  47                         debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
  48                 else \
  49                         debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
  50         } while (0)
  51 #define REGS_STR_PFX(buf, pfx, num) \
  52         ({ \
  53                 buf + (num >= 0 ? \
  54                         sprintf(buf, #pfx "%i_", num) : \
  55                         sprintf(buf, #pfx "_")); \
  56         })
  57 #define REGS_STR_PFX_C(buf, pfx, num) \
  58         ({ \
  59                 buf + (num >= 0 ? \
  60                         sprintf(buf, #pfx "%c_", 'A' + num) : \
  61                         sprintf(buf, #pfx "_")); \
  62         })
  63
  64 /*
  65  * Core registers (not memory mapped)
  66  */
  67 extern u32 last_seqstat;
  68
  69 static int debug_cclk_get(void *data, u64 *val)
  70 {
  71         *val = get_cclk();
  72         return 0;
  73 }
  74 DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
  75
  76 static int debug_sclk_get(void *data, u64 *val)
  77 {
  78         *val = get_sclk();
  79         return 0;
  80 }
  81 DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
  82
  83 #define DEFINE_SYSREG(sr, pre, post) \
  84 static int sysreg_##sr##_get(void *data, u64 *val) \
  85 { \
  86         unsigned long tmp; \
  87         pre; \
  88         __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
  89         *val = tmp; \
  90         return 0; \
  91 } \
  92 static int sysreg_##sr##_set(void *data, u64 val) \
  93 { \
  94         unsigned long tmp = val; \
  95         __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
  96         post; \
  97         return 0; \
  98 } \
  99 DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
 100
 101 DEFINE_SYSREG(cycles, , );
 102 DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
 103 DEFINE_SYSREG(emudat, , );
 104 DEFINE_SYSREG(seqstat, , );
 105 DEFINE_SYSREG(syscfg, , CSYNC());
 106 #define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
 107
 108 /*
 109  * CAN
 110  */
 111 #define CAN_OFF(mmr)  REGS_OFF(can, mmr)
 112 #define __CAN(uname, lname) __REGS(can, #uname, lname)
 113 static void __init __maybe_unused
 114 bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
 115 {
 116         static struct dentry *am, *mb;
 117         int i, j;
 118         char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
 119
 120         if (!am) {
 121                 am = debugfs_create_dir("am", parent);
 122                 mb = debugfs_create_dir("mb", parent);
 123         }
 124
 125         __CAN(MC1, mc1);
 126         __CAN(MD1, md1);
 127         __CAN(TRS1, trs1);
 128         __CAN(TRR1, trr1);
 129         __CAN(TA1, ta1);
 130         __CAN(AA1, aa1);
 131         __CAN(RMP1, rmp1);
 132         __CAN(RML1, rml1);
 133         __CAN(MBTIF1, mbtif1);
 134         __CAN(MBRIF1, mbrif1);
 135         __CAN(MBIM1, mbim1);
 136         __CAN(RFH1, rfh1);
 137         __CAN(OPSS1, opss1);
 138
 139         __CAN(MC2, mc2);
 140         __CAN(MD2, md2);
 141         __CAN(TRS2, trs2);
 142         __CAN(TRR2, trr2);
 143         __CAN(TA2, ta2);
 144         __CAN(AA2, aa2);
 145         __CAN(RMP2, rmp2);
 146         __CAN(RML2, rml2);
 147         __CAN(MBTIF2, mbtif2);
 148         __CAN(MBRIF2, mbrif2);
 149         __CAN(MBIM2, mbim2);
 150         __CAN(RFH2, rfh2);
 151         __CAN(OPSS2, opss2);
 152
 153         __CAN(CLOCK, clock);
 154         __CAN(TIMING, timing);
 155         __CAN(DEBUG, debug);
 156         __CAN(STATUS, status);
 157         __CAN(CEC, cec);
 158         __CAN(GIS, gis);
 159         __CAN(GIM, gim);
 160         __CAN(GIF, gif);
 161         __CAN(CONTROL, control);
 162         __CAN(INTR, intr);
 163         __CAN(VERSION, version);
 164         __CAN(MBTD, mbtd);
 165         __CAN(EWR, ewr);
 166         __CAN(ESR, esr);
 167         /*__CAN(UCREG, ucreg); no longer exists */
 168         __CAN(UCCNT, uccnt);
 169         __CAN(UCRC, ucrc);
 170         __CAN(UCCNF, uccnf);
 171         __CAN(VERSION2, version2);
 172
 173         for (i = 0; i < 32; ++i) {
 174                 sprintf(_buf, "AM%02iL", i);
 175                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
 176                         (u16 *)(base + CAN_OFF(msk[i].aml)));
 177                 sprintf(_buf, "AM%02iH", i);
 178                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
 179                         (u16 *)(base + CAN_OFF(msk[i].amh)));
 180
 181                 for (j = 0; j < 3; ++j) {
 182                         sprintf(_buf, "MB%02i_DATA%i", i, j);
 183                         debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 184                                 (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
 185                 }
 186                 sprintf(_buf, "MB%02i_LENGTH", i);
 187                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 188                         (u16 *)(base + CAN_OFF(chl[i].dlc)));
 189                 sprintf(_buf, "MB%02i_TIMESTAMP", i);
 190                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 191                         (u16 *)(base + CAN_OFF(chl[i].tsv)));
 192                 sprintf(_buf, "MB%02i_ID0", i);
 193                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 194                         (u16 *)(base + CAN_OFF(chl[i].id0)));
 195                 sprintf(_buf, "MB%02i_ID1", i);
 196                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 197                         (u16 *)(base + CAN_OFF(chl[i].id1)));
 198         }
 199 }
 200 #define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
 201
 202 /*
 203  * DMA
 204  */
 205 #define __DMA(uname, lname) __REGS(dma, #uname, lname)
 206 static void __init __maybe_unused
 207 bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
 208 {
 209         char buf[32], *_buf;
 210
 211         if (mdma)
 212                 _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
 213         else
 214                 _buf = buf + sprintf(buf, "%s%i_", pfx, num);
 215
 216         __DMA(NEXT_DESC_PTR, next_desc_ptr);
 217         __DMA(START_ADDR, start_addr);
 218         __DMA(CONFIG, config);
 219         __DMA(X_COUNT, x_count);
 220         __DMA(X_MODIFY, x_modify);
 221         __DMA(Y_COUNT, y_count);
 222         __DMA(Y_MODIFY, y_modify);
 223         __DMA(CURR_DESC_PTR, curr_desc_ptr);
 224         __DMA(CURR_ADDR, curr_addr);
 225         __DMA(IRQ_STATUS, irq_status);
 226         if (strcmp(pfx, "IMDMA") != 0)
 227                 __DMA(PERIPHERAL_MAP, peripheral_map);
 228         __DMA(CURR_X_COUNT, curr_x_count);
 229         __DMA(CURR_Y_COUNT, curr_y_count);
 230 }
 231 #define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
 232 #define DMA(num)  _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
 233 #define _MDMA(num, x) \
 234         do { \
 235                 _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
 236                 _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
 237         } while (0)
 238 #define MDMA(num) _MDMA(num, M)
 239 #define IMDMA(num) _MDMA(num, IM)
 240
 241 /*
 242  * EPPI
 243  */
 244 #define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
 245 static void __init __maybe_unused
 246 bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
 247 {
 248         char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
 249         __EPPI(STATUS, status);
 250         __EPPI(HCOUNT, hcount);
 251         __EPPI(HDELAY, hdelay);
 252         __EPPI(VCOUNT, vcount);
 253         __EPPI(VDELAY, vdelay);
 254         __EPPI(FRAME, frame);
 255         __EPPI(LINE, line);
 256         __EPPI(CLKDIV, clkdiv);
 257         __EPPI(CONTROL, control);
 258         __EPPI(FS1W_HBL, fs1w_hbl);
 259         __EPPI(FS1P_AVPL, fs1p_avpl);
 260         __EPPI(FS2W_LVB, fs2w_lvb);
 261         __EPPI(FS2P_LAVF, fs2p_lavf);
 262         __EPPI(CLIP, clip);
 263 }
 264 #define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
 265
 266 /*
 267  * General Purpose Timers
 268  */
 269 #define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
 270 static void __init __maybe_unused
 271 bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
 272 {
 273         char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
 274         __GPTIMER(CONFIG, config);
 275         __GPTIMER(COUNTER, counter);
 276         __GPTIMER(PERIOD, period);
 277         __GPTIMER(WIDTH, width);
 278 }
 279 #define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
 280
 281 /*
 282  * Handshake MDMA
 283  */
 284 #define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
 285 static void __init __maybe_unused
 286 bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
 287 {
 288         char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
 289         __HMDMA(CONTROL, control);
 290         __HMDMA(ECINIT, ecinit);
 291         __HMDMA(BCINIT, bcinit);
 292         __HMDMA(ECURGENT, ecurgent);
 293         __HMDMA(ECOVERFLOW, ecoverflow);
 294         __HMDMA(ECOUNT, ecount);
 295         __HMDMA(BCOUNT, bcount);
 296 }
 297 #define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
 298
 299 /*
 300  * Port/GPIO
 301  */
 302 #define bfin_gpio_regs gpio_port_t
 303 #define __PORT(uname, lname) __REGS(gpio, #uname, lname)
 304 static void __init __maybe_unused
 305 bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
 306 {
 307         char buf[32], *_buf;
 308 #ifdef __ADSPBF54x__
 309         _buf = REGS_STR_PFX_C(buf, PORT, num);
 310         __PORT(FER, port_fer);
 311         __PORT(SET, data_set);
 312         __PORT(CLEAR, data_clear);
 313         __PORT(DIR_SET, dir_set);
 314         __PORT(DIR_CLEAR, dir_clear);
 315         __PORT(INEN, inen);
 316         __PORT(MUX, port_mux);
 317 #else
 318         _buf = buf + sprintf(buf, "PORT%cIO_", num);
 319         __PORT(CLEAR, data_clear);
 320         __PORT(SET, data_set);
 321         __PORT(TOGGLE, toggle);
 322         __PORT(MASKA, maska);
 323         __PORT(MASKA_CLEAR, maska_clear);
 324         __PORT(MASKA_SET, maska_set);
 325         __PORT(MASKA_TOGGLE, maska_toggle);
 326         __PORT(MASKB, maskb);
 327         __PORT(MASKB_CLEAR, maskb_clear);
 328         __PORT(MASKB_SET, maskb_set);
 329         __PORT(MASKB_TOGGLE, maskb_toggle);
 330         __PORT(DIR, dir);
 331         __PORT(POLAR, polar);
 332         __PORT(EDGE, edge);
 333         __PORT(BOTH, both);
 334         __PORT(INEN, inen);
 335 #endif
 336         _buf[-1] = '\0';
 337         d(buf, 16, base + REGS_OFF(gpio, data));
 338 }
 339 #define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
 340
 341 /*
 342  * PPI
 343  */
 344 #define __PPI(uname, lname) __REGS(ppi, #uname, lname)
 345 static void __init __maybe_unused
 346 bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
 347 {
 348         char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
 349         __PPI(CONTROL, control);
 350         __PPI(STATUS, status);
 351         __PPI(COUNT, count);
 352         __PPI(DELAY, delay);
 353         __PPI(FRAME, frame);
 354 }
 355 #define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
 356
 357 /*
 358  * SPI
 359  */
 360 #define __SPI(uname, lname) __REGS(spi, #uname, lname)
 361 static void __init __maybe_unused
 362 bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
 363 {
 364         char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
 365         __SPI(CTL, ctl);
 366         __SPI(FLG, flg);
 367         __SPI(STAT, stat);
 368         __SPI(TDBR, tdbr);
 369         __SPI(RDBR, rdbr);
 370         __SPI(BAUD, baud);
 371         __SPI(SHADOW, shadow);
 372 }
 373 #define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
 374
 375 /*
 376  * SPORT
 377  */
 378 static inline int sport_width(void *mmr)
 379 {
 380         unsigned long lmmr = (unsigned long)mmr;
 381         if ((lmmr & 0xff) == 0x10)
 382                 /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
 383                 lmmr -= 0xc;
 384         else
 385                 /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
 386                 lmmr += 0xc;
 387         /* extract SLEN field from control register 2 and add 1 */
 388         return (bfin_read16(lmmr) & 0x1f) + 1;
 389 }
 390 static int sport_set(void *mmr, u64 val)
 391 {
 392         unsigned long flags;
 393         local_irq_save(flags);
 394         if (sport_width(mmr) <= 16)
 395                 bfin_write16(mmr, val);
 396         else
 397                 bfin_write32(mmr, val);
 398         local_irq_restore(flags);
 399         return 0;
 400 }
 401 static int sport_get(void *mmr, u64 *val)
 402 {
 403         unsigned long flags;
 404         local_irq_save(flags);
 405         if (sport_width(mmr) <= 16)
 406                 *val = bfin_read16(mmr);
 407         else
 408                 *val = bfin_read32(mmr);
 409         local_irq_restore(flags);
 410         return 0;
 411 }
 412 DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
 413 /*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
 414 DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
 415 #define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
 416 #define _D_SPORT(name, perms, fops) \
 417         do { \
 418                 strcpy(_buf, #name); \
 419                 debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
 420         } while (0)
 421 #define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
 422 #define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
 423 #define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
 424 #define __SPORT(name, bits) \
 425         do { \
 426                 strcpy(_buf, #name); \
 427                 debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
 428         } while (0)
 429 static void __init __maybe_unused
 430 bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
 431 {
 432         char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
 433         __SPORT(CHNL, 16);
 434         __SPORT(MCMC1, 16);
 435         __SPORT(MCMC2, 16);
 436         __SPORT(MRCS0, 32);
 437         __SPORT(MRCS1, 32);
 438         __SPORT(MRCS2, 32);
 439         __SPORT(MRCS3, 32);
 440         __SPORT(MTCS0, 32);
 441         __SPORT(MTCS1, 32);
 442         __SPORT(MTCS2, 32);
 443         __SPORT(MTCS3, 32);
 444         __SPORT(RCLKDIV, 16);
 445         __SPORT(RCR1, 16);
 446         __SPORT(RCR2, 16);
 447         __SPORT(RFSDIV, 16);
 448         __SPORT_RW(RX);
 449         __SPORT(STAT, 16);
 450         __SPORT(TCLKDIV, 16);
 451         __SPORT(TCR1, 16);
 452         __SPORT(TCR2, 16);
 453         __SPORT(TFSDIV, 16);
 454         __SPORT_WO(TX);
 455 }
 456 #define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
 457
 458 /*
 459  * TWI
 460  */
 461 #define __TWI(uname, lname) __REGS(twi, #uname, lname)
 462 static void __init __maybe_unused
 463 bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
 464 {
 465         char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
 466         __TWI(CLKDIV, clkdiv);
 467         __TWI(CONTROL, control);
 468         __TWI(SLAVE_CTL, slave_ctl);
 469         __TWI(SLAVE_STAT, slave_stat);
 470         __TWI(SLAVE_ADDR, slave_addr);
 471         __TWI(MASTER_CTL, master_ctl);
 472         __TWI(MASTER_STAT, master_stat);
 473         __TWI(MASTER_ADDR, master_addr);
 474         __TWI(INT_STAT, int_stat);
 475         __TWI(INT_MASK, int_mask);
 476         __TWI(FIFO_CTL, fifo_ctl);
 477         __TWI(FIFO_STAT, fifo_stat);
 478         __TWI(XMT_DATA8, xmt_data8);
 479         __TWI(XMT_DATA16, xmt_data16);
 480         __TWI(RCV_DATA8, rcv_data8);
 481         __TWI(RCV_DATA16, rcv_data16);
 482 }
 483 #define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
 484
 485 /*
 486  * UART
 487  */
 488 #define __UART(uname, lname) __REGS(uart, #uname, lname)
 489 static void __init __maybe_unused
 490 bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
 491 {
 492         char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
 493 #ifdef BFIN_UART_BF54X_STYLE
 494         __UART(DLL, dll);
 495         __UART(DLH, dlh);
 496         __UART(GCTL, gctl);
 497         __UART(LCR, lcr);
 498         __UART(MCR, mcr);
 499         __UART(LSR, lsr);
 500         __UART(MSR, msr);
 501         __UART(SCR, scr);
 502         __UART(IER_SET, ier_set);
 503         __UART(IER_CLEAR, ier_clear);
 504         __UART(THR, thr);
 505         __UART(RBR, rbr);
 506 #else
 507         __UART(DLL, dll);
 508         __UART(THR, thr);
 509         __UART(RBR, rbr);
 510         __UART(DLH, dlh);
 511         __UART(IER, ier);
 512         __UART(IIR, iir);
 513         __UART(LCR, lcr);
 514         __UART(MCR, mcr);
 515         __UART(LSR, lsr);
 516         __UART(MSR, msr);
 517         __UART(SCR, scr);
 518         __UART(GCTL, gctl);
 519 #endif
 520 }
 521 #define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
 522
 523 /*
 524  * The actual debugfs generation
 525  */
 526 static struct dentry *debug_mmrs_dentry;
 527
 528 static int __init bfin_debug_mmrs_init(void)
 529 {
 530         struct dentry *top, *parent;
 531
 532         pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
 533
 534         top = debugfs_create_dir("blackfin", NULL);
 535         if (top == NULL)
 536                 return -1;
 537
 538         parent = debugfs_create_dir("core_regs", top);
 539         debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
 540         debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
 541         debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
 542         D_SYSREG(cycles);
 543         D_SYSREG(cycles2);
 544         D_SYSREG(emudat);
 545         D_SYSREG(seqstat);
 546         D_SYSREG(syscfg);
 547
 548         /* Core MMRs */
 549         parent = debugfs_create_dir("ctimer", top);
 550         D32(TCNTL);
 551         D32(TCOUNT);
 552         D32(TPERIOD);
 553         D32(TSCALE);
 554
 555         parent = debugfs_create_dir("cec", top);
 556         D32(EVT0);
 557         D32(EVT1);
 558         D32(EVT2);
 559         D32(EVT3);
 560         D32(EVT4);
 561         D32(EVT5);
 562         D32(EVT6);
 563         D32(EVT7);
 564         D32(EVT8);
 565         D32(EVT9);
 566         D32(EVT10);
 567         D32(EVT11);
 568         D32(EVT12);
 569         D32(EVT13);
 570         D32(EVT14);
 571         D32(EVT15);
 572         D32(EVT_OVERRIDE);
 573         D32(IMASK);
 574         D32(IPEND);
 575         D32(ILAT);
 576         D32(IPRIO);
 577
 578         parent = debugfs_create_dir("debug", top);
 579         D32(DBGSTAT);
 580         D32(DSPID);
 581
 582         parent = debugfs_create_dir("mmu", top);
 583         D32(SRAM_BASE_ADDRESS);
 584         D32(DCPLB_ADDR0);
 585         D32(DCPLB_ADDR10);
 586         D32(DCPLB_ADDR11);
 587         D32(DCPLB_ADDR12);
 588         D32(DCPLB_ADDR13);
 589         D32(DCPLB_ADDR14);
 590         D32(DCPLB_ADDR15);
 591         D32(DCPLB_ADDR1);
 592         D32(DCPLB_ADDR2);
 593         D32(DCPLB_ADDR3);
 594         D32(DCPLB_ADDR4);
 595         D32(DCPLB_ADDR5);
 596         D32(DCPLB_ADDR6);
 597         D32(DCPLB_ADDR7);
 598         D32(DCPLB_ADDR8);
 599         D32(DCPLB_ADDR9);
 600         D32(DCPLB_DATA0);
 601         D32(DCPLB_DATA10);
 602         D32(DCPLB_DATA11);
 603         D32(DCPLB_DATA12);
 604         D32(DCPLB_DATA13);
 605         D32(DCPLB_DATA14);
 606         D32(DCPLB_DATA15);
 607         D32(DCPLB_DATA1);
 608         D32(DCPLB_DATA2);
 609         D32(DCPLB_DATA3);
 610         D32(DCPLB_DATA4);
 611         D32(DCPLB_DATA5);
 612         D32(DCPLB_DATA6);
 613         D32(DCPLB_DATA7);
 614         D32(DCPLB_DATA8);
 615         D32(DCPLB_DATA9);
 616         D32(DCPLB_FAULT_ADDR);
 617         D32(DCPLB_STATUS);
 618         D32(DMEM_CONTROL);
 619         D32(DTEST_COMMAND);
 620         D32(DTEST_DATA0);
 621         D32(DTEST_DATA1);
 622
 623         D32(ICPLB_ADDR0);
 624         D32(ICPLB_ADDR1);
 625         D32(ICPLB_ADDR2);
 626         D32(ICPLB_ADDR3);
 627         D32(ICPLB_ADDR4);
 628         D32(ICPLB_ADDR5);
 629         D32(ICPLB_ADDR6);
 630         D32(ICPLB_ADDR7);
 631         D32(ICPLB_ADDR8);
 632         D32(ICPLB_ADDR9);
 633         D32(ICPLB_ADDR10);
 634         D32(ICPLB_ADDR11);
 635         D32(ICPLB_ADDR12);
 636         D32(ICPLB_ADDR13);
 637         D32(ICPLB_ADDR14);
 638         D32(ICPLB_ADDR15);
 639         D32(ICPLB_DATA0);
 640         D32(ICPLB_DATA1);
 641         D32(ICPLB_DATA2);
 642         D32(ICPLB_DATA3);
 643         D32(ICPLB_DATA4);
 644         D32(ICPLB_DATA5);
 645         D32(ICPLB_DATA6);
 646         D32(ICPLB_DATA7);
 647         D32(ICPLB_DATA8);
 648         D32(ICPLB_DATA9);
 649         D32(ICPLB_DATA10);
 650         D32(ICPLB_DATA11);
 651         D32(ICPLB_DATA12);
 652         D32(ICPLB_DATA13);
 653         D32(ICPLB_DATA14);
 654         D32(ICPLB_DATA15);
 655         D32(ICPLB_FAULT_ADDR);
 656         D32(ICPLB_STATUS);
 657         D32(IMEM_CONTROL);
 658         if (!ANOMALY_05000481) {
 659                 D32(ITEST_COMMAND);
 660                 D32(ITEST_DATA0);
 661                 D32(ITEST_DATA1);
 662         }
 663
 664         parent = debugfs_create_dir("perf", top);
 665         D32(PFCNTR0);
 666         D32(PFCNTR1);
 667         D32(PFCTL);
 668
 669         parent = debugfs_create_dir("trace", top);
 670         D32(TBUF);
 671         D32(TBUFCTL);
 672         D32(TBUFSTAT);
 673
 674         parent = debugfs_create_dir("watchpoint", top);
 675         D32(WPIACTL);
 676         D32(WPIA0);
 677         D32(WPIA1);
 678         D32(WPIA2);
 679         D32(WPIA3);
 680         D32(WPIA4);
 681         D32(WPIA5);
 682         D32(WPIACNT0);
 683         D32(WPIACNT1);
 684         D32(WPIACNT2);
 685         D32(WPIACNT3);
 686         D32(WPIACNT4);
 687         D32(WPIACNT5);
 688         D32(WPDACTL);
 689         D32(WPDA0);
 690         D32(WPDA1);
 691         D32(WPDACNT0);
 692         D32(WPDACNT1);
 693         D32(WPSTAT);
 694
 695         /* System MMRs */
 696 #ifdef ATAPI_CONTROL
 697         parent = debugfs_create_dir("atapi", top);
 698         D16(ATAPI_CONTROL);
 699         D16(ATAPI_DEV_ADDR);
 700         D16(ATAPI_DEV_RXBUF);
 701         D16(ATAPI_DEV_TXBUF);
 702         D16(ATAPI_DMA_TFRCNT);
 703         D16(ATAPI_INT_MASK);
 704         D16(ATAPI_INT_STATUS);
 705         D16(ATAPI_LINE_STATUS);
 706         D16(ATAPI_MULTI_TIM_0);
 707         D16(ATAPI_MULTI_TIM_1);
 708         D16(ATAPI_MULTI_TIM_2);
 709         D16(ATAPI_PIO_TFRCNT);
 710         D16(ATAPI_PIO_TIM_0);
 711         D16(ATAPI_PIO_TIM_1);
 712         D16(ATAPI_REG_TIM_0);
 713         D16(ATAPI_SM_STATE);
 714         D16(ATAPI_STATUS);
 715         D16(ATAPI_TERMINATE);
 716         D16(ATAPI_UDMAOUT_TFRCNT);
 717         D16(ATAPI_ULTRA_TIM_0);
 718         D16(ATAPI_ULTRA_TIM_1);
 719         D16(ATAPI_ULTRA_TIM_2);
 720         D16(ATAPI_ULTRA_TIM_3);
 721         D16(ATAPI_UMAIN_TFRCNT);
 722         D16(ATAPI_XFER_LEN);
 723 #endif
 724
 725 #if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
 726         parent = debugfs_create_dir("can", top);
 727 # ifdef CAN_MC1
 728         bfin_debug_mmrs_can(parent, CAN_MC1, -1);
 729 # endif
 730 # ifdef CAN0_MC1
 731         CAN(0);
 732 # endif
 733 # ifdef CAN1_MC1
 734         CAN(1);
 735 # endif
 736 #endif
 737
 738 #ifdef CNT_COMMAND
 739         parent = debugfs_create_dir("counter", top);
 740         D16(CNT_COMMAND);
 741         D16(CNT_CONFIG);
 742         D32(CNT_COUNTER);
 743         D16(CNT_DEBOUNCE);
 744         D16(CNT_IMASK);
 745         D32(CNT_MAX);
 746         D32(CNT_MIN);
 747         D16(CNT_STATUS);
 748 #endif
 749
 750         parent = debugfs_create_dir("dmac", top);
 751 #ifdef DMAC_TC_CNT
 752         D16(DMAC_TC_CNT);
 753         D16(DMAC_TC_PER);
 754 #endif
 755 #ifdef DMAC0_TC_CNT
 756         D16(DMAC0_TC_CNT);
 757         D16(DMAC0_TC_PER);
 758 #endif
 759 #ifdef DMAC1_TC_CNT
 760         D16(DMAC1_TC_CNT);
 761         D16(DMAC1_TC_PER);
 762 #endif
 763 #ifdef DMAC1_PERIMUX
 764         D16(DMAC1_PERIMUX);
 765 #endif
 766
 767 #ifdef __ADSPBF561__
 768         /* XXX: should rewrite the MMR map */
 769 # define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
 770 # define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
 771 # define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
 772 # define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
 773 # define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
 774 # define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
 775 # define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
 776 # define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
 777 # define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
 778 # define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
 779 # define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
 780 # define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
 781 # define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
 782 # define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
 783 # define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
 784 # define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
 785 # define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
 786 # define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
 787 # define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
 788 # define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
 789 # define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
 790 # define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
 791 # define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
 792 # define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
 793 #endif
 794         parent = debugfs_create_dir("dma", top);
 795         DMA(0);
 796         DMA(1);
 797         DMA(1);
 798         DMA(2);
 799         DMA(3);
 800         DMA(4);
 801         DMA(5);
 802         DMA(6);
 803         DMA(7);
 804 #ifdef DMA8_NEXT_DESC_PTR
 805         DMA(8);
 806         DMA(9);
 807         DMA(10);
 808         DMA(11);
 809 #endif
 810 #ifdef DMA12_NEXT_DESC_PTR
 811         DMA(12);
 812         DMA(13);
 813         DMA(14);
 814         DMA(15);
 815         DMA(16);
 816         DMA(17);
 817         DMA(18);
 818         DMA(19);
 819 #endif
 820 #ifdef DMA20_NEXT_DESC_PTR
 821         DMA(20);
 822         DMA(21);
 823         DMA(22);
 824         DMA(23);
 825 #endif
 826
 827         parent = debugfs_create_dir("ebiu_amc", top);
 828         D32(EBIU_AMBCTL0);
 829         D32(EBIU_AMBCTL1);
 830         D16(EBIU_AMGCTL);
 831 #ifdef EBIU_MBSCTL
 832         D16(EBIU_MBSCTL);
 833         D32(EBIU_ARBSTAT);
 834         D32(EBIU_MODE);
 835         D16(EBIU_FCTL);
 836 #endif
 837
 838 #ifdef EBIU_SDGCTL
 839         parent = debugfs_create_dir("ebiu_sdram", top);
 840 # ifdef __ADSPBF561__
 841         D32(EBIU_SDBCTL);
 842 # else
 843         D16(EBIU_SDBCTL);
 844 # endif
 845         D32(EBIU_SDGCTL);
 846         D16(EBIU_SDRRC);
 847         D16(EBIU_SDSTAT);
 848 #endif
 849
 850 #ifdef EBIU_DDRACCT
 851         parent = debugfs_create_dir("ebiu_ddr", top);
 852         D32(EBIU_DDRACCT);
 853         D32(EBIU_DDRARCT);
 854         D32(EBIU_DDRBRC0);
 855         D32(EBIU_DDRBRC1);
 856         D32(EBIU_DDRBRC2);
 857         D32(EBIU_DDRBRC3);
 858         D32(EBIU_DDRBRC4);
 859         D32(EBIU_DDRBRC5);
 860         D32(EBIU_DDRBRC6);
 861         D32(EBIU_DDRBRC7);
 862         D32(EBIU_DDRBWC0);
 863         D32(EBIU_DDRBWC1);
 864         D32(EBIU_DDRBWC2);
 865         D32(EBIU_DDRBWC3);
 866         D32(EBIU_DDRBWC4);
 867         D32(EBIU_DDRBWC5);
 868         D32(EBIU_DDRBWC6);
 869         D32(EBIU_DDRBWC7);
 870         D32(EBIU_DDRCTL0);
 871         D32(EBIU_DDRCTL1);
 872         D32(EBIU_DDRCTL2);
 873         D32(EBIU_DDRCTL3);
 874         D32(EBIU_DDRGC0);
 875         D32(EBIU_DDRGC1);
 876         D32(EBIU_DDRGC2);
 877         D32(EBIU_DDRGC3);
 878         D32(EBIU_DDRMCCL);
 879         D32(EBIU_DDRMCEN);
 880         D32(EBIU_DDRQUE);
 881         D32(EBIU_DDRTACT);
 882         D32(EBIU_ERRADD);
 883         D16(EBIU_ERRMST);
 884         D16(EBIU_RSTCTL);
 885 #endif
 886
 887 #ifdef EMAC_ADDRHI
 888         parent = debugfs_create_dir("emac", top);
 889         D32(EMAC_ADDRHI);
 890         D32(EMAC_ADDRLO);
 891         D32(EMAC_FLC);
 892         D32(EMAC_HASHHI);
 893         D32(EMAC_HASHLO);
 894         D32(EMAC_MMC_CTL);
 895         D32(EMAC_MMC_RIRQE);
 896         D32(EMAC_MMC_RIRQS);
 897         D32(EMAC_MMC_TIRQE);
 898         D32(EMAC_MMC_TIRQS);
 899         D32(EMAC_OPMODE);
 900         D32(EMAC_RXC_ALIGN);
 901         D32(EMAC_RXC_ALLFRM);
 902         D32(EMAC_RXC_ALLOCT);
 903         D32(EMAC_RXC_BROAD);
 904         D32(EMAC_RXC_DMAOVF);
 905         D32(EMAC_RXC_EQ64);
 906         D32(EMAC_RXC_FCS);
 907         D32(EMAC_RXC_GE1024);
 908         D32(EMAC_RXC_LNERRI);
 909         D32(EMAC_RXC_LNERRO);
 910         D32(EMAC_RXC_LONG);
 911         D32(EMAC_RXC_LT1024);
 912         D32(EMAC_RXC_LT128);
 913         D32(EMAC_RXC_LT256);
 914         D32(EMAC_RXC_LT512);
 915         D32(EMAC_RXC_MACCTL);
 916         D32(EMAC_RXC_MULTI);
 917         D32(EMAC_RXC_OCTET);
 918         D32(EMAC_RXC_OK);
 919         D32(EMAC_RXC_OPCODE);
 920         D32(EMAC_RXC_PAUSE);
 921         D32(EMAC_RXC_SHORT);
 922         D32(EMAC_RXC_TYPED);
 923         D32(EMAC_RXC_UNICST);
 924         D32(EMAC_RX_IRQE);
 925         D32(EMAC_RX_STAT);
 926         D32(EMAC_RX_STKY);
 927         D32(EMAC_STAADD);
 928         D32(EMAC_STADAT);
 929         D32(EMAC_SYSCTL);
 930         D32(EMAC_SYSTAT);
 931         D32(EMAC_TXC_1COL);
 932         D32(EMAC_TXC_ABORT);
 933         D32(EMAC_TXC_ALLFRM);
 934         D32(EMAC_TXC_ALLOCT);
 935         D32(EMAC_TXC_BROAD);
 936         D32(EMAC_TXC_CRSERR);
 937         D32(EMAC_TXC_DEFER);
 938         D32(EMAC_TXC_DMAUND);
 939         D32(EMAC_TXC_EQ64);
 940         D32(EMAC_TXC_GE1024);
 941         D32(EMAC_TXC_GT1COL);
 942         D32(EMAC_TXC_LATECL);
 943         D32(EMAC_TXC_LT1024);
 944         D32(EMAC_TXC_LT128);
 945         D32(EMAC_TXC_LT256);
 946         D32(EMAC_TXC_LT512);
 947         D32(EMAC_TXC_MACCTL);
 948         D32(EMAC_TXC_MULTI);
 949         D32(EMAC_TXC_OCTET);
 950         D32(EMAC_TXC_OK);
 951         D32(EMAC_TXC_UNICST);
 952         D32(EMAC_TXC_XS_COL);
 953         D32(EMAC_TXC_XS_DFR);
 954         D32(EMAC_TX_IRQE);
 955         D32(EMAC_TX_STAT);
 956         D32(EMAC_TX_STKY);
 957         D32(EMAC_VLAN1);
 958         D32(EMAC_VLAN2);
 959         D32(EMAC_WKUP_CTL);
 960         D32(EMAC_WKUP_FFCMD);
 961         D32(EMAC_WKUP_FFCRC0);
 962         D32(EMAC_WKUP_FFCRC1);
 963         D32(EMAC_WKUP_FFMSK0);
 964         D32(EMAC_WKUP_FFMSK1);
 965         D32(EMAC_WKUP_FFMSK2);
 966         D32(EMAC_WKUP_FFMSK3);
 967         D32(EMAC_WKUP_FFOFF);
 968 # ifdef EMAC_PTP_ACCR
 969         D32(EMAC_PTP_ACCR);
 970         D32(EMAC_PTP_ADDEND);
 971         D32(EMAC_PTP_ALARMHI);
 972         D32(EMAC_PTP_ALARMLO);
 973         D16(EMAC_PTP_CTL);
 974         D32(EMAC_PTP_FOFF);
 975         D32(EMAC_PTP_FV1);
 976         D32(EMAC_PTP_FV2);
 977         D32(EMAC_PTP_FV3);
 978         D16(EMAC_PTP_ID_OFF);
 979         D32(EMAC_PTP_ID_SNAP);
 980         D16(EMAC_PTP_IE);
 981         D16(EMAC_PTP_ISTAT);
 982         D32(EMAC_PTP_OFFSET);
 983         D32(EMAC_PTP_PPS_PERIOD);
 984         D32(EMAC_PTP_PPS_STARTHI);
 985         D32(EMAC_PTP_PPS_STARTLO);
 986         D32(EMAC_PTP_RXSNAPHI);
 987         D32(EMAC_PTP_RXSNAPLO);
 988         D32(EMAC_PTP_TIMEHI);
 989         D32(EMAC_PTP_TIMELO);
 990         D32(EMAC_PTP_TXSNAPHI);
 991         D32(EMAC_PTP_TXSNAPLO);
 992 # endif
 993 #endif
 994
 995 #if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
 996         parent = debugfs_create_dir("eppi", top);
 997 # ifdef EPPI0_STATUS
 998         EPPI(0);
 999 # endif
1000 # ifdef EPPI1_STATUS
1001         EPPI(1);
1002 # endif
1003 # ifdef EPPI2_STATUS
1004         EPPI(2);
1005 # endif
1006 #endif
1007
1008         parent = debugfs_create_dir("gptimer", top);
1009 #ifdef TIMER_DISABLE
1010         D16(TIMER_DISABLE);
1011         D16(TIMER_ENABLE);
1012         D32(TIMER_STATUS);
1013 #endif
1014 #ifdef TIMER_DISABLE0
1015         D16(TIMER_DISABLE0);
1016         D16(TIMER_ENABLE0);
1017         D32(TIMER_STATUS0);
1018 #endif
1019 #ifdef TIMER_DISABLE1
1020         D16(TIMER_DISABLE1);
1021         D16(TIMER_ENABLE1);
1022         D32(TIMER_STATUS1);
1023 #endif
1024         /* XXX: Should convert BF561 MMR names */
1025 #ifdef TMRS4_DISABLE
1026         D16(TMRS4_DISABLE);
1027         D16(TMRS4_ENABLE);
1028         D32(TMRS4_STATUS);
1029         D16(TMRS8_DISABLE);
1030         D16(TMRS8_ENABLE);
1031         D32(TMRS8_STATUS);
1032 #endif
1033         GPTIMER(0);
1034         GPTIMER(1);
1035         GPTIMER(2);
1036 #ifdef TIMER3_CONFIG
1037         GPTIMER(3);
1038         GPTIMER(4);
1039         GPTIMER(5);
1040         GPTIMER(6);
1041         GPTIMER(7);
1042 #endif
1043 #ifdef TIMER8_CONFIG
1044         GPTIMER(8);
1045         GPTIMER(9);
1046         GPTIMER(10);
1047 #endif
1048 #ifdef TIMER11_CONFIG
1049         GPTIMER(11);
1050 #endif
1051
1052 #ifdef HMDMA0_CONTROL
1053         parent = debugfs_create_dir("hmdma", top);
1054         HMDMA(0);
1055         HMDMA(1);
1056 #endif
1057
1058 #ifdef HOST_CONTROL
1059         parent = debugfs_create_dir("hostdp", top);
1060         D16(HOST_CONTROL);
1061         D16(HOST_STATUS);
1062         D16(HOST_TIMEOUT);
1063 #endif
1064
1065 #ifdef IMDMA_S0_CONFIG
1066         parent = debugfs_create_dir("imdma", top);
1067         IMDMA(0);
1068         IMDMA(1);
1069 #endif
1070
1071 #ifdef KPAD_CTL
1072         parent = debugfs_create_dir("keypad", top);
1073         D16(KPAD_CTL);
1074         D16(KPAD_PRESCALE);
1075         D16(KPAD_MSEL);
1076         D16(KPAD_ROWCOL);
1077         D16(KPAD_STAT);
1078         D16(KPAD_SOFTEVAL);
1079 #endif
1080
1081         parent = debugfs_create_dir("mdma", top);
1082         MDMA(0);
1083         MDMA(1);
1084 #ifdef MDMA_D2_CONFIG
1085         MDMA(2);
1086         MDMA(3);
1087 #endif
1088
1089 #ifdef MXVR_CONFIG
1090         parent = debugfs_create_dir("mxvr", top);
1091         D16(MXVR_CONFIG);
1092 # ifdef MXVR_PLL_CTL_0
1093         D32(MXVR_PLL_CTL_0);
1094 # endif
1095         D32(MXVR_STATE_0);
1096         D32(MXVR_STATE_1);
1097         D32(MXVR_INT_STAT_0);
1098         D32(MXVR_INT_STAT_1);
1099         D32(MXVR_INT_EN_0);
1100         D32(MXVR_INT_EN_1);
1101         D16(MXVR_POSITION);
1102         D16(MXVR_MAX_POSITION);
1103         D16(MXVR_DELAY);
1104         D16(MXVR_MAX_DELAY);
1105         D32(MXVR_LADDR);
1106         D16(MXVR_GADDR);
1107         D32(MXVR_AADDR);
1108         D32(MXVR_ALLOC_0);
1109         D32(MXVR_ALLOC_1);
1110         D32(MXVR_ALLOC_2);
1111         D32(MXVR_ALLOC_3);
1112         D32(MXVR_ALLOC_4);
1113         D32(MXVR_ALLOC_5);
1114         D32(MXVR_ALLOC_6);
1115         D32(MXVR_ALLOC_7);
1116         D32(MXVR_ALLOC_8);
1117         D32(MXVR_ALLOC_9);
1118         D32(MXVR_ALLOC_10);
1119         D32(MXVR_ALLOC_11);
1120         D32(MXVR_ALLOC_12);
1121         D32(MXVR_ALLOC_13);
1122         D32(MXVR_ALLOC_14);
1123         D32(MXVR_SYNC_LCHAN_0);
1124         D32(MXVR_SYNC_LCHAN_1);
1125         D32(MXVR_SYNC_LCHAN_2);
1126         D32(MXVR_SYNC_LCHAN_3);
1127         D32(MXVR_SYNC_LCHAN_4);
1128         D32(MXVR_SYNC_LCHAN_5);
1129         D32(MXVR_SYNC_LCHAN_6);
1130         D32(MXVR_SYNC_LCHAN_7);
1131         D32(MXVR_DMA0_CONFIG);
1132         D32(MXVR_DMA0_START_ADDR);
1133         D16(MXVR_DMA0_COUNT);
1134         D32(MXVR_DMA0_CURR_ADDR);
1135         D16(MXVR_DMA0_CURR_COUNT);
1136         D32(MXVR_DMA1_CONFIG);
1137         D32(MXVR_DMA1_START_ADDR);
1138         D16(MXVR_DMA1_COUNT);
1139         D32(MXVR_DMA1_CURR_ADDR);
1140         D16(MXVR_DMA1_CURR_COUNT);
1141         D32(MXVR_DMA2_CONFIG);
1142         D32(MXVR_DMA2_START_ADDR);
1143         D16(MXVR_DMA2_COUNT);
1144         D32(MXVR_DMA2_CURR_ADDR);
1145         D16(MXVR_DMA2_CURR_COUNT);
1146         D32(MXVR_DMA3_CONFIG);
1147         D32(MXVR_DMA3_START_ADDR);
1148         D16(MXVR_DMA3_COUNT);
1149         D32(MXVR_DMA3_CURR_ADDR);
1150         D16(MXVR_DMA3_CURR_COUNT);
1151         D32(MXVR_DMA4_CONFIG);
1152         D32(MXVR_DMA4_START_ADDR);
1153         D16(MXVR_DMA4_COUNT);
1154         D32(MXVR_DMA4_CURR_ADDR);
1155         D16(MXVR_DMA4_CURR_COUNT);
1156         D32(MXVR_DMA5_CONFIG);
1157         D32(MXVR_DMA5_START_ADDR);
1158         D16(MXVR_DMA5_COUNT);
1159         D32(MXVR_DMA5_CURR_ADDR);
1160         D16(MXVR_DMA5_CURR_COUNT);
1161         D32(MXVR_DMA6_CONFIG);
1162         D32(MXVR_DMA6_START_ADDR);
1163         D16(MXVR_DMA6_COUNT);
1164         D32(MXVR_DMA6_CURR_ADDR);
1165         D16(MXVR_DMA6_CURR_COUNT);
1166         D32(MXVR_DMA7_CONFIG);
1167         D32(MXVR_DMA7_START_ADDR);
1168         D16(MXVR_DMA7_COUNT);
1169         D32(MXVR_DMA7_CURR_ADDR);
1170         D16(MXVR_DMA7_CURR_COUNT);
1171         D16(MXVR_AP_CTL);
1172         D32(MXVR_APRB_START_ADDR);
1173         D32(MXVR_APRB_CURR_ADDR);
1174         D32(MXVR_APTB_START_ADDR);
1175         D32(MXVR_APTB_CURR_ADDR);
1176         D32(MXVR_CM_CTL);
1177         D32(MXVR_CMRB_START_ADDR);
1178         D32(MXVR_CMRB_CURR_ADDR);
1179         D32(MXVR_CMTB_START_ADDR);
1180         D32(MXVR_CMTB_CURR_ADDR);
1181         D32(MXVR_RRDB_START_ADDR);
1182         D32(MXVR_RRDB_CURR_ADDR);
1183         D32(MXVR_PAT_DATA_0);
1184         D32(MXVR_PAT_EN_0);
1185         D32(MXVR_PAT_DATA_1);
1186         D32(MXVR_PAT_EN_1);
1187         D16(MXVR_FRAME_CNT_0);
1188         D16(MXVR_FRAME_CNT_1);
1189         D32(MXVR_ROUTING_0);
1190         D32(MXVR_ROUTING_1);
1191         D32(MXVR_ROUTING_2);
1192         D32(MXVR_ROUTING_3);
1193         D32(MXVR_ROUTING_4);
1194         D32(MXVR_ROUTING_5);
1195         D32(MXVR_ROUTING_6);
1196         D32(MXVR_ROUTING_7);
1197         D32(MXVR_ROUTING_8);
1198         D32(MXVR_ROUTING_9);
1199         D32(MXVR_ROUTING_10);
1200         D32(MXVR_ROUTING_11);
1201         D32(MXVR_ROUTING_12);
1202         D32(MXVR_ROUTING_13);
1203         D32(MXVR_ROUTING_14);
1204 # ifdef MXVR_PLL_CTL_1
1205         D32(MXVR_PLL_CTL_1);
1206 # endif
1207         D16(MXVR_BLOCK_CNT);
1208 # ifdef MXVR_CLK_CTL
1209         D32(MXVR_CLK_CTL);
1210 # endif
1211 # ifdef MXVR_CDRPLL_CTL
1212         D32(MXVR_CDRPLL_CTL);
1213 # endif
1214 # ifdef MXVR_FMPLL_CTL
1215         D32(MXVR_FMPLL_CTL);
1216 # endif
1217 # ifdef MXVR_PIN_CTL
1218         D16(MXVR_PIN_CTL);
1219 # endif
1220 # ifdef MXVR_SCLK_CNT
1221         D16(MXVR_SCLK_CNT);
1222 # endif
1223 #endif
1224
1225 #ifdef NFC_ADDR
1226         parent = debugfs_create_dir("nfc", top);
1227         D_WO(NFC_ADDR, 16);
1228         D_WO(NFC_CMD, 16);
1229         D_RO(NFC_COUNT, 16);
1230         D16(NFC_CTL);
1231         D_WO(NFC_DATA_RD, 16);
1232         D_WO(NFC_DATA_WR, 16);
1233         D_RO(NFC_ECC0, 16);
1234         D_RO(NFC_ECC1, 16);
1235         D_RO(NFC_ECC2, 16);
1236         D_RO(NFC_ECC3, 16);
1237         D16(NFC_IRQMASK);
1238         D16(NFC_IRQSTAT);
1239         D_WO(NFC_PGCTL, 16);
1240         D_RO(NFC_READ, 16);
1241         D16(NFC_RST);
1242         D_RO(NFC_STAT, 16);
1243 #endif
1244
1245 #ifdef OTP_CONTROL
1246         parent = debugfs_create_dir("otp", top);
1247         D16(OTP_CONTROL);
1248         D16(OTP_BEN);
1249         D16(OTP_STATUS);
1250         D32(OTP_TIMING);
1251         D32(OTP_DATA0);
1252         D32(OTP_DATA1);
1253         D32(OTP_DATA2);
1254         D32(OTP_DATA3);
1255 #endif
1256
1257 #ifdef PIXC_CTL
1258         parent = debugfs_create_dir("pixc", top);
1259         D16(PIXC_CTL);
1260         D16(PIXC_PPL);
1261         D16(PIXC_LPF);
1262         D16(PIXC_AHSTART);
1263         D16(PIXC_AHEND);
1264         D16(PIXC_AVSTART);
1265         D16(PIXC_AVEND);
1266         D16(PIXC_ATRANSP);
1267         D16(PIXC_BHSTART);
1268         D16(PIXC_BHEND);
1269         D16(PIXC_BVSTART);
1270         D16(PIXC_BVEND);
1271         D16(PIXC_BTRANSP);
1272         D16(PIXC_INTRSTAT);
1273         D32(PIXC_RYCON);
1274         D32(PIXC_GUCON);
1275         D32(PIXC_BVCON);
1276         D32(PIXC_CCBIAS);
1277         D32(PIXC_TC);
1278 #endif
1279
1280         parent = debugfs_create_dir("pll", top);
1281         D16(PLL_CTL);
1282         D16(PLL_DIV);
1283         D16(PLL_LOCKCNT);
1284         D16(PLL_STAT);
1285         D16(VR_CTL);
1286         D32(CHIPID);    /* it's part of this hardware block */
1287
1288 #if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
1289         parent = debugfs_create_dir("ppi", top);
1290 # ifdef PPI_CONTROL
1291         bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
1292 # endif
1293 # ifdef PPI0_CONTROL
1294         PPI(0);
1295 # endif
1296 # ifdef PPI1_CONTROL
1297         PPI(1);
1298 # endif
1299 #endif
1300
1301 #ifdef PWM_CTRL
1302         parent = debugfs_create_dir("pwm", top);
1303         D16(PWM_CTRL);
1304         D16(PWM_STAT);
1305         D16(PWM_TM);
1306         D16(PWM_DT);
1307         D16(PWM_GATE);
1308         D16(PWM_CHA);
1309         D16(PWM_CHB);
1310         D16(PWM_CHC);
1311         D16(PWM_SEG);
1312         D16(PWM_SYNCWT);
1313         D16(PWM_CHAL);
1314         D16(PWM_CHBL);
1315         D16(PWM_CHCL);
1316         D16(PWM_LSI);
1317         D16(PWM_STAT2);
1318 #endif
1319
1320 #ifdef RSI_CONFIG
1321         parent = debugfs_create_dir("rsi", top);
1322         D32(RSI_ARGUMENT);
1323         D16(RSI_CEATA_CONTROL);
1324         D16(RSI_CLK_CONTROL);
1325         D16(RSI_COMMAND);
1326         D16(RSI_CONFIG);
1327         D16(RSI_DATA_CNT);
1328         D16(RSI_DATA_CONTROL);
1329         D16(RSI_DATA_LGTH);
1330         D32(RSI_DATA_TIMER);
1331         D16(RSI_EMASK);
1332         D16(RSI_ESTAT);
1333         D32(RSI_FIFO);
1334         D16(RSI_FIFO_CNT);
1335         D32(RSI_MASK0);
1336         D32(RSI_MASK1);
1337         D16(RSI_PID0);
1338         D16(RSI_PID1);
1339         D16(RSI_PID2);
1340         D16(RSI_PID3);
1341         D16(RSI_PID4);
1342         D16(RSI_PID5);
1343         D16(RSI_PID6);
1344         D16(RSI_PID7);
1345         D16(RSI_PWR_CONTROL);
1346         D16(RSI_RD_WAIT_EN);
1347         D32(RSI_RESPONSE0);
1348         D32(RSI_RESPONSE1);
1349         D32(RSI_RESPONSE2);
1350         D32(RSI_RESPONSE3);
1351         D16(RSI_RESP_CMD);
1352         D32(RSI_STATUS);
1353         D_WO(RSI_STATUSCL, 16);
1354 #endif
1355
1356 #ifdef RTC_ALARM
1357         parent = debugfs_create_dir("rtc", top);
1358         D32(RTC_ALARM);
1359         D16(RTC_ICTL);
1360         D16(RTC_ISTAT);
1361         D16(RTC_PREN);
1362         D32(RTC_STAT);
1363         D16(RTC_SWCNT);
1364 #endif
1365
1366 #ifdef SDH_CFG
1367         parent = debugfs_create_dir("sdh", top);
1368         D32(SDH_ARGUMENT);
1369         D16(SDH_CFG);
1370         D16(SDH_CLK_CTL);
1371         D16(SDH_COMMAND);
1372         D_RO(SDH_DATA_CNT, 16);
1373         D16(SDH_DATA_CTL);
1374         D16(SDH_DATA_LGTH);
1375         D32(SDH_DATA_TIMER);
1376         D16(SDH_E_MASK);
1377         D16(SDH_E_STATUS);
1378         D32(SDH_FIFO);
1379         D_RO(SDH_FIFO_CNT, 16);
1380         D32(SDH_MASK0);
1381         D32(SDH_MASK1);
1382         D_RO(SDH_PID0, 16);
1383         D_RO(SDH_PID1, 16);
1384         D_RO(SDH_PID2, 16);
1385         D_RO(SDH_PID3, 16);
1386         D_RO(SDH_PID4, 16);
1387         D_RO(SDH_PID5, 16);
1388         D_RO(SDH_PID6, 16);
1389         D_RO(SDH_PID7, 16);
1390         D16(SDH_PWR_CTL);
1391         D16(SDH_RD_WAIT_EN);
1392         D_RO(SDH_RESPONSE0, 32);
1393         D_RO(SDH_RESPONSE1, 32);
1394         D_RO(SDH_RESPONSE2, 32);
1395         D_RO(SDH_RESPONSE3, 32);
1396         D_RO(SDH_RESP_CMD, 16);
1397         D_RO(SDH_STATUS, 32);
1398         D_WO(SDH_STATUS_CLR, 16);
1399 #endif
1400
1401 #ifdef SECURE_CONTROL
1402         parent = debugfs_create_dir("security", top);
1403         D16(SECURE_CONTROL);
1404         D16(SECURE_STATUS);
1405         D32(SECURE_SYSSWT);
1406 #endif
1407
1408         parent = debugfs_create_dir("sic", top);
1409         D16(SWRST);
1410         D16(SYSCR);
1411         D16(SIC_RVECT);
1412         D32(SIC_IAR0);
1413         D32(SIC_IAR1);
1414         D32(SIC_IAR2);
1415 #ifdef SIC_IAR3
1416         D32(SIC_IAR3);
1417 #endif
1418 #ifdef SIC_IAR4
1419         D32(SIC_IAR4);
1420         D32(SIC_IAR5);
1421         D32(SIC_IAR6);
1422 #endif
1423 #ifdef SIC_IAR7
1424         D32(SIC_IAR7);
1425 #endif
1426 #ifdef SIC_IAR8
1427         D32(SIC_IAR8);
1428         D32(SIC_IAR9);
1429         D32(SIC_IAR10);
1430         D32(SIC_IAR11);
1431 #endif
1432 #ifdef SIC_IMASK
1433         D32(SIC_IMASK);
1434         D32(SIC_ISR);
1435         D32(SIC_IWR);
1436 #endif
1437 #ifdef SIC_IMASK0
1438         D32(SIC_IMASK0);
1439         D32(SIC_IMASK1);
1440         D32(SIC_ISR0);
1441         D32(SIC_ISR1);
1442         D32(SIC_IWR0);
1443         D32(SIC_IWR1);
1444 #endif
1445 #ifdef SIC_IMASK2
1446         D32(SIC_IMASK2);
1447         D32(SIC_ISR2);
1448         D32(SIC_IWR2);
1449 #endif
1450 #ifdef SICB_RVECT
1451         D16(SICB_SWRST);
1452         D16(SICB_SYSCR);
1453         D16(SICB_RVECT);
1454         D32(SICB_IAR0);
1455         D32(SICB_IAR1);
1456         D32(SICB_IAR2);
1457         D32(SICB_IAR3);
1458         D32(SICB_IAR4);
1459         D32(SICB_IAR5);
1460         D32(SICB_IAR6);
1461         D32(SICB_IAR7);
1462         D32(SICB_IMASK0);
1463         D32(SICB_IMASK1);
1464         D32(SICB_ISR0);
1465         D32(SICB_ISR1);
1466         D32(SICB_IWR0);
1467         D32(SICB_IWR1);
1468 #endif
1469
1470         parent = debugfs_create_dir("spi", top);
1471 #ifdef SPI0_REGBASE
1472         SPI(0);
1473 #endif
1474 #ifdef SPI1_REGBASE
1475         SPI(1);
1476 #endif
1477 #ifdef SPI2_REGBASE
1478         SPI(2);
1479 #endif
1480
1481         parent = debugfs_create_dir("sport", top);
1482 #ifdef SPORT0_STAT
1483         SPORT(0);
1484 #endif
1485 #ifdef SPORT1_STAT
1486         SPORT(1);
1487 #endif
1488 #ifdef SPORT2_STAT
1489         SPORT(2);
1490 #endif
1491 #ifdef SPORT3_STAT
1492         SPORT(3);
1493 #endif
1494
1495 #if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
1496         parent = debugfs_create_dir("twi", top);
1497 # ifdef TWI_CLKDIV
1498         bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
1499 # endif
1500 # ifdef TWI0_CLKDIV
1501         TWI(0);
1502 # endif
1503 # ifdef TWI1_CLKDIV
1504         TWI(1);
1505 # endif
1506 #endif
1507
1508         parent = debugfs_create_dir("uart", top);
1509 #ifdef BFIN_UART_DLL
1510         bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
1511 #endif
1512 #ifdef UART0_DLL
1513         UART(0);
1514 #endif
1515 #ifdef UART1_DLL
1516         UART(1);
1517 #endif
1518 #ifdef UART2_DLL
1519         UART(2);
1520 #endif
1521 #ifdef UART3_DLL
1522         UART(3);
1523 #endif
1524
1525 #ifdef USB_FADDR
1526         parent = debugfs_create_dir("usb", top);
1527         D16(USB_FADDR);
1528         D16(USB_POWER);
1529         D16(USB_INTRTX);
1530         D16(USB_INTRRX);
1531         D16(USB_INTRTXE);
1532         D16(USB_INTRRXE);
1533         D16(USB_INTRUSB);
1534         D16(USB_INTRUSBE);
1535         D16(USB_FRAME);
1536         D16(USB_INDEX);
1537         D16(USB_TESTMODE);
1538         D16(USB_GLOBINTR);
1539         D16(USB_GLOBAL_CTL);
1540         D16(USB_TX_MAX_PACKET);
1541         D16(USB_CSR0);
1542         D16(USB_TXCSR);
1543         D16(USB_RX_MAX_PACKET);
1544         D16(USB_RXCSR);
1545         D16(USB_COUNT0);
1546         D16(USB_RXCOUNT);
1547         D16(USB_TXTYPE);
1548         D16(USB_NAKLIMIT0);
1549         D16(USB_TXINTERVAL);
1550         D16(USB_RXTYPE);
1551         D16(USB_RXINTERVAL);
1552         D16(USB_TXCOUNT);
1553         D16(USB_EP0_FIFO);
1554         D16(USB_EP1_FIFO);
1555         D16(USB_EP2_FIFO);
1556         D16(USB_EP3_FIFO);
1557         D16(USB_EP4_FIFO);
1558         D16(USB_EP5_FIFO);
1559         D16(USB_EP6_FIFO);
1560         D16(USB_EP7_FIFO);
1561         D16(USB_OTG_DEV_CTL);
1562         D16(USB_OTG_VBUS_IRQ);
1563         D16(USB_OTG_VBUS_MASK);
1564         D16(USB_LINKINFO);
1565         D16(USB_VPLEN);
1566         D16(USB_HS_EOF1);
1567         D16(USB_FS_EOF1);
1568         D16(USB_LS_EOF1);
1569         D16(USB_APHY_CNTRL);
1570         D16(USB_APHY_CALIB);
1571         D16(USB_APHY_CNTRL2);
1572         D16(USB_PHY_TEST);
1573         D16(USB_PLLOSC_CTRL);
1574         D16(USB_SRP_CLKDIV);
1575         D16(USB_EP_NI0_TXMAXP);
1576         D16(USB_EP_NI0_TXCSR);
1577         D16(USB_EP_NI0_RXMAXP);
1578         D16(USB_EP_NI0_RXCSR);
1579         D16(USB_EP_NI0_RXCOUNT);
1580         D16(USB_EP_NI0_TXTYPE);
1581         D16(USB_EP_NI0_TXINTERVAL);
1582         D16(USB_EP_NI0_RXTYPE);
1583         D16(USB_EP_NI0_RXINTERVAL);
1584         D16(USB_EP_NI0_TXCOUNT);
1585         D16(USB_EP_NI1_TXMAXP);
1586         D16(USB_EP_NI1_TXCSR);
1587         D16(USB_EP_NI1_RXMAXP);
1588         D16(USB_EP_NI1_RXCSR);
1589         D16(USB_EP_NI1_RXCOUNT);
1590         D16(USB_EP_NI1_TXTYPE);
1591         D16(USB_EP_NI1_TXINTERVAL);
1592         D16(USB_EP_NI1_RXTYPE);
1593         D16(USB_EP_NI1_RXINTERVAL);
1594         D16(USB_EP_NI1_TXCOUNT);
1595         D16(USB_EP_NI2_TXMAXP);
1596         D16(USB_EP_NI2_TXCSR);
1597         D16(USB_EP_NI2_RXMAXP);
1598         D16(USB_EP_NI2_RXCSR);
1599         D16(USB_EP_NI2_RXCOUNT);
1600         D16(USB_EP_NI2_TXTYPE);
1601         D16(USB_EP_NI2_TXINTERVAL);
1602         D16(USB_EP_NI2_RXTYPE);
1603         D16(USB_EP_NI2_RXINTERVAL);
1604         D16(USB_EP_NI2_TXCOUNT);
1605         D16(USB_EP_NI3_TXMAXP);
1606         D16(USB_EP_NI3_TXCSR);
1607         D16(USB_EP_NI3_RXMAXP);
1608         D16(USB_EP_NI3_RXCSR);
1609         D16(USB_EP_NI3_RXCOUNT);
1610         D16(USB_EP_NI3_TXTYPE);
1611         D16(USB_EP_NI3_TXINTERVAL);
1612         D16(USB_EP_NI3_RXTYPE);
1613         D16(USB_EP_NI3_RXINTERVAL);
1614         D16(USB_EP_NI3_TXCOUNT);
1615         D16(USB_EP_NI4_TXMAXP);
1616         D16(USB_EP_NI4_TXCSR);
1617         D16(USB_EP_NI4_RXMAXP);
1618         D16(USB_EP_NI4_RXCSR);
1619         D16(USB_EP_NI4_RXCOUNT);
1620         D16(USB_EP_NI4_TXTYPE);
1621         D16(USB_EP_NI4_TXINTERVAL);
1622         D16(USB_EP_NI4_RXTYPE);
1623         D16(USB_EP_NI4_RXINTERVAL);
1624         D16(USB_EP_NI4_TXCOUNT);
1625         D16(USB_EP_NI5_TXMAXP);
1626         D16(USB_EP_NI5_TXCSR);
1627         D16(USB_EP_NI5_RXMAXP);
1628         D16(USB_EP_NI5_RXCSR);
1629         D16(USB_EP_NI5_RXCOUNT);
1630         D16(USB_EP_NI5_TXTYPE);
1631         D16(USB_EP_NI5_TXINTERVAL);
1632         D16(USB_EP_NI5_RXTYPE);
1633         D16(USB_EP_NI5_RXINTERVAL);
1634         D16(USB_EP_NI5_TXCOUNT);
1635         D16(USB_EP_NI6_TXMAXP);
1636         D16(USB_EP_NI6_TXCSR);
1637         D16(USB_EP_NI6_RXMAXP);
1638         D16(USB_EP_NI6_RXCSR);
1639         D16(USB_EP_NI6_RXCOUNT);
1640         D16(USB_EP_NI6_TXTYPE);
1641         D16(USB_EP_NI6_TXINTERVAL);
1642         D16(USB_EP_NI6_RXTYPE);
1643         D16(USB_EP_NI6_RXINTERVAL);
1644         D16(USB_EP_NI6_TXCOUNT);
1645         D16(USB_EP_NI7_TXMAXP);
1646         D16(USB_EP_NI7_TXCSR);
1647         D16(USB_EP_NI7_RXMAXP);
1648         D16(USB_EP_NI7_RXCSR);
1649         D16(USB_EP_NI7_RXCOUNT);
1650         D16(USB_EP_NI7_TXTYPE);
1651         D16(USB_EP_NI7_TXINTERVAL);
1652         D16(USB_EP_NI7_RXTYPE);
1653         D16(USB_EP_NI7_RXINTERVAL);
1654         D16(USB_EP_NI7_TXCOUNT);
1655         D16(USB_DMA_INTERRUPT);
1656         D16(USB_DMA0CONTROL);
1657         D16(USB_DMA0ADDRLOW);
1658         D16(USB_DMA0ADDRHIGH);
1659         D16(USB_DMA0COUNTLOW);
1660         D16(USB_DMA0COUNTHIGH);
1661         D16(USB_DMA1CONTROL);
1662         D16(USB_DMA1ADDRLOW);
1663         D16(USB_DMA1ADDRHIGH);
1664         D16(USB_DMA1COUNTLOW);
1665         D16(USB_DMA1COUNTHIGH);
1666         D16(USB_DMA2CONTROL);
1667         D16(USB_DMA2ADDRLOW);
1668         D16(USB_DMA2ADDRHIGH);
1669         D16(USB_DMA2COUNTLOW);
1670         D16(USB_DMA2COUNTHIGH);
1671         D16(USB_DMA3CONTROL);
1672         D16(USB_DMA3ADDRLOW);
1673         D16(USB_DMA3ADDRHIGH);
1674         D16(USB_DMA3COUNTLOW);
1675         D16(USB_DMA3COUNTHIGH);
1676         D16(USB_DMA4CONTROL);
1677         D16(USB_DMA4ADDRLOW);
1678         D16(USB_DMA4ADDRHIGH);
1679         D16(USB_DMA4COUNTLOW);
1680         D16(USB_DMA4COUNTHIGH);
1681         D16(USB_DMA5CONTROL);
1682         D16(USB_DMA5ADDRLOW);
1683         D16(USB_DMA5ADDRHIGH);
1684         D16(USB_DMA5COUNTLOW);
1685         D16(USB_DMA5COUNTHIGH);
1686         D16(USB_DMA6CONTROL);
1687         D16(USB_DMA6ADDRLOW);
1688         D16(USB_DMA6ADDRHIGH);
1689         D16(USB_DMA6COUNTLOW);
1690         D16(USB_DMA6COUNTHIGH);
1691         D16(USB_DMA7CONTROL);
1692         D16(USB_DMA7ADDRLOW);
1693         D16(USB_DMA7ADDRHIGH);
1694         D16(USB_DMA7COUNTLOW);
1695         D16(USB_DMA7COUNTHIGH);
1696 #endif
1697
1698 #ifdef WDOG_CNT
1699         parent = debugfs_create_dir("watchdog", top);
1700         D32(WDOG_CNT);
1701         D16(WDOG_CTL);
1702         D32(WDOG_STAT);
1703 #endif
1704 #ifdef WDOGA_CNT
1705         parent = debugfs_create_dir("watchdog", top);
1706         D32(WDOGA_CNT);
1707         D16(WDOGA_CTL);
1708         D32(WDOGA_STAT);
1709         D32(WDOGB_CNT);
1710         D16(WDOGB_CTL);
1711         D32(WDOGB_STAT);
1712 #endif
1713
1714         /* BF533 glue */
1715 #ifdef FIO_FLAG_D
1716 #define PORTFIO FIO_FLAG_D
1717 #endif
1718         /* BF561 glue */
1719 #ifdef FIO0_FLAG_D
1720 #define PORTFIO FIO0_FLAG_D
1721 #endif
1722 #ifdef FIO1_FLAG_D
1723 #define PORTGIO FIO1_FLAG_D
1724 #endif
1725 #ifdef FIO2_FLAG_D
1726 #define PORTHIO FIO2_FLAG_D
1727 #endif
1728         parent = debugfs_create_dir("port", top);
1729 #ifdef PORTFIO
1730         PORT(PORTFIO, 'F');
1731 #endif
1732 #ifdef PORTGIO
1733         PORT(PORTGIO, 'G');
1734 #endif
1735 #ifdef PORTHIO
1736         PORT(PORTHIO, 'H');
1737 #endif
1738
1739 #ifdef __ADSPBF51x__
1740         D16(PORTF_FER);
1741         D16(PORTF_DRIVE);
1742         D16(PORTF_HYSTERESIS);
1743         D16(PORTF_MUX);
1744
1745         D16(PORTG_FER);
1746         D16(PORTG_DRIVE);
1747         D16(PORTG_HYSTERESIS);
1748         D16(PORTG_MUX);
1749
1750         D16(PORTH_FER);
1751         D16(PORTH_DRIVE);
1752         D16(PORTH_HYSTERESIS);
1753         D16(PORTH_MUX);
1754
1755         D16(MISCPORT_DRIVE);
1756         D16(MISCPORT_HYSTERESIS);
1757 #endif  /* BF51x */
1758
1759 #ifdef __ADSPBF52x__
1760         D16(PORTF_FER);
1761         D16(PORTF_DRIVE);
1762         D16(PORTF_HYSTERESIS);
1763         D16(PORTF_MUX);
1764         D16(PORTF_SLEW);
1765
1766         D16(PORTG_FER);
1767         D16(PORTG_DRIVE);
1768         D16(PORTG_HYSTERESIS);
1769         D16(PORTG_MUX);
1770         D16(PORTG_SLEW);
1771
1772         D16(PORTH_FER);
1773         D16(PORTH_DRIVE);
1774         D16(PORTH_HYSTERESIS);
1775         D16(PORTH_MUX);
1776         D16(PORTH_SLEW);
1777
1778         D16(MISCPORT_DRIVE);
1779         D16(MISCPORT_HYSTERESIS);
1780         D16(MISCPORT_SLEW);
1781 #endif  /* BF52x */
1782
1783 #ifdef BF537_FAMILY
1784         D16(PORTF_FER);
1785         D16(PORTG_FER);
1786         D16(PORTH_FER);
1787         D16(PORT_MUX);
1788 #endif  /* BF534 BF536 BF537 */
1789
1790 #ifdef BF538_FAMILY
1791         D16(PORTCIO_FER);
1792         D16(PORTCIO);
1793         D16(PORTCIO_CLEAR);
1794         D16(PORTCIO_SET);
1795         D16(PORTCIO_TOGGLE);
1796         D16(PORTCIO_DIR);
1797         D16(PORTCIO_INEN);
1798
1799         D16(PORTDIO);
1800         D16(PORTDIO_CLEAR);
1801         D16(PORTDIO_DIR);
1802         D16(PORTDIO_FER);
1803         D16(PORTDIO_INEN);
1804         D16(PORTDIO_SET);
1805         D16(PORTDIO_TOGGLE);
1806
1807         D16(PORTEIO);
1808         D16(PORTEIO_CLEAR);
1809         D16(PORTEIO_DIR);
1810         D16(PORTEIO_FER);
1811         D16(PORTEIO_INEN);
1812         D16(PORTEIO_SET);
1813         D16(PORTEIO_TOGGLE);
1814 #endif  /* BF538 BF539 */
1815
1816 #ifdef __ADSPBF54x__
1817         {
1818                 int num;
1819                 unsigned long base;
1820                 char *_buf, buf[32];
1821
1822                 base = PORTA_FER;
1823                 for (num = 0; num < 10; ++num) {
1824                         PORT(base, num);
1825                         base += sizeof(struct bfin_gpio_regs);
1826                 }
1827
1828 #define __PINT(uname, lname) __REGS(pint, #uname, lname)
1829                 parent = debugfs_create_dir("pint", top);
1830                 base = PINT0_MASK_SET;
1831                 for (num = 0; num < 4; ++num) {
1832                         _buf = REGS_STR_PFX(buf, PINT, num);
1833                         __PINT(MASK_SET, mask_set);
1834                         __PINT(MASK_CLEAR, mask_clear);
1835                         __PINT(IRQ, irq);
1836                         __PINT(ASSIGN, assign);
1837                         __PINT(EDGE_SET, edge_set);
1838                         __PINT(EDGE_CLEAR, edge_clear);
1839                         __PINT(INVERT_SET, invert_set);
1840                         __PINT(INVERT_CLEAR, invert_clear);
1841                         __PINT(PINSTATE, pinstate);
1842                         __PINT(LATCH, latch);
1843                         base += sizeof(struct bfin_pint_regs);
1844                 }
1845
1846         }
1847 #endif  /* BF54x */
1848
1849         debug_mmrs_dentry = top;
1850
1851         return 0;
1852 }
1853 module_init(bfin_debug_mmrs_init);
1854
1855 static void __exit bfin_debug_mmrs_exit(void)
1856 {
1857         debugfs_remove_recursive(debug_mmrs_dentry);
1858 }
1859 module_exit(bfin_debug_mmrs_exit);
1860
1861 MODULE_LICENSE("GPL");