arch/blackfin/kernel/debug-mmrs.c

   1 /*
   2  * debugfs interface to core/system MMRs
   3  *
   4  * Copyright 2007-2011 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later
   7  */
   8
   9 #include <linux/debugfs.h>
  10 #include <linux/fs.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13
  14 #include <asm/blackfin.h>
  15 #include <asm/gpio.h>
  16 #include <asm/gptimers.h>
  17 #include <asm/bfin_can.h>
  18 #include <asm/bfin_dma.h>
  19 #include <asm/bfin_ppi.h>
  20 #include <asm/bfin_serial.h>
  21 #include <asm/bfin5xx_spi.h>
  22 #include <asm/bfin_twi.h>
  23
  24 /* Common code defines PORT_MUX on us, so redirect the MMR back locally */
  25 #ifdef BFIN_PORT_MUX
  26 #undef PORT_MUX
  27 #define PORT_MUX BFIN_PORT_MUX
  28 #endif
  29
  30 #define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr))
  31 #define d(name, bits, addr)         _d(name, bits, addr, S_IRUSR|S_IWUSR)
  32 #define d_RO(name, bits, addr)      _d(name, bits, addr, S_IRUSR)
  33 #define d_WO(name, bits, addr)      _d(name, bits, addr, S_IWUSR)
  34
  35 #define D_RO(name, bits) d_RO(#name, bits, name)
  36 #define D_WO(name, bits) d_WO(#name, bits, name)
  37 #define D32(name)        d(#name, 32, name)
  38 #define D16(name)        d(#name, 16, name)
  39
  40 #define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
  41 #define __REGS(peri, sname, rname) \
  42         do { \
  43                 struct bfin_##peri##_regs r; \
  44                 void *addr = (void *)(base + REGS_OFF(peri, rname)); \
  45                 strcpy(_buf, sname); \
  46                 if (sizeof(r.rname) == 2) \
  47                         debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
  48                 else \
  49                         debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
  50         } while (0)
  51 #define REGS_STR_PFX(buf, pfx, num) \
  52         ({ \
  53                 buf + (num >= 0 ? \
  54                         sprintf(buf, #pfx "%i_", num) : \
  55                         sprintf(buf, #pfx "_")); \
  56         })
  57 #define REGS_STR_PFX_C(buf, pfx, num) \
  58         ({ \
  59                 buf + (num >= 0 ? \
  60                         sprintf(buf, #pfx "%c_", 'A' + num) : \
  61                         sprintf(buf, #pfx "_")); \
  62         })
  63
  64 /*
  65  * Core registers (not memory mapped)
  66  */
  67 extern u32 last_seqstat;
  68
  69 static int debug_cclk_get(void *data, u64 *val)
  70 {
  71         *val = get_cclk();
  72         return 0;
  73 }
  74 DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
  75
  76 static int debug_sclk_get(void *data, u64 *val)
  77 {
  78         *val = get_sclk();
  79         return 0;
  80 }
  81 DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
  82
  83 #define DEFINE_SYSREG(sr, pre, post) \
  84 static int sysreg_##sr##_get(void *data, u64 *val) \
  85 { \
  86         unsigned long tmp; \
  87         pre; \
  88         __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
  89         *val = tmp; \
  90         return 0; \
  91 } \
  92 static int sysreg_##sr##_set(void *data, u64 val) \
  93 { \
  94         unsigned long tmp = val; \
  95         __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
  96         post; \
  97         return 0; \
  98 } \
  99 DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
 100
 101 DEFINE_SYSREG(cycles, , );
 102 DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
 103 DEFINE_SYSREG(emudat, , );
 104 DEFINE_SYSREG(seqstat, , );
 105 DEFINE_SYSREG(syscfg, , CSYNC());
 106 #define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
 107
 108 /*
 109  * CAN
 110  */
 111 #define CAN_OFF(mmr)  REGS_OFF(can, mmr)
 112 #define __CAN(uname, lname) __REGS(can, #uname, lname)
 113 static void __init __maybe_unused
 114 bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
 115 {
 116         static struct dentry *am, *mb;
 117         int i, j;
 118         char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
 119
 120         if (!am) {
 121                 am = debugfs_create_dir("am", parent);
 122                 mb = debugfs_create_dir("mb", parent);
 123         }
 124
 125         __CAN(MC1, mc1);
 126         __CAN(MD1, md1);
 127         __CAN(TRS1, trs1);
 128         __CAN(TRR1, trr1);
 129         __CAN(TA1, ta1);
 130         __CAN(AA1, aa1);
 131         __CAN(RMP1, rmp1);
 132         __CAN(RML1, rml1);
 133         __CAN(MBTIF1, mbtif1);
 134         __CAN(MBRIF1, mbrif1);
 135         __CAN(MBIM1, mbim1);
 136         __CAN(RFH1, rfh1);
 137         __CAN(OPSS1, opss1);
 138
 139         __CAN(MC2, mc2);
 140         __CAN(MD2, md2);
 141         __CAN(TRS2, trs2);
 142         __CAN(TRR2, trr2);
 143         __CAN(TA2, ta2);
 144         __CAN(AA2, aa2);
 145         __CAN(RMP2, rmp2);
 146         __CAN(RML2, rml2);
 147         __CAN(MBTIF2, mbtif2);
 148         __CAN(MBRIF2, mbrif2);
 149         __CAN(MBIM2, mbim2);
 150         __CAN(RFH2, rfh2);
 151         __CAN(OPSS2, opss2);
 152
 153         __CAN(CLOCK, clock);
 154         __CAN(TIMING, timing);
 155         __CAN(DEBUG, debug);
 156         __CAN(STATUS, status);
 157         __CAN(CEC, cec);
 158         __CAN(GIS, gis);
 159         __CAN(GIM, gim);
 160         __CAN(GIF, gif);
 161         __CAN(CONTROL, control);
 162         __CAN(INTR, intr);
 163         __CAN(VERSION, version);
 164         __CAN(MBTD, mbtd);
 165         __CAN(EWR, ewr);
 166         __CAN(ESR, esr);
 167         /*__CAN(UCREG, ucreg); no longer exists */
 168         __CAN(UCCNT, uccnt);
 169         __CAN(UCRC, ucrc);
 170         __CAN(UCCNF, uccnf);
 171         __CAN(VERSION2, version2);
 172
 173         for (i = 0; i < 32; ++i) {
 174                 sprintf(_buf, "AM%02iL", i);
 175                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
 176                         (u16 *)(base + CAN_OFF(msk[i].aml)));
 177                 sprintf(_buf, "AM%02iH", i);
 178                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
 179                         (u16 *)(base + CAN_OFF(msk[i].amh)));
 180
 181                 for (j = 0; j < 3; ++j) {
 182                         sprintf(_buf, "MB%02i_DATA%i", i, j);
 183                         debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 184                                 (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
 185                 }
 186                 sprintf(_buf, "MB%02i_LENGTH", i);
 187                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 188                         (u16 *)(base + CAN_OFF(chl[i].dlc)));
 189                 sprintf(_buf, "MB%02i_TIMESTAMP", i);
 190                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 191                         (u16 *)(base + CAN_OFF(chl[i].tsv)));
 192                 sprintf(_buf, "MB%02i_ID0", i);
 193                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 194                         (u16 *)(base + CAN_OFF(chl[i].id0)));
 195                 sprintf(_buf, "MB%02i_ID1", i);
 196                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 197                         (u16 *)(base + CAN_OFF(chl[i].id1)));
 198         }
 199 }
 200 #define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
 201
 202 /*
 203  * DMA
 204  */
 205 #define __DMA(uname, lname) __REGS(dma, #uname, lname)
 206 static void __init __maybe_unused
 207 bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
 208 {
 209         char buf[32], *_buf;
 210
 211         if (mdma)
 212                 _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
 213         else
 214                 _buf = buf + sprintf(buf, "%s%i_", pfx, num);
 215
 216         __DMA(NEXT_DESC_PTR, next_desc_ptr);
 217         __DMA(START_ADDR, start_addr);
 218         __DMA(CONFIG, config);
 219         __DMA(X_COUNT, x_count);
 220         __DMA(X_MODIFY, x_modify);
 221         __DMA(Y_COUNT, y_count);
 222         __DMA(Y_MODIFY, y_modify);
 223         __DMA(CURR_DESC_PTR, curr_desc_ptr);
 224         __DMA(CURR_ADDR, curr_addr);
 225         __DMA(IRQ_STATUS, irq_status);
 226         if (strcmp(pfx, "IMDMA") != 0)
 227                 __DMA(PERIPHERAL_MAP, peripheral_map);
 228         __DMA(CURR_X_COUNT, curr_x_count);
 229         __DMA(CURR_Y_COUNT, curr_y_count);
 230 }
 231 #define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
 232 #define DMA(num)  _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
 233 #define _MDMA(num, x) \
 234         do { \
 235                 _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
 236                 _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
 237         } while (0)
 238 #define MDMA(num) _MDMA(num, M)
 239 #define IMDMA(num) _MDMA(num, IM)
 240
 241 /*
 242  * EPPI
 243  */
 244 #define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
 245 static void __init __maybe_unused
 246 bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
 247 {
 248         char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
 249         __EPPI(STATUS, status);
 250         __EPPI(HCOUNT, hcount);
 251         __EPPI(HDELAY, hdelay);
 252         __EPPI(VCOUNT, vcount);
 253         __EPPI(VDELAY, vdelay);
 254         __EPPI(FRAME, frame);
 255         __EPPI(LINE, line);
 256         __EPPI(CLKDIV, clkdiv);
 257         __EPPI(CONTROL, control);
 258         __EPPI(FS1W_HBL, fs1w_hbl);
 259         __EPPI(FS1P_AVPL, fs1p_avpl);
 260         __EPPI(FS2W_LVB, fs2w_lvb);
 261         __EPPI(FS2P_LAVF, fs2p_lavf);
 262         __EPPI(CLIP, clip);
 263 }
 264 #define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
 265
 266 /*
 267  * General Purpose Timers
 268  */
 269 #define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
 270 static void __init __maybe_unused
 271 bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
 272 {
 273         char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
 274         __GPTIMER(CONFIG, config);
 275         __GPTIMER(COUNTER, counter);
 276         __GPTIMER(PERIOD, period);
 277         __GPTIMER(WIDTH, width);
 278 }
 279 #define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
 280
 281 #define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr)
 282 #define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname)
 283 static void __init __maybe_unused
 284 bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num)
 285 {
 286         char buf[32], *_buf;
 287
 288         if (num == -1) {
 289                 _buf = buf + sprintf(buf, "TIMER_");
 290                 __GPTIMER_GROUP(ENABLE, enable);
 291                 __GPTIMER_GROUP(DISABLE, disable);
 292                 __GPTIMER_GROUP(STATUS, status);
 293         } else {
 294                 /* These MMRs are a bit odd as the group # is a suffix */
 295                 _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num);
 296                 d(buf, 16, base + GPTIMER_GROUP_OFF(enable));
 297
 298                 _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num);
 299                 d(buf, 16, base + GPTIMER_GROUP_OFF(disable));
 300
 301                 _buf = buf + sprintf(buf, "TIMER_STATUS%i", num);
 302                 d(buf, 32, base + GPTIMER_GROUP_OFF(status));
 303         }
 304 }
 305 #define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num)
 306
 307 /*
 308  * Handshake MDMA
 309  */
 310 #define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
 311 static void __init __maybe_unused
 312 bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
 313 {
 314         char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
 315         __HMDMA(CONTROL, control);
 316         __HMDMA(ECINIT, ecinit);
 317         __HMDMA(BCINIT, bcinit);
 318         __HMDMA(ECURGENT, ecurgent);
 319         __HMDMA(ECOVERFLOW, ecoverflow);
 320         __HMDMA(ECOUNT, ecount);
 321         __HMDMA(BCOUNT, bcount);
 322 }
 323 #define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
 324
 325 /*
 326  * Port/GPIO
 327  */
 328 #define bfin_gpio_regs gpio_port_t
 329 #define __PORT(uname, lname) __REGS(gpio, #uname, lname)
 330 static void __init __maybe_unused
 331 bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
 332 {
 333         char buf[32], *_buf;
 334 #ifdef __ADSPBF54x__
 335         _buf = REGS_STR_PFX_C(buf, PORT, num);
 336         __PORT(FER, port_fer);
 337         __PORT(SET, data_set);
 338         __PORT(CLEAR, data_clear);
 339         __PORT(DIR_SET, dir_set);
 340         __PORT(DIR_CLEAR, dir_clear);
 341         __PORT(INEN, inen);
 342         __PORT(MUX, port_mux);
 343 #else
 344         _buf = buf + sprintf(buf, "PORT%cIO_", num);
 345         __PORT(CLEAR, data_clear);
 346         __PORT(SET, data_set);
 347         __PORT(TOGGLE, toggle);
 348         __PORT(MASKA, maska);
 349         __PORT(MASKA_CLEAR, maska_clear);
 350         __PORT(MASKA_SET, maska_set);
 351         __PORT(MASKA_TOGGLE, maska_toggle);
 352         __PORT(MASKB, maskb);
 353         __PORT(MASKB_CLEAR, maskb_clear);
 354         __PORT(MASKB_SET, maskb_set);
 355         __PORT(MASKB_TOGGLE, maskb_toggle);
 356         __PORT(DIR, dir);
 357         __PORT(POLAR, polar);
 358         __PORT(EDGE, edge);
 359         __PORT(BOTH, both);
 360         __PORT(INEN, inen);
 361 #endif
 362         _buf[-1] = '\0';
 363         d(buf, 16, base + REGS_OFF(gpio, data));
 364 }
 365 #define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
 366
 367 /*
 368  * PPI
 369  */
 370 #define __PPI(uname, lname) __REGS(ppi, #uname, lname)
 371 static void __init __maybe_unused
 372 bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
 373 {
 374         char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
 375         __PPI(CONTROL, control);
 376         __PPI(STATUS, status);
 377         __PPI(COUNT, count);
 378         __PPI(DELAY, delay);
 379         __PPI(FRAME, frame);
 380 }
 381 #define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
 382
 383 /*
 384  * SPI
 385  */
 386 #define __SPI(uname, lname) __REGS(spi, #uname, lname)
 387 static void __init __maybe_unused
 388 bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
 389 {
 390         char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
 391         __SPI(CTL, ctl);
 392         __SPI(FLG, flg);
 393         __SPI(STAT, stat);
 394         __SPI(TDBR, tdbr);
 395         __SPI(RDBR, rdbr);
 396         __SPI(BAUD, baud);
 397         __SPI(SHADOW, shadow);
 398 }
 399 #define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
 400
 401 /*
 402  * SPORT
 403  */
 404 static inline int sport_width(void *mmr)
 405 {
 406         unsigned long lmmr = (unsigned long)mmr;
 407         if ((lmmr & 0xff) == 0x10)
 408                 /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
 409                 lmmr -= 0xc;
 410         else
 411                 /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
 412                 lmmr += 0xc;
 413         /* extract SLEN field from control register 2 and add 1 */
 414         return (bfin_read16(lmmr) & 0x1f) + 1;
 415 }
 416 static int sport_set(void *mmr, u64 val)
 417 {
 418         unsigned long flags;
 419         local_irq_save(flags);
 420         if (sport_width(mmr) <= 16)
 421                 bfin_write16(mmr, val);
 422         else
 423                 bfin_write32(mmr, val);
 424         local_irq_restore(flags);
 425         return 0;
 426 }
 427 static int sport_get(void *mmr, u64 *val)
 428 {
 429         unsigned long flags;
 430         local_irq_save(flags);
 431         if (sport_width(mmr) <= 16)
 432                 *val = bfin_read16(mmr);
 433         else
 434                 *val = bfin_read32(mmr);
 435         local_irq_restore(flags);
 436         return 0;
 437 }
 438 DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
 439 /*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
 440 DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
 441 #define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
 442 #define _D_SPORT(name, perms, fops) \
 443         do { \
 444                 strcpy(_buf, #name); \
 445                 debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
 446         } while (0)
 447 #define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
 448 #define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
 449 #define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
 450 #define __SPORT(name, bits) \
 451         do { \
 452                 strcpy(_buf, #name); \
 453                 debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
 454         } while (0)
 455 static void __init __maybe_unused
 456 bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
 457 {
 458         char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
 459         __SPORT(CHNL, 16);
 460         __SPORT(MCMC1, 16);
 461         __SPORT(MCMC2, 16);
 462         __SPORT(MRCS0, 32);
 463         __SPORT(MRCS1, 32);
 464         __SPORT(MRCS2, 32);
 465         __SPORT(MRCS3, 32);
 466         __SPORT(MTCS0, 32);
 467         __SPORT(MTCS1, 32);
 468         __SPORT(MTCS2, 32);
 469         __SPORT(MTCS3, 32);
 470         __SPORT(RCLKDIV, 16);
 471         __SPORT(RCR1, 16);
 472         __SPORT(RCR2, 16);
 473         __SPORT(RFSDIV, 16);
 474         __SPORT_RW(RX);
 475         __SPORT(STAT, 16);
 476         __SPORT(TCLKDIV, 16);
 477         __SPORT(TCR1, 16);
 478         __SPORT(TCR2, 16);
 479         __SPORT(TFSDIV, 16);
 480         __SPORT_WO(TX);
 481 }
 482 #define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
 483
 484 /*
 485  * TWI
 486  */
 487 #define __TWI(uname, lname) __REGS(twi, #uname, lname)
 488 static void __init __maybe_unused
 489 bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
 490 {
 491         char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
 492         __TWI(CLKDIV, clkdiv);
 493         __TWI(CONTROL, control);
 494         __TWI(SLAVE_CTL, slave_ctl);
 495         __TWI(SLAVE_STAT, slave_stat);
 496         __TWI(SLAVE_ADDR, slave_addr);
 497         __TWI(MASTER_CTL, master_ctl);
 498         __TWI(MASTER_STAT, master_stat);
 499         __TWI(MASTER_ADDR, master_addr);
 500         __TWI(INT_STAT, int_stat);
 501         __TWI(INT_MASK, int_mask);
 502         __TWI(FIFO_CTL, fifo_ctl);
 503         __TWI(FIFO_STAT, fifo_stat);
 504         __TWI(XMT_DATA8, xmt_data8);
 505         __TWI(XMT_DATA16, xmt_data16);
 506         __TWI(RCV_DATA8, rcv_data8);
 507         __TWI(RCV_DATA16, rcv_data16);
 508 }
 509 #define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
 510
 511 /*
 512  * UART
 513  */
 514 #define __UART(uname, lname) __REGS(uart, #uname, lname)
 515 static void __init __maybe_unused
 516 bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
 517 {
 518         char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
 519 #ifdef BFIN_UART_BF54X_STYLE
 520         __UART(DLL, dll);
 521         __UART(DLH, dlh);
 522         __UART(GCTL, gctl);
 523         __UART(LCR, lcr);
 524         __UART(MCR, mcr);
 525         __UART(LSR, lsr);
 526         __UART(MSR, msr);
 527         __UART(SCR, scr);
 528         __UART(IER_SET, ier_set);
 529         __UART(IER_CLEAR, ier_clear);
 530         __UART(THR, thr);
 531         __UART(RBR, rbr);
 532 #else
 533         __UART(DLL, dll);
 534         __UART(THR, thr);
 535         __UART(RBR, rbr);
 536         __UART(DLH, dlh);
 537         __UART(IER, ier);
 538         __UART(IIR, iir);
 539         __UART(LCR, lcr);
 540         __UART(MCR, mcr);
 541         __UART(LSR, lsr);
 542         __UART(MSR, msr);
 543         __UART(SCR, scr);
 544         __UART(GCTL, gctl);
 545 #endif
 546 }
 547 #define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
 548
 549 /*
 550  * The actual debugfs generation
 551  */
 552 static struct dentry *debug_mmrs_dentry;
 553
 554 static int __init bfin_debug_mmrs_init(void)
 555 {
 556         struct dentry *top, *parent;
 557
 558         pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
 559
 560         top = debugfs_create_dir("blackfin", NULL);
 561         if (top == NULL)
 562                 return -1;
 563
 564         parent = debugfs_create_dir("core_regs", top);
 565         debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
 566         debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
 567         debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
 568         D_SYSREG(cycles);
 569         D_SYSREG(cycles2);
 570         D_SYSREG(emudat);
 571         D_SYSREG(seqstat);
 572         D_SYSREG(syscfg);
 573
 574         /* Core MMRs */
 575         parent = debugfs_create_dir("ctimer", top);
 576         D32(TCNTL);
 577         D32(TCOUNT);
 578         D32(TPERIOD);
 579         D32(TSCALE);
 580
 581         parent = debugfs_create_dir("cec", top);
 582         D32(EVT0);
 583         D32(EVT1);
 584         D32(EVT2);
 585         D32(EVT3);
 586         D32(EVT4);
 587         D32(EVT5);
 588         D32(EVT6);
 589         D32(EVT7);
 590         D32(EVT8);
 591         D32(EVT9);
 592         D32(EVT10);
 593         D32(EVT11);
 594         D32(EVT12);
 595         D32(EVT13);
 596         D32(EVT14);
 597         D32(EVT15);
 598         D32(EVT_OVERRIDE);
 599         D32(IMASK);
 600         D32(IPEND);
 601         D32(ILAT);
 602         D32(IPRIO);
 603
 604         parent = debugfs_create_dir("debug", top);
 605         D32(DBGSTAT);
 606         D32(DSPID);
 607
 608         parent = debugfs_create_dir("mmu", top);
 609         D32(SRAM_BASE_ADDRESS);
 610         D32(DCPLB_ADDR0);
 611         D32(DCPLB_ADDR10);
 612         D32(DCPLB_ADDR11);
 613         D32(DCPLB_ADDR12);
 614         D32(DCPLB_ADDR13);
 615         D32(DCPLB_ADDR14);
 616         D32(DCPLB_ADDR15);
 617         D32(DCPLB_ADDR1);
 618         D32(DCPLB_ADDR2);
 619         D32(DCPLB_ADDR3);
 620         D32(DCPLB_ADDR4);
 621         D32(DCPLB_ADDR5);
 622         D32(DCPLB_ADDR6);
 623         D32(DCPLB_ADDR7);
 624         D32(DCPLB_ADDR8);
 625         D32(DCPLB_ADDR9);
 626         D32(DCPLB_DATA0);
 627         D32(DCPLB_DATA10);
 628         D32(DCPLB_DATA11);
 629         D32(DCPLB_DATA12);
 630         D32(DCPLB_DATA13);
 631         D32(DCPLB_DATA14);
 632         D32(DCPLB_DATA15);
 633         D32(DCPLB_DATA1);
 634         D32(DCPLB_DATA2);
 635         D32(DCPLB_DATA3);
 636         D32(DCPLB_DATA4);
 637         D32(DCPLB_DATA5);
 638         D32(DCPLB_DATA6);
 639         D32(DCPLB_DATA7);
 640         D32(DCPLB_DATA8);
 641         D32(DCPLB_DATA9);
 642         D32(DCPLB_FAULT_ADDR);
 643         D32(DCPLB_STATUS);
 644         D32(DMEM_CONTROL);
 645         D32(DTEST_COMMAND);
 646         D32(DTEST_DATA0);
 647         D32(DTEST_DATA1);
 648
 649         D32(ICPLB_ADDR0);
 650         D32(ICPLB_ADDR1);
 651         D32(ICPLB_ADDR2);
 652         D32(ICPLB_ADDR3);
 653         D32(ICPLB_ADDR4);
 654         D32(ICPLB_ADDR5);
 655         D32(ICPLB_ADDR6);
 656         D32(ICPLB_ADDR7);
 657         D32(ICPLB_ADDR8);
 658         D32(ICPLB_ADDR9);
 659         D32(ICPLB_ADDR10);
 660         D32(ICPLB_ADDR11);
 661         D32(ICPLB_ADDR12);
 662         D32(ICPLB_ADDR13);
 663         D32(ICPLB_ADDR14);
 664         D32(ICPLB_ADDR15);
 665         D32(ICPLB_DATA0);
 666         D32(ICPLB_DATA1);
 667         D32(ICPLB_DATA2);
 668         D32(ICPLB_DATA3);
 669         D32(ICPLB_DATA4);
 670         D32(ICPLB_DATA5);
 671         D32(ICPLB_DATA6);
 672         D32(ICPLB_DATA7);
 673         D32(ICPLB_DATA8);
 674         D32(ICPLB_DATA9);
 675         D32(ICPLB_DATA10);
 676         D32(ICPLB_DATA11);
 677         D32(ICPLB_DATA12);
 678         D32(ICPLB_DATA13);
 679         D32(ICPLB_DATA14);
 680         D32(ICPLB_DATA15);
 681         D32(ICPLB_FAULT_ADDR);
 682         D32(ICPLB_STATUS);
 683         D32(IMEM_CONTROL);
 684         if (!ANOMALY_05000481) {
 685                 D32(ITEST_COMMAND);
 686                 D32(ITEST_DATA0);
 687                 D32(ITEST_DATA1);
 688         }
 689
 690         parent = debugfs_create_dir("perf", top);
 691         D32(PFCNTR0);
 692         D32(PFCNTR1);
 693         D32(PFCTL);
 694
 695         parent = debugfs_create_dir("trace", top);
 696         D32(TBUF);
 697         D32(TBUFCTL);
 698         D32(TBUFSTAT);
 699
 700         parent = debugfs_create_dir("watchpoint", top);
 701         D32(WPIACTL);
 702         D32(WPIA0);
 703         D32(WPIA1);
 704         D32(WPIA2);
 705         D32(WPIA3);
 706         D32(WPIA4);
 707         D32(WPIA5);
 708         D32(WPIACNT0);
 709         D32(WPIACNT1);
 710         D32(WPIACNT2);
 711         D32(WPIACNT3);
 712         D32(WPIACNT4);
 713         D32(WPIACNT5);
 714         D32(WPDACTL);
 715         D32(WPDA0);
 716         D32(WPDA1);
 717         D32(WPDACNT0);
 718         D32(WPDACNT1);
 719         D32(WPSTAT);
 720
 721         /* System MMRs */
 722 #ifdef ATAPI_CONTROL
 723         parent = debugfs_create_dir("atapi", top);
 724         D16(ATAPI_CONTROL);
 725         D16(ATAPI_DEV_ADDR);
 726         D16(ATAPI_DEV_RXBUF);
 727         D16(ATAPI_DEV_TXBUF);
 728         D16(ATAPI_DMA_TFRCNT);
 729         D16(ATAPI_INT_MASK);
 730         D16(ATAPI_INT_STATUS);
 731         D16(ATAPI_LINE_STATUS);
 732         D16(ATAPI_MULTI_TIM_0);
 733         D16(ATAPI_MULTI_TIM_1);
 734         D16(ATAPI_MULTI_TIM_2);
 735         D16(ATAPI_PIO_TFRCNT);
 736         D16(ATAPI_PIO_TIM_0);
 737         D16(ATAPI_PIO_TIM_1);
 738         D16(ATAPI_REG_TIM_0);
 739         D16(ATAPI_SM_STATE);
 740         D16(ATAPI_STATUS);
 741         D16(ATAPI_TERMINATE);
 742         D16(ATAPI_UDMAOUT_TFRCNT);
 743         D16(ATAPI_ULTRA_TIM_0);
 744         D16(ATAPI_ULTRA_TIM_1);
 745         D16(ATAPI_ULTRA_TIM_2);
 746         D16(ATAPI_ULTRA_TIM_3);
 747         D16(ATAPI_UMAIN_TFRCNT);
 748         D16(ATAPI_XFER_LEN);
 749 #endif
 750
 751 #if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
 752         parent = debugfs_create_dir("can", top);
 753 # ifdef CAN_MC1
 754         bfin_debug_mmrs_can(parent, CAN_MC1, -1);
 755 # endif
 756 # ifdef CAN0_MC1
 757         CAN(0);
 758 # endif
 759 # ifdef CAN1_MC1
 760         CAN(1);
 761 # endif
 762 #endif
 763
 764 #ifdef CNT_COMMAND
 765         parent = debugfs_create_dir("counter", top);
 766         D16(CNT_COMMAND);
 767         D16(CNT_CONFIG);
 768         D32(CNT_COUNTER);
 769         D16(CNT_DEBOUNCE);
 770         D16(CNT_IMASK);
 771         D32(CNT_MAX);
 772         D32(CNT_MIN);
 773         D16(CNT_STATUS);
 774 #endif
 775
 776         parent = debugfs_create_dir("dmac", top);
 777 #ifdef DMAC_TC_CNT
 778         D16(DMAC_TC_CNT);
 779         D16(DMAC_TC_PER);
 780 #endif
 781 #ifdef DMAC0_TC_CNT
 782         D16(DMAC0_TC_CNT);
 783         D16(DMAC0_TC_PER);
 784 #endif
 785 #ifdef DMAC1_TC_CNT
 786         D16(DMAC1_TC_CNT);
 787         D16(DMAC1_TC_PER);
 788 #endif
 789 #ifdef DMAC1_PERIMUX
 790         D16(DMAC1_PERIMUX);
 791 #endif
 792
 793 #ifdef __ADSPBF561__
 794         /* XXX: should rewrite the MMR map */
 795 # define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
 796 # define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
 797 # define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
 798 # define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
 799 # define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
 800 # define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
 801 # define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
 802 # define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
 803 # define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
 804 # define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
 805 # define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
 806 # define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
 807 # define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
 808 # define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
 809 # define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
 810 # define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
 811 # define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
 812 # define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
 813 # define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
 814 # define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
 815 # define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
 816 # define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
 817 # define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
 818 # define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
 819 #endif
 820         parent = debugfs_create_dir("dma", top);
 821         DMA(0);
 822         DMA(1);
 823         DMA(1);
 824         DMA(2);
 825         DMA(3);
 826         DMA(4);
 827         DMA(5);
 828         DMA(6);
 829         DMA(7);
 830 #ifdef DMA8_NEXT_DESC_PTR
 831         DMA(8);
 832         DMA(9);
 833         DMA(10);
 834         DMA(11);
 835 #endif
 836 #ifdef DMA12_NEXT_DESC_PTR
 837         DMA(12);
 838         DMA(13);
 839         DMA(14);
 840         DMA(15);
 841         DMA(16);
 842         DMA(17);
 843         DMA(18);
 844         DMA(19);
 845 #endif
 846 #ifdef DMA20_NEXT_DESC_PTR
 847         DMA(20);
 848         DMA(21);
 849         DMA(22);
 850         DMA(23);
 851 #endif
 852
 853         parent = debugfs_create_dir("ebiu_amc", top);
 854         D32(EBIU_AMBCTL0);
 855         D32(EBIU_AMBCTL1);
 856         D16(EBIU_AMGCTL);
 857 #ifdef EBIU_MBSCTL
 858         D16(EBIU_MBSCTL);
 859         D32(EBIU_ARBSTAT);
 860         D32(EBIU_MODE);
 861         D16(EBIU_FCTL);
 862 #endif
 863
 864 #ifdef EBIU_SDGCTL
 865         parent = debugfs_create_dir("ebiu_sdram", top);
 866 # ifdef __ADSPBF561__
 867         D32(EBIU_SDBCTL);
 868 # else
 869         D16(EBIU_SDBCTL);
 870 # endif
 871         D32(EBIU_SDGCTL);
 872         D16(EBIU_SDRRC);
 873         D16(EBIU_SDSTAT);
 874 #endif
 875
 876 #ifdef EBIU_DDRACCT
 877         parent = debugfs_create_dir("ebiu_ddr", top);
 878         D32(EBIU_DDRACCT);
 879         D32(EBIU_DDRARCT);
 880         D32(EBIU_DDRBRC0);
 881         D32(EBIU_DDRBRC1);
 882         D32(EBIU_DDRBRC2);
 883         D32(EBIU_DDRBRC3);
 884         D32(EBIU_DDRBRC4);
 885         D32(EBIU_DDRBRC5);
 886         D32(EBIU_DDRBRC6);
 887         D32(EBIU_DDRBRC7);
 888         D32(EBIU_DDRBWC0);
 889         D32(EBIU_DDRBWC1);
 890         D32(EBIU_DDRBWC2);
 891         D32(EBIU_DDRBWC3);
 892         D32(EBIU_DDRBWC4);
 893         D32(EBIU_DDRBWC5);
 894         D32(EBIU_DDRBWC6);
 895         D32(EBIU_DDRBWC7);
 896         D32(EBIU_DDRCTL0);
 897         D32(EBIU_DDRCTL1);
 898         D32(EBIU_DDRCTL2);
 899         D32(EBIU_DDRCTL3);
 900         D32(EBIU_DDRGC0);
 901         D32(EBIU_DDRGC1);
 902         D32(EBIU_DDRGC2);
 903         D32(EBIU_DDRGC3);
 904         D32(EBIU_DDRMCCL);
 905         D32(EBIU_DDRMCEN);
 906         D32(EBIU_DDRQUE);
 907         D32(EBIU_DDRTACT);
 908         D32(EBIU_ERRADD);
 909         D16(EBIU_ERRMST);
 910         D16(EBIU_RSTCTL);
 911 #endif
 912
 913 #ifdef EMAC_ADDRHI
 914         parent = debugfs_create_dir("emac", top);
 915         D32(EMAC_ADDRHI);
 916         D32(EMAC_ADDRLO);
 917         D32(EMAC_FLC);
 918         D32(EMAC_HASHHI);
 919         D32(EMAC_HASHLO);
 920         D32(EMAC_MMC_CTL);
 921         D32(EMAC_MMC_RIRQE);
 922         D32(EMAC_MMC_RIRQS);
 923         D32(EMAC_MMC_TIRQE);
 924         D32(EMAC_MMC_TIRQS);
 925         D32(EMAC_OPMODE);
 926         D32(EMAC_RXC_ALIGN);
 927         D32(EMAC_RXC_ALLFRM);
 928         D32(EMAC_RXC_ALLOCT);
 929         D32(EMAC_RXC_BROAD);
 930         D32(EMAC_RXC_DMAOVF);
 931         D32(EMAC_RXC_EQ64);
 932         D32(EMAC_RXC_FCS);
 933         D32(EMAC_RXC_GE1024);
 934         D32(EMAC_RXC_LNERRI);
 935         D32(EMAC_RXC_LNERRO);
 936         D32(EMAC_RXC_LONG);
 937         D32(EMAC_RXC_LT1024);
 938         D32(EMAC_RXC_LT128);
 939         D32(EMAC_RXC_LT256);
 940         D32(EMAC_RXC_LT512);
 941         D32(EMAC_RXC_MACCTL);
 942         D32(EMAC_RXC_MULTI);
 943         D32(EMAC_RXC_OCTET);
 944         D32(EMAC_RXC_OK);
 945         D32(EMAC_RXC_OPCODE);
 946         D32(EMAC_RXC_PAUSE);
 947         D32(EMAC_RXC_SHORT);
 948         D32(EMAC_RXC_TYPED);
 949         D32(EMAC_RXC_UNICST);
 950         D32(EMAC_RX_IRQE);
 951         D32(EMAC_RX_STAT);
 952         D32(EMAC_RX_STKY);
 953         D32(EMAC_STAADD);
 954         D32(EMAC_STADAT);
 955         D32(EMAC_SYSCTL);
 956         D32(EMAC_SYSTAT);
 957         D32(EMAC_TXC_1COL);
 958         D32(EMAC_TXC_ABORT);
 959         D32(EMAC_TXC_ALLFRM);
 960         D32(EMAC_TXC_ALLOCT);
 961         D32(EMAC_TXC_BROAD);
 962         D32(EMAC_TXC_CRSERR);
 963         D32(EMAC_TXC_DEFER);
 964         D32(EMAC_TXC_DMAUND);
 965         D32(EMAC_TXC_EQ64);
 966         D32(EMAC_TXC_GE1024);
 967         D32(EMAC_TXC_GT1COL);
 968         D32(EMAC_TXC_LATECL);
 969         D32(EMAC_TXC_LT1024);
 970         D32(EMAC_TXC_LT128);
 971         D32(EMAC_TXC_LT256);
 972         D32(EMAC_TXC_LT512);
 973         D32(EMAC_TXC_MACCTL);
 974         D32(EMAC_TXC_MULTI);
 975         D32(EMAC_TXC_OCTET);
 976         D32(EMAC_TXC_OK);
 977         D32(EMAC_TXC_UNICST);
 978         D32(EMAC_TXC_XS_COL);
 979         D32(EMAC_TXC_XS_DFR);
 980         D32(EMAC_TX_IRQE);
 981         D32(EMAC_TX_STAT);
 982         D32(EMAC_TX_STKY);
 983         D32(EMAC_VLAN1);
 984         D32(EMAC_VLAN2);
 985         D32(EMAC_WKUP_CTL);
 986         D32(EMAC_WKUP_FFCMD);
 987         D32(EMAC_WKUP_FFCRC0);
 988         D32(EMAC_WKUP_FFCRC1);
 989         D32(EMAC_WKUP_FFMSK0);
 990         D32(EMAC_WKUP_FFMSK1);
 991         D32(EMAC_WKUP_FFMSK2);
 992         D32(EMAC_WKUP_FFMSK3);
 993         D32(EMAC_WKUP_FFOFF);
 994 # ifdef EMAC_PTP_ACCR
 995         D32(EMAC_PTP_ACCR);
 996         D32(EMAC_PTP_ADDEND);
 997         D32(EMAC_PTP_ALARMHI);
 998         D32(EMAC_PTP_ALARMLO);
 999         D16(EMAC_PTP_CTL);
1000         D32(EMAC_PTP_FOFF);
1001         D32(EMAC_PTP_FV1);
1002         D32(EMAC_PTP_FV2);
1003         D32(EMAC_PTP_FV3);
1004         D16(EMAC_PTP_ID_OFF);
1005         D32(EMAC_PTP_ID_SNAP);
1006         D16(EMAC_PTP_IE);
1007         D16(EMAC_PTP_ISTAT);
1008         D32(EMAC_PTP_OFFSET);
1009         D32(EMAC_PTP_PPS_PERIOD);
1010         D32(EMAC_PTP_PPS_STARTHI);
1011         D32(EMAC_PTP_PPS_STARTLO);
1012         D32(EMAC_PTP_RXSNAPHI);
1013         D32(EMAC_PTP_RXSNAPLO);
1014         D32(EMAC_PTP_TIMEHI);
1015         D32(EMAC_PTP_TIMELO);
1016         D32(EMAC_PTP_TXSNAPHI);
1017         D32(EMAC_PTP_TXSNAPLO);
1018 # endif
1019 #endif
1020
1021 #if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
1022         parent = debugfs_create_dir("eppi", top);
1023 # ifdef EPPI0_STATUS
1024         EPPI(0);
1025 # endif
1026 # ifdef EPPI1_STATUS
1027         EPPI(1);
1028 # endif
1029 # ifdef EPPI2_STATUS
1030         EPPI(2);
1031 # endif
1032 #endif
1033
1034         parent = debugfs_create_dir("gptimer", top);
1035 #ifdef TIMER_ENABLE
1036         GPTIMER_GROUP(TIMER_ENABLE, -1);
1037 #endif
1038 #ifdef TIMER_ENABLE0
1039         GPTIMER_GROUP(TIMER_ENABLE0, 0);
1040 #endif
1041 #ifdef TIMER_ENABLE1
1042         GPTIMER_GROUP(TIMER_ENABLE1, 1);
1043 #endif
1044         /* XXX: Should convert BF561 MMR names */
1045 #ifdef TMRS4_DISABLE
1046         GPTIMER_GROUP(TMRS4_ENABLE, 0);
1047         GPTIMER_GROUP(TMRS8_ENABLE, 1);
1048 #endif
1049         GPTIMER(0);
1050         GPTIMER(1);
1051         GPTIMER(2);
1052 #ifdef TIMER3_CONFIG
1053         GPTIMER(3);
1054         GPTIMER(4);
1055         GPTIMER(5);
1056         GPTIMER(6);
1057         GPTIMER(7);
1058 #endif
1059 #ifdef TIMER8_CONFIG
1060         GPTIMER(8);
1061         GPTIMER(9);
1062         GPTIMER(10);
1063 #endif
1064 #ifdef TIMER11_CONFIG
1065         GPTIMER(11);
1066 #endif
1067
1068 #ifdef HMDMA0_CONTROL
1069         parent = debugfs_create_dir("hmdma", top);
1070         HMDMA(0);
1071         HMDMA(1);
1072 #endif
1073
1074 #ifdef HOST_CONTROL
1075         parent = debugfs_create_dir("hostdp", top);
1076         D16(HOST_CONTROL);
1077         D16(HOST_STATUS);
1078         D16(HOST_TIMEOUT);
1079 #endif
1080
1081 #ifdef IMDMA_S0_CONFIG
1082         parent = debugfs_create_dir("imdma", top);
1083         IMDMA(0);
1084         IMDMA(1);
1085 #endif
1086
1087 #ifdef KPAD_CTL
1088         parent = debugfs_create_dir("keypad", top);
1089         D16(KPAD_CTL);
1090         D16(KPAD_PRESCALE);
1091         D16(KPAD_MSEL);
1092         D16(KPAD_ROWCOL);
1093         D16(KPAD_STAT);
1094         D16(KPAD_SOFTEVAL);
1095 #endif
1096
1097         parent = debugfs_create_dir("mdma", top);
1098         MDMA(0);
1099         MDMA(1);
1100 #ifdef MDMA_D2_CONFIG
1101         MDMA(2);
1102         MDMA(3);
1103 #endif
1104
1105 #ifdef MXVR_CONFIG
1106         parent = debugfs_create_dir("mxvr", top);
1107         D16(MXVR_CONFIG);
1108 # ifdef MXVR_PLL_CTL_0
1109         D32(MXVR_PLL_CTL_0);
1110 # endif
1111         D32(MXVR_STATE_0);
1112         D32(MXVR_STATE_1);
1113         D32(MXVR_INT_STAT_0);
1114         D32(MXVR_INT_STAT_1);
1115         D32(MXVR_INT_EN_0);
1116         D32(MXVR_INT_EN_1);
1117         D16(MXVR_POSITION);
1118         D16(MXVR_MAX_POSITION);
1119         D16(MXVR_DELAY);
1120         D16(MXVR_MAX_DELAY);
1121         D32(MXVR_LADDR);
1122         D16(MXVR_GADDR);
1123         D32(MXVR_AADDR);
1124         D32(MXVR_ALLOC_0);
1125         D32(MXVR_ALLOC_1);
1126         D32(MXVR_ALLOC_2);
1127         D32(MXVR_ALLOC_3);
1128         D32(MXVR_ALLOC_4);
1129         D32(MXVR_ALLOC_5);
1130         D32(MXVR_ALLOC_6);
1131         D32(MXVR_ALLOC_7);
1132         D32(MXVR_ALLOC_8);
1133         D32(MXVR_ALLOC_9);
1134         D32(MXVR_ALLOC_10);
1135         D32(MXVR_ALLOC_11);
1136         D32(MXVR_ALLOC_12);
1137         D32(MXVR_ALLOC_13);
1138         D32(MXVR_ALLOC_14);
1139         D32(MXVR_SYNC_LCHAN_0);
1140         D32(MXVR_SYNC_LCHAN_1);
1141         D32(MXVR_SYNC_LCHAN_2);
1142         D32(MXVR_SYNC_LCHAN_3);
1143         D32(MXVR_SYNC_LCHAN_4);
1144         D32(MXVR_SYNC_LCHAN_5);
1145         D32(MXVR_SYNC_LCHAN_6);
1146         D32(MXVR_SYNC_LCHAN_7);
1147         D32(MXVR_DMA0_CONFIG);
1148         D32(MXVR_DMA0_START_ADDR);
1149         D16(MXVR_DMA0_COUNT);
1150         D32(MXVR_DMA0_CURR_ADDR);
1151         D16(MXVR_DMA0_CURR_COUNT);
1152         D32(MXVR_DMA1_CONFIG);
1153         D32(MXVR_DMA1_START_ADDR);
1154         D16(MXVR_DMA1_COUNT);
1155         D32(MXVR_DMA1_CURR_ADDR);
1156         D16(MXVR_DMA1_CURR_COUNT);
1157         D32(MXVR_DMA2_CONFIG);
1158         D32(MXVR_DMA2_START_ADDR);
1159         D16(MXVR_DMA2_COUNT);
1160         D32(MXVR_DMA2_CURR_ADDR);
1161         D16(MXVR_DMA2_CURR_COUNT);
1162         D32(MXVR_DMA3_CONFIG);
1163         D32(MXVR_DMA3_START_ADDR);
1164         D16(MXVR_DMA3_COUNT);
1165         D32(MXVR_DMA3_CURR_ADDR);
1166         D16(MXVR_DMA3_CURR_COUNT);
1167         D32(MXVR_DMA4_CONFIG);
1168         D32(MXVR_DMA4_START_ADDR);
1169         D16(MXVR_DMA4_COUNT);
1170         D32(MXVR_DMA4_CURR_ADDR);
1171         D16(MXVR_DMA4_CURR_COUNT);
1172         D32(MXVR_DMA5_CONFIG);
1173         D32(MXVR_DMA5_START_ADDR);
1174         D16(MXVR_DMA5_COUNT);
1175         D32(MXVR_DMA5_CURR_ADDR);
1176         D16(MXVR_DMA5_CURR_COUNT);
1177         D32(MXVR_DMA6_CONFIG);
1178         D32(MXVR_DMA6_START_ADDR);
1179         D16(MXVR_DMA6_COUNT);
1180         D32(MXVR_DMA6_CURR_ADDR);
1181         D16(MXVR_DMA6_CURR_COUNT);
1182         D32(MXVR_DMA7_CONFIG);
1183         D32(MXVR_DMA7_START_ADDR);
1184         D16(MXVR_DMA7_COUNT);
1185         D32(MXVR_DMA7_CURR_ADDR);
1186         D16(MXVR_DMA7_CURR_COUNT);
1187         D16(MXVR_AP_CTL);
1188         D32(MXVR_APRB_START_ADDR);
1189         D32(MXVR_APRB_CURR_ADDR);
1190         D32(MXVR_APTB_START_ADDR);
1191         D32(MXVR_APTB_CURR_ADDR);
1192         D32(MXVR_CM_CTL);
1193         D32(MXVR_CMRB_START_ADDR);
1194         D32(MXVR_CMRB_CURR_ADDR);
1195         D32(MXVR_CMTB_START_ADDR);
1196         D32(MXVR_CMTB_CURR_ADDR);
1197         D32(MXVR_RRDB_START_ADDR);
1198         D32(MXVR_RRDB_CURR_ADDR);
1199         D32(MXVR_PAT_DATA_0);
1200         D32(MXVR_PAT_EN_0);
1201         D32(MXVR_PAT_DATA_1);
1202         D32(MXVR_PAT_EN_1);
1203         D16(MXVR_FRAME_CNT_0);
1204         D16(MXVR_FRAME_CNT_1);
1205         D32(MXVR_ROUTING_0);
1206         D32(MXVR_ROUTING_1);
1207         D32(MXVR_ROUTING_2);
1208         D32(MXVR_ROUTING_3);
1209         D32(MXVR_ROUTING_4);
1210         D32(MXVR_ROUTING_5);
1211         D32(MXVR_ROUTING_6);
1212         D32(MXVR_ROUTING_7);
1213         D32(MXVR_ROUTING_8);
1214         D32(MXVR_ROUTING_9);
1215         D32(MXVR_ROUTING_10);
1216         D32(MXVR_ROUTING_11);
1217         D32(MXVR_ROUTING_12);
1218         D32(MXVR_ROUTING_13);
1219         D32(MXVR_ROUTING_14);
1220 # ifdef MXVR_PLL_CTL_1
1221         D32(MXVR_PLL_CTL_1);
1222 # endif
1223         D16(MXVR_BLOCK_CNT);
1224 # ifdef MXVR_CLK_CTL
1225         D32(MXVR_CLK_CTL);
1226 # endif
1227 # ifdef MXVR_CDRPLL_CTL
1228         D32(MXVR_CDRPLL_CTL);
1229 # endif
1230 # ifdef MXVR_FMPLL_CTL
1231         D32(MXVR_FMPLL_CTL);
1232 # endif
1233 # ifdef MXVR_PIN_CTL
1234         D16(MXVR_PIN_CTL);
1235 # endif
1236 # ifdef MXVR_SCLK_CNT
1237         D16(MXVR_SCLK_CNT);
1238 # endif
1239 #endif
1240
1241 #ifdef NFC_ADDR
1242         parent = debugfs_create_dir("nfc", top);
1243         D_WO(NFC_ADDR, 16);
1244         D_WO(NFC_CMD, 16);
1245         D_RO(NFC_COUNT, 16);
1246         D16(NFC_CTL);
1247         D_WO(NFC_DATA_RD, 16);
1248         D_WO(NFC_DATA_WR, 16);
1249         D_RO(NFC_ECC0, 16);
1250         D_RO(NFC_ECC1, 16);
1251         D_RO(NFC_ECC2, 16);
1252         D_RO(NFC_ECC3, 16);
1253         D16(NFC_IRQMASK);
1254         D16(NFC_IRQSTAT);
1255         D_WO(NFC_PGCTL, 16);
1256         D_RO(NFC_READ, 16);
1257         D16(NFC_RST);
1258         D_RO(NFC_STAT, 16);
1259 #endif
1260
1261 #ifdef OTP_CONTROL
1262         parent = debugfs_create_dir("otp", top);
1263         D16(OTP_CONTROL);
1264         D16(OTP_BEN);
1265         D16(OTP_STATUS);
1266         D32(OTP_TIMING);
1267         D32(OTP_DATA0);
1268         D32(OTP_DATA1);
1269         D32(OTP_DATA2);
1270         D32(OTP_DATA3);
1271 #endif
1272
1273 #ifdef PIXC_CTL
1274         parent = debugfs_create_dir("pixc", top);
1275         D16(PIXC_CTL);
1276         D16(PIXC_PPL);
1277         D16(PIXC_LPF);
1278         D16(PIXC_AHSTART);
1279         D16(PIXC_AHEND);
1280         D16(PIXC_AVSTART);
1281         D16(PIXC_AVEND);
1282         D16(PIXC_ATRANSP);
1283         D16(PIXC_BHSTART);
1284         D16(PIXC_BHEND);
1285         D16(PIXC_BVSTART);
1286         D16(PIXC_BVEND);
1287         D16(PIXC_BTRANSP);
1288         D16(PIXC_INTRSTAT);
1289         D32(PIXC_RYCON);
1290         D32(PIXC_GUCON);
1291         D32(PIXC_BVCON);
1292         D32(PIXC_CCBIAS);
1293         D32(PIXC_TC);
1294 #endif
1295
1296         parent = debugfs_create_dir("pll", top);
1297         D16(PLL_CTL);
1298         D16(PLL_DIV);
1299         D16(PLL_LOCKCNT);
1300         D16(PLL_STAT);
1301         D16(VR_CTL);
1302         D32(CHIPID);    /* it's part of this hardware block */
1303
1304 #if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
1305         parent = debugfs_create_dir("ppi", top);
1306 # ifdef PPI_CONTROL
1307         bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
1308 # endif
1309 # ifdef PPI0_CONTROL
1310         PPI(0);
1311 # endif
1312 # ifdef PPI1_CONTROL
1313         PPI(1);
1314 # endif
1315 #endif
1316
1317 #ifdef PWM_CTRL
1318         parent = debugfs_create_dir("pwm", top);
1319         D16(PWM_CTRL);
1320         D16(PWM_STAT);
1321         D16(PWM_TM);
1322         D16(PWM_DT);
1323         D16(PWM_GATE);
1324         D16(PWM_CHA);
1325         D16(PWM_CHB);
1326         D16(PWM_CHC);
1327         D16(PWM_SEG);
1328         D16(PWM_SYNCWT);
1329         D16(PWM_CHAL);
1330         D16(PWM_CHBL);
1331         D16(PWM_CHCL);
1332         D16(PWM_LSI);
1333         D16(PWM_STAT2);
1334 #endif
1335
1336 #ifdef RSI_CONFIG
1337         parent = debugfs_create_dir("rsi", top);
1338         D32(RSI_ARGUMENT);
1339         D16(RSI_CEATA_CONTROL);
1340         D16(RSI_CLK_CONTROL);
1341         D16(RSI_COMMAND);
1342         D16(RSI_CONFIG);
1343         D16(RSI_DATA_CNT);
1344         D16(RSI_DATA_CONTROL);
1345         D16(RSI_DATA_LGTH);
1346         D32(RSI_DATA_TIMER);
1347         D16(RSI_EMASK);
1348         D16(RSI_ESTAT);
1349         D32(RSI_FIFO);
1350         D16(RSI_FIFO_CNT);
1351         D32(RSI_MASK0);
1352         D32(RSI_MASK1);
1353         D16(RSI_PID0);
1354         D16(RSI_PID1);
1355         D16(RSI_PID2);
1356         D16(RSI_PID3);
1357         D16(RSI_PID4);
1358         D16(RSI_PID5);
1359         D16(RSI_PID6);
1360         D16(RSI_PID7);
1361         D16(RSI_PWR_CONTROL);
1362         D16(RSI_RD_WAIT_EN);
1363         D32(RSI_RESPONSE0);
1364         D32(RSI_RESPONSE1);
1365         D32(RSI_RESPONSE2);
1366         D32(RSI_RESPONSE3);
1367         D16(RSI_RESP_CMD);
1368         D32(RSI_STATUS);
1369         D_WO(RSI_STATUSCL, 16);
1370 #endif
1371
1372 #ifdef RTC_ALARM
1373         parent = debugfs_create_dir("rtc", top);
1374         D32(RTC_ALARM);
1375         D16(RTC_ICTL);
1376         D16(RTC_ISTAT);
1377         D16(RTC_PREN);
1378         D32(RTC_STAT);
1379         D16(RTC_SWCNT);
1380 #endif
1381
1382 #ifdef SDH_CFG
1383         parent = debugfs_create_dir("sdh", top);
1384         D32(SDH_ARGUMENT);
1385         D16(SDH_CFG);
1386         D16(SDH_CLK_CTL);
1387         D16(SDH_COMMAND);
1388         D_RO(SDH_DATA_CNT, 16);
1389         D16(SDH_DATA_CTL);
1390         D16(SDH_DATA_LGTH);
1391         D32(SDH_DATA_TIMER);
1392         D16(SDH_E_MASK);
1393         D16(SDH_E_STATUS);
1394         D32(SDH_FIFO);
1395         D_RO(SDH_FIFO_CNT, 16);
1396         D32(SDH_MASK0);
1397         D32(SDH_MASK1);
1398         D_RO(SDH_PID0, 16);
1399         D_RO(SDH_PID1, 16);
1400         D_RO(SDH_PID2, 16);
1401         D_RO(SDH_PID3, 16);
1402         D_RO(SDH_PID4, 16);
1403         D_RO(SDH_PID5, 16);
1404         D_RO(SDH_PID6, 16);
1405         D_RO(SDH_PID7, 16);
1406         D16(SDH_PWR_CTL);
1407         D16(SDH_RD_WAIT_EN);
1408         D_RO(SDH_RESPONSE0, 32);
1409         D_RO(SDH_RESPONSE1, 32);
1410         D_RO(SDH_RESPONSE2, 32);
1411         D_RO(SDH_RESPONSE3, 32);
1412         D_RO(SDH_RESP_CMD, 16);
1413         D_RO(SDH_STATUS, 32);
1414         D_WO(SDH_STATUS_CLR, 16);
1415 #endif
1416
1417 #ifdef SECURE_CONTROL
1418         parent = debugfs_create_dir("security", top);
1419         D16(SECURE_CONTROL);
1420         D16(SECURE_STATUS);
1421         D32(SECURE_SYSSWT);
1422 #endif
1423
1424         parent = debugfs_create_dir("sic", top);
1425         D16(SWRST);
1426         D16(SYSCR);
1427         D16(SIC_RVECT);
1428         D32(SIC_IAR0);
1429         D32(SIC_IAR1);
1430         D32(SIC_IAR2);
1431 #ifdef SIC_IAR3
1432         D32(SIC_IAR3);
1433 #endif
1434 #ifdef SIC_IAR4
1435         D32(SIC_IAR4);
1436         D32(SIC_IAR5);
1437         D32(SIC_IAR6);
1438 #endif
1439 #ifdef SIC_IAR7
1440         D32(SIC_IAR7);
1441 #endif
1442 #ifdef SIC_IAR8
1443         D32(SIC_IAR8);
1444         D32(SIC_IAR9);
1445         D32(SIC_IAR10);
1446         D32(SIC_IAR11);
1447 #endif
1448 #ifdef SIC_IMASK
1449         D32(SIC_IMASK);
1450         D32(SIC_ISR);
1451         D32(SIC_IWR);
1452 #endif
1453 #ifdef SIC_IMASK0
1454         D32(SIC_IMASK0);
1455         D32(SIC_IMASK1);
1456         D32(SIC_ISR0);
1457         D32(SIC_ISR1);
1458         D32(SIC_IWR0);
1459         D32(SIC_IWR1);
1460 #endif
1461 #ifdef SIC_IMASK2
1462         D32(SIC_IMASK2);
1463         D32(SIC_ISR2);
1464         D32(SIC_IWR2);
1465 #endif
1466 #ifdef SICB_RVECT
1467         D16(SICB_SWRST);
1468         D16(SICB_SYSCR);
1469         D16(SICB_RVECT);
1470         D32(SICB_IAR0);
1471         D32(SICB_IAR1);
1472         D32(SICB_IAR2);
1473         D32(SICB_IAR3);
1474         D32(SICB_IAR4);
1475         D32(SICB_IAR5);
1476         D32(SICB_IAR6);
1477         D32(SICB_IAR7);
1478         D32(SICB_IMASK0);
1479         D32(SICB_IMASK1);
1480         D32(SICB_ISR0);
1481         D32(SICB_ISR1);
1482         D32(SICB_IWR0);
1483         D32(SICB_IWR1);
1484 #endif
1485
1486         parent = debugfs_create_dir("spi", top);
1487 #ifdef SPI0_REGBASE
1488         SPI(0);
1489 #endif
1490 #ifdef SPI1_REGBASE
1491         SPI(1);
1492 #endif
1493 #ifdef SPI2_REGBASE
1494         SPI(2);
1495 #endif
1496
1497         parent = debugfs_create_dir("sport", top);
1498 #ifdef SPORT0_STAT
1499         SPORT(0);
1500 #endif
1501 #ifdef SPORT1_STAT
1502         SPORT(1);
1503 #endif
1504 #ifdef SPORT2_STAT
1505         SPORT(2);
1506 #endif
1507 #ifdef SPORT3_STAT
1508         SPORT(3);
1509 #endif
1510
1511 #if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
1512         parent = debugfs_create_dir("twi", top);
1513 # ifdef TWI_CLKDIV
1514         bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
1515 # endif
1516 # ifdef TWI0_CLKDIV
1517         TWI(0);
1518 # endif
1519 # ifdef TWI1_CLKDIV
1520         TWI(1);
1521 # endif
1522 #endif
1523
1524         parent = debugfs_create_dir("uart", top);
1525 #ifdef BFIN_UART_DLL
1526         bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
1527 #endif
1528 #ifdef UART0_DLL
1529         UART(0);
1530 #endif
1531 #ifdef UART1_DLL
1532         UART(1);
1533 #endif
1534 #ifdef UART2_DLL
1535         UART(2);
1536 #endif
1537 #ifdef UART3_DLL
1538         UART(3);
1539 #endif
1540
1541 #ifdef USB_FADDR
1542         parent = debugfs_create_dir("usb", top);
1543         D16(USB_FADDR);
1544         D16(USB_POWER);
1545         D16(USB_INTRTX);
1546         D16(USB_INTRRX);
1547         D16(USB_INTRTXE);
1548         D16(USB_INTRRXE);
1549         D16(USB_INTRUSB);
1550         D16(USB_INTRUSBE);
1551         D16(USB_FRAME);
1552         D16(USB_INDEX);
1553         D16(USB_TESTMODE);
1554         D16(USB_GLOBINTR);
1555         D16(USB_GLOBAL_CTL);
1556         D16(USB_TX_MAX_PACKET);
1557         D16(USB_CSR0);
1558         D16(USB_TXCSR);
1559         D16(USB_RX_MAX_PACKET);
1560         D16(USB_RXCSR);
1561         D16(USB_COUNT0);
1562         D16(USB_RXCOUNT);
1563         D16(USB_TXTYPE);
1564         D16(USB_NAKLIMIT0);
1565         D16(USB_TXINTERVAL);
1566         D16(USB_RXTYPE);
1567         D16(USB_RXINTERVAL);
1568         D16(USB_TXCOUNT);
1569         D16(USB_EP0_FIFO);
1570         D16(USB_EP1_FIFO);
1571         D16(USB_EP2_FIFO);
1572         D16(USB_EP3_FIFO);
1573         D16(USB_EP4_FIFO);
1574         D16(USB_EP5_FIFO);
1575         D16(USB_EP6_FIFO);
1576         D16(USB_EP7_FIFO);
1577         D16(USB_OTG_DEV_CTL);
1578         D16(USB_OTG_VBUS_IRQ);
1579         D16(USB_OTG_VBUS_MASK);
1580         D16(USB_LINKINFO);
1581         D16(USB_VPLEN);
1582         D16(USB_HS_EOF1);
1583         D16(USB_FS_EOF1);
1584         D16(USB_LS_EOF1);
1585         D16(USB_APHY_CNTRL);
1586         D16(USB_APHY_CALIB);
1587         D16(USB_APHY_CNTRL2);
1588         D16(USB_PHY_TEST);
1589         D16(USB_PLLOSC_CTRL);
1590         D16(USB_SRP_CLKDIV);
1591         D16(USB_EP_NI0_TXMAXP);
1592         D16(USB_EP_NI0_TXCSR);
1593         D16(USB_EP_NI0_RXMAXP);
1594         D16(USB_EP_NI0_RXCSR);
1595         D16(USB_EP_NI0_RXCOUNT);
1596         D16(USB_EP_NI0_TXTYPE);
1597         D16(USB_EP_NI0_TXINTERVAL);
1598         D16(USB_EP_NI0_RXTYPE);
1599         D16(USB_EP_NI0_RXINTERVAL);
1600         D16(USB_EP_NI0_TXCOUNT);
1601         D16(USB_EP_NI1_TXMAXP);
1602         D16(USB_EP_NI1_TXCSR);
1603         D16(USB_EP_NI1_RXMAXP);
1604         D16(USB_EP_NI1_RXCSR);
1605         D16(USB_EP_NI1_RXCOUNT);
1606         D16(USB_EP_NI1_TXTYPE);
1607         D16(USB_EP_NI1_TXINTERVAL);
1608         D16(USB_EP_NI1_RXTYPE);
1609         D16(USB_EP_NI1_RXINTERVAL);
1610         D16(USB_EP_NI1_TXCOUNT);
1611         D16(USB_EP_NI2_TXMAXP);
1612         D16(USB_EP_NI2_TXCSR);
1613         D16(USB_EP_NI2_RXMAXP);
1614         D16(USB_EP_NI2_RXCSR);
1615         D16(USB_EP_NI2_RXCOUNT);
1616         D16(USB_EP_NI2_TXTYPE);
1617         D16(USB_EP_NI2_TXINTERVAL);
1618         D16(USB_EP_NI2_RXTYPE);
1619         D16(USB_EP_NI2_RXINTERVAL);
1620         D16(USB_EP_NI2_TXCOUNT);
1621         D16(USB_EP_NI3_TXMAXP);
1622         D16(USB_EP_NI3_TXCSR);
1623         D16(USB_EP_NI3_RXMAXP);
1624         D16(USB_EP_NI3_RXCSR);
1625         D16(USB_EP_NI3_RXCOUNT);
1626         D16(USB_EP_NI3_TXTYPE);
1627         D16(USB_EP_NI3_TXINTERVAL);
1628         D16(USB_EP_NI3_RXTYPE);
1629         D16(USB_EP_NI3_RXINTERVAL);
1630         D16(USB_EP_NI3_TXCOUNT);
1631         D16(USB_EP_NI4_TXMAXP);
1632         D16(USB_EP_NI4_TXCSR);
1633         D16(USB_EP_NI4_RXMAXP);
1634         D16(USB_EP_NI4_RXCSR);
1635         D16(USB_EP_NI4_RXCOUNT);
1636         D16(USB_EP_NI4_TXTYPE);
1637         D16(USB_EP_NI4_TXINTERVAL);
1638         D16(USB_EP_NI4_RXTYPE);
1639         D16(USB_EP_NI4_RXINTERVAL);
1640         D16(USB_EP_NI4_TXCOUNT);
1641         D16(USB_EP_NI5_TXMAXP);
1642         D16(USB_EP_NI5_TXCSR);
1643         D16(USB_EP_NI5_RXMAXP);
1644         D16(USB_EP_NI5_RXCSR);
1645         D16(USB_EP_NI5_RXCOUNT);
1646         D16(USB_EP_NI5_TXTYPE);
1647         D16(USB_EP_NI5_TXINTERVAL);
1648         D16(USB_EP_NI5_RXTYPE);
1649         D16(USB_EP_NI5_RXINTERVAL);
1650         D16(USB_EP_NI5_TXCOUNT);
1651         D16(USB_EP_NI6_TXMAXP);
1652         D16(USB_EP_NI6_TXCSR);
1653         D16(USB_EP_NI6_RXMAXP);
1654         D16(USB_EP_NI6_RXCSR);
1655         D16(USB_EP_NI6_RXCOUNT);
1656         D16(USB_EP_NI6_TXTYPE);
1657         D16(USB_EP_NI6_TXINTERVAL);
1658         D16(USB_EP_NI6_RXTYPE);
1659         D16(USB_EP_NI6_RXINTERVAL);
1660         D16(USB_EP_NI6_TXCOUNT);
1661         D16(USB_EP_NI7_TXMAXP);
1662         D16(USB_EP_NI7_TXCSR);
1663         D16(USB_EP_NI7_RXMAXP);
1664         D16(USB_EP_NI7_RXCSR);
1665         D16(USB_EP_NI7_RXCOUNT);
1666         D16(USB_EP_NI7_TXTYPE);
1667         D16(USB_EP_NI7_TXINTERVAL);
1668         D16(USB_EP_NI7_RXTYPE);
1669         D16(USB_EP_NI7_RXINTERVAL);
1670         D16(USB_EP_NI7_TXCOUNT);
1671         D16(USB_DMA_INTERRUPT);
1672         D16(USB_DMA0CONTROL);
1673         D16(USB_DMA0ADDRLOW);
1674         D16(USB_DMA0ADDRHIGH);
1675         D16(USB_DMA0COUNTLOW);
1676         D16(USB_DMA0COUNTHIGH);
1677         D16(USB_DMA1CONTROL);
1678         D16(USB_DMA1ADDRLOW);
1679         D16(USB_DMA1ADDRHIGH);
1680         D16(USB_DMA1COUNTLOW);
1681         D16(USB_DMA1COUNTHIGH);
1682         D16(USB_DMA2CONTROL);
1683         D16(USB_DMA2ADDRLOW);
1684         D16(USB_DMA2ADDRHIGH);
1685         D16(USB_DMA2COUNTLOW);
1686         D16(USB_DMA2COUNTHIGH);
1687         D16(USB_DMA3CONTROL);
1688         D16(USB_DMA3ADDRLOW);
1689         D16(USB_DMA3ADDRHIGH);
1690         D16(USB_DMA3COUNTLOW);
1691         D16(USB_DMA3COUNTHIGH);
1692         D16(USB_DMA4CONTROL);
1693         D16(USB_DMA4ADDRLOW);
1694         D16(USB_DMA4ADDRHIGH);
1695         D16(USB_DMA4COUNTLOW);
1696         D16(USB_DMA4COUNTHIGH);
1697         D16(USB_DMA5CONTROL);
1698         D16(USB_DMA5ADDRLOW);
1699         D16(USB_DMA5ADDRHIGH);
1700         D16(USB_DMA5COUNTLOW);
1701         D16(USB_DMA5COUNTHIGH);
1702         D16(USB_DMA6CONTROL);
1703         D16(USB_DMA6ADDRLOW);
1704         D16(USB_DMA6ADDRHIGH);
1705         D16(USB_DMA6COUNTLOW);
1706         D16(USB_DMA6COUNTHIGH);
1707         D16(USB_DMA7CONTROL);
1708         D16(USB_DMA7ADDRLOW);
1709         D16(USB_DMA7ADDRHIGH);
1710         D16(USB_DMA7COUNTLOW);
1711         D16(USB_DMA7COUNTHIGH);
1712 #endif
1713
1714 #ifdef WDOG_CNT
1715         parent = debugfs_create_dir("watchdog", top);
1716         D32(WDOG_CNT);
1717         D16(WDOG_CTL);
1718         D32(WDOG_STAT);
1719 #endif
1720 #ifdef WDOGA_CNT
1721         parent = debugfs_create_dir("watchdog", top);
1722         D32(WDOGA_CNT);
1723         D16(WDOGA_CTL);
1724         D32(WDOGA_STAT);
1725         D32(WDOGB_CNT);
1726         D16(WDOGB_CTL);
1727         D32(WDOGB_STAT);
1728 #endif
1729
1730         /* BF533 glue */
1731 #ifdef FIO_FLAG_D
1732 #define PORTFIO FIO_FLAG_D
1733 #endif
1734         /* BF561 glue */
1735 #ifdef FIO0_FLAG_D
1736 #define PORTFIO FIO0_FLAG_D
1737 #endif
1738 #ifdef FIO1_FLAG_D
1739 #define PORTGIO FIO1_FLAG_D
1740 #endif
1741 #ifdef FIO2_FLAG_D
1742 #define PORTHIO FIO2_FLAG_D
1743 #endif
1744         parent = debugfs_create_dir("port", top);
1745 #ifdef PORTFIO
1746         PORT(PORTFIO, 'F');
1747 #endif
1748 #ifdef PORTGIO
1749         PORT(PORTGIO, 'G');
1750 #endif
1751 #ifdef PORTHIO
1752         PORT(PORTHIO, 'H');
1753 #endif
1754
1755 #ifdef __ADSPBF51x__
1756         D16(PORTF_FER);
1757         D16(PORTF_DRIVE);
1758         D16(PORTF_HYSTERESIS);
1759         D16(PORTF_MUX);
1760
1761         D16(PORTG_FER);
1762         D16(PORTG_DRIVE);
1763         D16(PORTG_HYSTERESIS);
1764         D16(PORTG_MUX);
1765
1766         D16(PORTH_FER);
1767         D16(PORTH_DRIVE);
1768         D16(PORTH_HYSTERESIS);
1769         D16(PORTH_MUX);
1770
1771         D16(MISCPORT_DRIVE);
1772         D16(MISCPORT_HYSTERESIS);
1773 #endif  /* BF51x */
1774
1775 #ifdef __ADSPBF52x__
1776         D16(PORTF_FER);
1777         D16(PORTF_DRIVE);
1778         D16(PORTF_HYSTERESIS);
1779         D16(PORTF_MUX);
1780         D16(PORTF_SLEW);
1781
1782         D16(PORTG_FER);
1783         D16(PORTG_DRIVE);
1784         D16(PORTG_HYSTERESIS);
1785         D16(PORTG_MUX);
1786         D16(PORTG_SLEW);
1787
1788         D16(PORTH_FER);
1789         D16(PORTH_DRIVE);
1790         D16(PORTH_HYSTERESIS);
1791         D16(PORTH_MUX);
1792         D16(PORTH_SLEW);
1793
1794         D16(MISCPORT_DRIVE);
1795         D16(MISCPORT_HYSTERESIS);
1796         D16(MISCPORT_SLEW);
1797 #endif  /* BF52x */
1798
1799 #ifdef BF537_FAMILY
1800         D16(PORTF_FER);
1801         D16(PORTG_FER);
1802         D16(PORTH_FER);
1803         D16(PORT_MUX);
1804 #endif  /* BF534 BF536 BF537 */
1805
1806 #ifdef BF538_FAMILY
1807         D16(PORTCIO_FER);
1808         D16(PORTCIO);
1809         D16(PORTCIO_CLEAR);
1810         D16(PORTCIO_SET);
1811         D16(PORTCIO_TOGGLE);
1812         D16(PORTCIO_DIR);
1813         D16(PORTCIO_INEN);
1814
1815         D16(PORTDIO);
1816         D16(PORTDIO_CLEAR);
1817         D16(PORTDIO_DIR);
1818         D16(PORTDIO_FER);
1819         D16(PORTDIO_INEN);
1820         D16(PORTDIO_SET);
1821         D16(PORTDIO_TOGGLE);
1822
1823         D16(PORTEIO);
1824         D16(PORTEIO_CLEAR);
1825         D16(PORTEIO_DIR);
1826         D16(PORTEIO_FER);
1827         D16(PORTEIO_INEN);
1828         D16(PORTEIO_SET);
1829         D16(PORTEIO_TOGGLE);
1830 #endif  /* BF538 BF539 */
1831
1832 #ifdef __ADSPBF54x__
1833         {
1834                 int num;
1835                 unsigned long base;
1836                 char *_buf, buf[32];
1837
1838                 base = PORTA_FER;
1839                 for (num = 0; num < 10; ++num) {
1840                         PORT(base, num);
1841                         base += sizeof(struct bfin_gpio_regs);
1842                 }
1843
1844 #define __PINT(uname, lname) __REGS(pint, #uname, lname)
1845                 parent = debugfs_create_dir("pint", top);
1846                 base = PINT0_MASK_SET;
1847                 for (num = 0; num < 4; ++num) {
1848                         _buf = REGS_STR_PFX(buf, PINT, num);
1849                         __PINT(MASK_SET, mask_set);
1850                         __PINT(MASK_CLEAR, mask_clear);
1851                         __PINT(REQUEST, request);
1852                         __PINT(ASSIGN, assign);
1853                         __PINT(EDGE_SET, edge_set);
1854                         __PINT(EDGE_CLEAR, edge_clear);
1855                         __PINT(INVERT_SET, invert_set);
1856                         __PINT(INVERT_CLEAR, invert_clear);
1857                         __PINT(PINSTATE, pinstate);
1858                         __PINT(LATCH, latch);
1859                         base += sizeof(struct bfin_pint_regs);
1860                 }
1861
1862         }
1863 #endif  /* BF54x */
1864
1865         debug_mmrs_dentry = top;
1866
1867         return 0;
1868 }
1869 module_init(bfin_debug_mmrs_init);
1870
1871 static void __exit bfin_debug_mmrs_exit(void)
1872 {
1873         debugfs_remove_recursive(debug_mmrs_dentry);
1874 }
1875 module_exit(bfin_debug_mmrs_exit);
1876
1877 MODULE_LICENSE("GPL");