2 * debugfs interface to core/system MMRs
4 * Copyright 2007-2011 Analog Devices Inc.
6 * Licensed under the GPL-2 or later
9 #include <linux/debugfs.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
14 #include <asm/blackfin.h>
16 #include <asm/bfin_can.h>
17 #include <asm/bfin_dma.h>
18 #include <asm/bfin_ppi.h>
19 #include <asm/bfin_serial.h>
20 #include <asm/bfin5xx_spi.h>
21 #include <asm/bfin_twi.h>
23 /* Common code defines PORT_MUX on us, so redirect the MMR back locally */
26 #define PORT_MUX BFIN_PORT_MUX
29 #define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)addr)
30 #define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
31 #define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
32 #define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
34 #define D_RO(name, bits) d_RO(#name, bits, name)
35 #define D_WO(name, bits) d_WO(#name, bits, name)
36 #define D32(name) d(#name, 32, name)
37 #define D16(name) d(#name, 16, name)
39 #define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
40 #define __REGS(peri, sname, rname) \
42 struct bfin_##peri##_regs r; \
43 void *addr = (void *)(base + REGS_OFF(peri, rname)); \
44 strcpy(_buf, sname); \
45 if (sizeof(r.rname) == 2) \
46 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
48 debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
50 #define REGS_STR_PFX(buf, pfx, num) \
53 sprintf(buf, #pfx "%i_", num) : \
54 sprintf(buf, #pfx "_")); \
56 #define REGS_STR_PFX_C(buf, pfx, num) \
59 sprintf(buf, #pfx "%c_", 'A' + num) : \
60 sprintf(buf, #pfx "_")); \
64 * Core registers (not memory mapped)
66 extern u32 last_seqstat;
68 static int debug_cclk_get(void *data, u64 *val)
73 DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
75 static int debug_sclk_get(void *data, u64 *val)
80 DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
82 #define DEFINE_SYSREG(sr, pre, post) \
83 static int sysreg_##sr##_get(void *data, u64 *val) \
87 __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
91 static int sysreg_##sr##_set(void *data, u64 val) \
93 unsigned long tmp = val; \
94 __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
98 DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
100 DEFINE_SYSREG(cycles, , );
101 DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
102 DEFINE_SYSREG(emudat, , );
103 DEFINE_SYSREG(seqstat, , );
104 DEFINE_SYSREG(syscfg, , CSYNC());
105 #define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
110 #define CAN_OFF(mmr) REGS_OFF(can, mmr)
111 #define __CAN(uname, lname) __REGS(can, #uname, lname)
112 static void __init __maybe_unused
113 bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
115 static struct dentry *am, *mb;
117 char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
120 am = debugfs_create_dir("am", parent);
121 mb = debugfs_create_dir("mb", parent);
132 __CAN(MBTIF1, mbtif1);
133 __CAN(MBRIF1, mbrif1);
146 __CAN(MBTIF2, mbtif2);
147 __CAN(MBRIF2, mbrif2);
153 __CAN(TIMING, timing);
155 __CAN(STATUS, status);
160 __CAN(CONTROL, control);
162 __CAN(VERSION, version);
166 /*__CAN(UCREG, ucreg); no longer exists */
170 __CAN(VERSION2, version2);
172 for (i = 0; i < 32; ++i) {
173 sprintf(_buf, "AM%02iL", i);
174 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
175 (u16 *)(base + CAN_OFF(msk[i].aml)));
176 sprintf(_buf, "AM%02iH", i);
177 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
178 (u16 *)(base + CAN_OFF(msk[i].amh)));
180 for (j = 0; j < 3; ++j) {
181 sprintf(_buf, "MB%02i_DATA%i", i, j);
182 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
183 (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
185 sprintf(_buf, "MB%02i_LENGTH", i);
186 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
187 (u16 *)(base + CAN_OFF(chl[i].dlc)));
188 sprintf(_buf, "MB%02i_TIMESTAMP", i);
189 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
190 (u16 *)(base + CAN_OFF(chl[i].tsv)));
191 sprintf(_buf, "MB%02i_ID0", i);
192 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
193 (u16 *)(base + CAN_OFF(chl[i].id0)));
194 sprintf(_buf, "MB%02i_ID1", i);
195 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
196 (u16 *)(base + CAN_OFF(chl[i].id1)));
199 #define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
204 #define __DMA(uname, lname) __REGS(dma, #uname, lname)
205 static void __init __maybe_unused
206 bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
211 _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
213 _buf = buf + sprintf(buf, "%s%i_", pfx, num);
215 __DMA(NEXT_DESC_PTR, next_desc_ptr);
216 __DMA(START_ADDR, start_addr);
217 __DMA(CONFIG, config);
218 __DMA(X_COUNT, x_count);
219 __DMA(X_MODIFY, x_modify);
220 __DMA(Y_COUNT, y_count);
221 __DMA(Y_MODIFY, y_modify);
222 __DMA(CURR_DESC_PTR, curr_desc_ptr);
223 __DMA(CURR_ADDR, curr_addr);
224 __DMA(IRQ_STATUS, irq_status);
225 __DMA(PERIPHERAL_MAP, peripheral_map);
226 __DMA(CURR_X_COUNT, curr_x_count);
227 __DMA(CURR_Y_COUNT, curr_y_count);
229 #define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
230 #define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
231 #define _MDMA(num, x) \
233 _DMA(num, x##DMA_D##num##_CONFIG, 'D', #x); \
234 _DMA(num, x##DMA_S##num##_CONFIG, 'S', #x); \
236 #define MDMA(num) _MDMA(num, M)
237 #define IMDMA(num) _MDMA(num, IM)
242 #define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
243 static void __init __maybe_unused
244 bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
246 char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
247 __EPPI(STATUS, status);
248 __EPPI(HCOUNT, hcount);
249 __EPPI(HDELAY, hdelay);
250 __EPPI(VCOUNT, vcount);
251 __EPPI(VDELAY, vdelay);
252 __EPPI(FRAME, frame);
254 __EPPI(CLKDIV, clkdiv);
255 __EPPI(CONTROL, control);
256 __EPPI(FS1W_HBL, fs1w_hbl);
257 __EPPI(FS1P_AVPL, fs1p_avpl);
258 __EPPI(FS2W_LVB, fs2w_lvb);
259 __EPPI(FS2P_LAVF, fs2p_lavf);
262 #define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
265 * General Purpose Timers
267 #define GPTIMER_OFF(mmr) (TIMER0_##mmr - TIMER0_CONFIG)
268 #define __GPTIMER(name) \
270 strcpy(_buf, #name); \
271 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, (u16 *)(base + GPTIMER_OFF(name))); \
273 static void __init __maybe_unused
274 bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
276 char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
282 #define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
287 #define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
288 static void __init __maybe_unused
289 bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
291 char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
292 __HMDMA(CONTROL, control);
293 __HMDMA(ECINIT, ecinit);
294 __HMDMA(BCINIT, bcinit);
295 __HMDMA(ECURGENT, ecurgent);
296 __HMDMA(ECOVERFLOW, ecoverflow);
297 __HMDMA(ECOUNT, ecount);
298 __HMDMA(BCOUNT, bcount);
300 #define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
305 #define bfin_gpio_regs gpio_port_t
306 #define __PORT(uname, lname) __REGS(gpio, #uname, lname)
307 static void __init __maybe_unused
308 bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
312 _buf = REGS_STR_PFX_C(buf, PORT, num);
313 __PORT(FER, port_fer);
314 __PORT(SET, data_set);
315 __PORT(CLEAR, data_clear);
316 __PORT(DIR_SET, dir_set);
317 __PORT(DIR_CLEAR, dir_clear);
319 __PORT(MUX, port_mux);
321 _buf = buf + sprintf(buf, "PORT%cIO_", num);
322 __PORT(CLEAR, data_clear);
323 __PORT(SET, data_set);
324 __PORT(TOGGLE, toggle);
325 __PORT(MASKA, maska);
326 __PORT(MASKA_CLEAR, maska_clear);
327 __PORT(MASKA_SET, maska_set);
328 __PORT(MASKA_TOGGLE, maska_toggle);
329 __PORT(MASKB, maskb);
330 __PORT(MASKB_CLEAR, maskb_clear);
331 __PORT(MASKB_SET, maskb_set);
332 __PORT(MASKB_TOGGLE, maskb_toggle);
334 __PORT(POLAR, polar);
340 d(buf, 16, base + REGS_OFF(gpio, data));
342 #define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
347 #define __PPI(uname, lname) __REGS(ppi, #uname, lname)
348 static void __init __maybe_unused
349 bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
351 char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
352 __PPI(CONTROL, control);
353 __PPI(STATUS, status);
358 #define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_STATUS, num)
363 #define __SPI(uname, lname) __REGS(spi, #uname, lname)
364 static void __init __maybe_unused
365 bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
367 char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
374 __SPI(SHADOW, shadow);
376 #define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
381 static inline int sport_width(void *mmr)
383 unsigned long lmmr = (unsigned long)mmr;
384 if ((lmmr & 0xff) == 0x10)
385 /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
388 /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
390 /* extract SLEN field from control register 2 and add 1 */
391 return (bfin_read16(lmmr) & 0x1f) + 1;
393 static int sport_set(void *mmr, u64 val)
396 local_irq_save(flags);
397 if (sport_width(mmr) <= 16)
398 bfin_write16(mmr, val);
400 bfin_write32(mmr, val);
401 local_irq_restore(flags);
404 static int sport_get(void *mmr, u64 *val)
407 local_irq_save(flags);
408 if (sport_width(mmr) <= 16)
409 *val = bfin_read16(mmr);
411 *val = bfin_read32(mmr);
412 local_irq_restore(flags);
415 DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
416 /*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
417 DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
418 #define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
419 #define _D_SPORT(name, perms, fops) \
421 strcpy(_buf, #name); \
422 debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
424 #define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
425 #define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
426 #define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
427 #define __SPORT(name, bits) \
429 strcpy(_buf, #name); \
430 debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
432 static void __init __maybe_unused
433 bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
435 char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
447 __SPORT(RCLKDIV, 16);
453 __SPORT(TCLKDIV, 16);
459 #define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
464 #define __TWI(uname, lname) __REGS(twi, #uname, lname)
465 static void __init __maybe_unused
466 bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
468 char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
469 __TWI(CLKDIV, clkdiv);
470 __TWI(CONTROL, control);
471 __TWI(SLAVE_CTL, slave_ctl);
472 __TWI(SLAVE_STAT, slave_stat);
473 __TWI(SLAVE_ADDR, slave_addr);
474 __TWI(MASTER_CTL, master_ctl);
475 __TWI(MASTER_STAT, master_stat);
476 __TWI(MASTER_ADDR, master_addr);
477 __TWI(INT_STAT, int_stat);
478 __TWI(INT_MASK, int_mask);
479 __TWI(FIFO_CTL, fifo_ctl);
480 __TWI(FIFO_STAT, fifo_stat);
481 __TWI(XMT_DATA8, xmt_data8);
482 __TWI(XMT_DATA16, xmt_data16);
483 __TWI(RCV_DATA8, rcv_data8);
484 __TWI(RCV_DATA16, rcv_data16);
486 #define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
491 #define __UART(uname, lname) __REGS(uart, #uname, lname)
492 static void __init __maybe_unused
493 bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
495 char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
496 #ifdef BFIN_UART_BF54X_STYLE
505 __UART(IER_SET, ier_set);
506 __UART(IER_CLEAR, ier_clear);
524 #define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
527 * The actual debugfs generation
529 static struct dentry *debug_mmrs_dentry;
531 static int __init bfin_debug_mmrs_init(void)
533 struct dentry *top, *parent;
535 pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
537 top = debugfs_create_dir("blackfin", NULL);
541 parent = debugfs_create_dir("core_regs", top);
542 debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
543 debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
544 debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
552 parent = debugfs_create_dir("ctimer", top);
558 parent = debugfs_create_dir("cec", top);
581 parent = debugfs_create_dir("debug", top);
585 parent = debugfs_create_dir("mmu", top);
586 D32(SRAM_BASE_ADDRESS);
619 D32(DCPLB_FAULT_ADDR);
658 D32(ICPLB_FAULT_ADDR);
661 if (!ANOMALY_05000481) {
667 parent = debugfs_create_dir("perf", top);
672 parent = debugfs_create_dir("trace", top);
677 parent = debugfs_create_dir("watchpoint", top);
700 parent = debugfs_create_dir("atapi", top);
703 D16(ATAPI_DEV_RXBUF);
704 D16(ATAPI_DEV_TXBUF);
705 D16(ATAPI_DMA_TFRCNT);
707 D16(ATAPI_INT_STATUS);
708 D16(ATAPI_LINE_STATUS);
709 D16(ATAPI_MULTI_TIM_0);
710 D16(ATAPI_MULTI_TIM_1);
711 D16(ATAPI_MULTI_TIM_2);
712 D16(ATAPI_PIO_TFRCNT);
713 D16(ATAPI_PIO_TIM_0);
714 D16(ATAPI_PIO_TIM_1);
715 D16(ATAPI_REG_TIM_0);
718 D16(ATAPI_TERMINATE);
719 D16(ATAPI_UDMAOUT_TFRCNT);
720 D16(ATAPI_ULTRA_TIM_0);
721 D16(ATAPI_ULTRA_TIM_1);
722 D16(ATAPI_ULTRA_TIM_2);
723 D16(ATAPI_ULTRA_TIM_3);
724 D16(ATAPI_UMAIN_TFRCNT);
728 #if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
729 parent = debugfs_create_dir("can", top);
731 bfin_debug_mmrs_can(parent, CAN_MC1, -1);
742 parent = debugfs_create_dir("counter", top);
753 parent = debugfs_create_dir("dmac", top);
771 /* XXX: should rewrite the MMR map */
772 # define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
773 # define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
774 # define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
775 # define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
776 # define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
777 # define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
778 # define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
779 # define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
780 # define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
781 # define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
782 # define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
783 # define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
784 # define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
785 # define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
786 # define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
787 # define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
788 # define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
789 # define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
790 # define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
791 # define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
792 # define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
793 # define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
794 # define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
795 # define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
797 parent = debugfs_create_dir("dma", top);
807 #ifdef DMA8_NEXT_DESC_PTR
813 #ifdef DMA12_NEXT_DESC_PTR
823 #ifdef DMA20_NEXT_DESC_PTR
830 parent = debugfs_create_dir("ebiu_amc", top);
842 parent = debugfs_create_dir("ebiu_sdram", top);
843 # ifdef __ADSPBF561__
854 parent = debugfs_create_dir("ebiu_ddr", top);
891 parent = debugfs_create_dir("emac", top);
904 D32(EMAC_RXC_ALLFRM);
905 D32(EMAC_RXC_ALLOCT);
907 D32(EMAC_RXC_DMAOVF);
910 D32(EMAC_RXC_GE1024);
911 D32(EMAC_RXC_LNERRI);
912 D32(EMAC_RXC_LNERRO);
914 D32(EMAC_RXC_LT1024);
918 D32(EMAC_RXC_MACCTL);
922 D32(EMAC_RXC_OPCODE);
926 D32(EMAC_RXC_UNICST);
936 D32(EMAC_TXC_ALLFRM);
937 D32(EMAC_TXC_ALLOCT);
939 D32(EMAC_TXC_CRSERR);
941 D32(EMAC_TXC_DMAUND);
943 D32(EMAC_TXC_GE1024);
944 D32(EMAC_TXC_GT1COL);
945 D32(EMAC_TXC_LATECL);
946 D32(EMAC_TXC_LT1024);
950 D32(EMAC_TXC_MACCTL);
954 D32(EMAC_TXC_UNICST);
955 D32(EMAC_TXC_XS_COL);
956 D32(EMAC_TXC_XS_DFR);
963 D32(EMAC_WKUP_FFCMD);
964 D32(EMAC_WKUP_FFCRC0);
965 D32(EMAC_WKUP_FFCRC1);
966 D32(EMAC_WKUP_FFMSK0);
967 D32(EMAC_WKUP_FFMSK1);
968 D32(EMAC_WKUP_FFMSK2);
969 D32(EMAC_WKUP_FFMSK3);
970 D32(EMAC_WKUP_FFOFF);
971 # ifdef EMAC_PTP_ACCR
973 D32(EMAC_PTP_ADDEND);
974 D32(EMAC_PTP_ALARMHI);
975 D32(EMAC_PTP_ALARMLO);
981 D16(EMAC_PTP_ID_OFF);
982 D32(EMAC_PTP_ID_SNAP);
985 D32(EMAC_PTP_OFFSET);
986 D32(EMAC_PTP_PPS_PERIOD);
987 D32(EMAC_PTP_PPS_STARTHI);
988 D32(EMAC_PTP_PPS_STARTLO);
989 D32(EMAC_PTP_RXSNAPHI);
990 D32(EMAC_PTP_RXSNAPLO);
991 D32(EMAC_PTP_TIMEHI);
992 D32(EMAC_PTP_TIMELO);
993 D32(EMAC_PTP_TXSNAPHI);
994 D32(EMAC_PTP_TXSNAPLO);
998 #if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
999 parent = debugfs_create_dir("eppi", top);
1000 # ifdef EPPI0_STATUS
1003 # ifdef EPPI1_STATUS
1006 # ifdef EPPI2_STATUS
1011 parent = debugfs_create_dir("gptimer", top);
1012 #ifdef TIMER_DISABLE
1017 #ifdef TIMER_DISABLE0
1018 D16(TIMER_DISABLE0);
1022 #ifdef TIMER_DISABLE1
1023 D16(TIMER_DISABLE1);
1027 /* XXX: Should convert BF561 MMR names */
1028 #ifdef TMRS4_DISABLE
1039 #ifdef TIMER3_CONFIG
1046 #ifdef TIMER8_CONFIG
1051 #ifdef TIMER11_CONFIG
1055 #ifdef HMDMA0_CONTROL
1056 parent = debugfs_create_dir("hmdma", top);
1062 parent = debugfs_create_dir("hostdp", top);
1068 #ifdef IMDMA_S0_CONFIG
1069 parent = debugfs_create_dir("imdma", top);
1075 parent = debugfs_create_dir("keypad", top);
1084 parent = debugfs_create_dir("mdma", top);
1087 #ifdef MDMA_D2_CONFIG
1093 parent = debugfs_create_dir("mxvr", top);
1095 # ifdef MXVR_PLL_CTL_0
1096 D32(MXVR_PLL_CTL_0);
1100 D32(MXVR_INT_STAT_0);
1101 D32(MXVR_INT_STAT_1);
1105 D16(MXVR_MAX_POSITION);
1107 D16(MXVR_MAX_DELAY);
1126 D32(MXVR_SYNC_LCHAN_0);
1127 D32(MXVR_SYNC_LCHAN_1);
1128 D32(MXVR_SYNC_LCHAN_2);
1129 D32(MXVR_SYNC_LCHAN_3);
1130 D32(MXVR_SYNC_LCHAN_4);
1131 D32(MXVR_SYNC_LCHAN_5);
1132 D32(MXVR_SYNC_LCHAN_6);
1133 D32(MXVR_SYNC_LCHAN_7);
1134 D32(MXVR_DMA0_CONFIG);
1135 D32(MXVR_DMA0_START_ADDR);
1136 D16(MXVR_DMA0_COUNT);
1137 D32(MXVR_DMA0_CURR_ADDR);
1138 D16(MXVR_DMA0_CURR_COUNT);
1139 D32(MXVR_DMA1_CONFIG);
1140 D32(MXVR_DMA1_START_ADDR);
1141 D16(MXVR_DMA1_COUNT);
1142 D32(MXVR_DMA1_CURR_ADDR);
1143 D16(MXVR_DMA1_CURR_COUNT);
1144 D32(MXVR_DMA2_CONFIG);
1145 D32(MXVR_DMA2_START_ADDR);
1146 D16(MXVR_DMA2_COUNT);
1147 D32(MXVR_DMA2_CURR_ADDR);
1148 D16(MXVR_DMA2_CURR_COUNT);
1149 D32(MXVR_DMA3_CONFIG);
1150 D32(MXVR_DMA3_START_ADDR);
1151 D16(MXVR_DMA3_COUNT);
1152 D32(MXVR_DMA3_CURR_ADDR);
1153 D16(MXVR_DMA3_CURR_COUNT);
1154 D32(MXVR_DMA4_CONFIG);
1155 D32(MXVR_DMA4_START_ADDR);
1156 D16(MXVR_DMA4_COUNT);
1157 D32(MXVR_DMA4_CURR_ADDR);
1158 D16(MXVR_DMA4_CURR_COUNT);
1159 D32(MXVR_DMA5_CONFIG);
1160 D32(MXVR_DMA5_START_ADDR);
1161 D16(MXVR_DMA5_COUNT);
1162 D32(MXVR_DMA5_CURR_ADDR);
1163 D16(MXVR_DMA5_CURR_COUNT);
1164 D32(MXVR_DMA6_CONFIG);
1165 D32(MXVR_DMA6_START_ADDR);
1166 D16(MXVR_DMA6_COUNT);
1167 D32(MXVR_DMA6_CURR_ADDR);
1168 D16(MXVR_DMA6_CURR_COUNT);
1169 D32(MXVR_DMA7_CONFIG);
1170 D32(MXVR_DMA7_START_ADDR);
1171 D16(MXVR_DMA7_COUNT);
1172 D32(MXVR_DMA7_CURR_ADDR);
1173 D16(MXVR_DMA7_CURR_COUNT);
1175 D32(MXVR_APRB_START_ADDR);
1176 D32(MXVR_APRB_CURR_ADDR);
1177 D32(MXVR_APTB_START_ADDR);
1178 D32(MXVR_APTB_CURR_ADDR);
1180 D32(MXVR_CMRB_START_ADDR);
1181 D32(MXVR_CMRB_CURR_ADDR);
1182 D32(MXVR_CMTB_START_ADDR);
1183 D32(MXVR_CMTB_CURR_ADDR);
1184 D32(MXVR_RRDB_START_ADDR);
1185 D32(MXVR_RRDB_CURR_ADDR);
1186 D32(MXVR_PAT_DATA_0);
1188 D32(MXVR_PAT_DATA_1);
1190 D16(MXVR_FRAME_CNT_0);
1191 D16(MXVR_FRAME_CNT_1);
1192 D32(MXVR_ROUTING_0);
1193 D32(MXVR_ROUTING_1);
1194 D32(MXVR_ROUTING_2);
1195 D32(MXVR_ROUTING_3);
1196 D32(MXVR_ROUTING_4);
1197 D32(MXVR_ROUTING_5);
1198 D32(MXVR_ROUTING_6);
1199 D32(MXVR_ROUTING_7);
1200 D32(MXVR_ROUTING_8);
1201 D32(MXVR_ROUTING_9);
1202 D32(MXVR_ROUTING_10);
1203 D32(MXVR_ROUTING_11);
1204 D32(MXVR_ROUTING_12);
1205 D32(MXVR_ROUTING_13);
1206 D32(MXVR_ROUTING_14);
1207 # ifdef MXVR_PLL_CTL_1
1208 D32(MXVR_PLL_CTL_1);
1210 D16(MXVR_BLOCK_CNT);
1211 # ifdef MXVR_CLK_CTL
1214 # ifdef MXVR_CDRPLL_CTL
1215 D32(MXVR_CDRPLL_CTL);
1217 # ifdef MXVR_FMPLL_CTL
1218 D32(MXVR_FMPLL_CTL);
1220 # ifdef MXVR_PIN_CTL
1223 # ifdef MXVR_SCLK_CNT
1229 parent = debugfs_create_dir("nfc", top);
1232 D_RO(NFC_COUNT, 16);
1234 D_WO(NFC_DATA_RD, 16);
1235 D_WO(NFC_DATA_WR, 16);
1242 D_WO(NFC_PGCTL, 16);
1249 parent = debugfs_create_dir("otp", top);
1261 parent = debugfs_create_dir("pixc", top);
1283 parent = debugfs_create_dir("pll", top);
1289 D32(CHIPID); /* it's part of this hardware block */
1291 #if defined(PPI_STATUS) || defined(PPI0_STATUS) || defined(PPI1_STATUS)
1292 parent = debugfs_create_dir("ppi", top);
1294 bfin_debug_mmrs_ppi(parent, PPI_STATUS, -1);
1305 parent = debugfs_create_dir("pwm", top);
1324 parent = debugfs_create_dir("rsi", top);
1326 D16(RSI_CEATA_CONTROL);
1327 D16(RSI_CLK_CONTROL);
1331 D16(RSI_DATA_CONTROL);
1333 D32(RSI_DATA_TIMER);
1344 D16(RSI_PWR_CONTROL);
1345 D16(RSI_RD_WAIT_EN);
1352 D_WO(RSI_STATUSCL, 16);
1356 parent = debugfs_create_dir("rtc", top);
1366 parent = debugfs_create_dir("sdh", top);
1371 D_RO(SDH_DATA_CNT, 16);
1374 D32(SDH_DATA_TIMER);
1378 D_RO(SDH_FIFO_CNT, 16);
1390 D16(SDH_RD_WAIT_EN);
1391 D_RO(SDH_RESPONSE0, 32);
1392 D_RO(SDH_RESPONSE1, 32);
1393 D_RO(SDH_RESPONSE2, 32);
1394 D_RO(SDH_RESPONSE3, 32);
1395 D_RO(SDH_RESP_CMD, 16);
1396 D_RO(SDH_STATUS, 32);
1397 D_WO(SDH_STATUS_CLR, 16);
1400 #ifdef SECURE_CONTROL
1401 parent = debugfs_create_dir("security", top);
1402 D16(SECURE_CONTROL);
1407 parent = debugfs_create_dir("sic", top);
1469 parent = debugfs_create_dir("spi", top);
1480 parent = debugfs_create_dir("sport", top);
1494 #if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
1495 parent = debugfs_create_dir("twi", top);
1497 bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
1507 parent = debugfs_create_dir("uart", top);
1508 #ifdef BFIN_UART_DLL
1509 bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
1525 parent = debugfs_create_dir("usb", top);
1538 D16(USB_GLOBAL_CTL);
1539 D16(USB_TX_MAX_PACKET);
1542 D16(USB_RX_MAX_PACKET);
1548 D16(USB_TXINTERVAL);
1550 D16(USB_RXINTERVAL);
1560 D16(USB_OTG_DEV_CTL);
1561 D16(USB_OTG_VBUS_IRQ);
1562 D16(USB_OTG_VBUS_MASK);
1568 D16(USB_APHY_CNTRL);
1569 D16(USB_APHY_CALIB);
1570 D16(USB_APHY_CNTRL2);
1572 D16(USB_PLLOSC_CTRL);
1573 D16(USB_SRP_CLKDIV);
1574 D16(USB_EP_NI0_TXMAXP);
1575 D16(USB_EP_NI0_TXCSR);
1576 D16(USB_EP_NI0_RXMAXP);
1577 D16(USB_EP_NI0_RXCSR);
1578 D16(USB_EP_NI0_RXCOUNT);
1579 D16(USB_EP_NI0_TXTYPE);
1580 D16(USB_EP_NI0_TXINTERVAL);
1581 D16(USB_EP_NI0_RXTYPE);
1582 D16(USB_EP_NI0_RXINTERVAL);
1583 D16(USB_EP_NI0_TXCOUNT);
1584 D16(USB_EP_NI1_TXMAXP);
1585 D16(USB_EP_NI1_TXCSR);
1586 D16(USB_EP_NI1_RXMAXP);
1587 D16(USB_EP_NI1_RXCSR);
1588 D16(USB_EP_NI1_RXCOUNT);
1589 D16(USB_EP_NI1_TXTYPE);
1590 D16(USB_EP_NI1_TXINTERVAL);
1591 D16(USB_EP_NI1_RXTYPE);
1592 D16(USB_EP_NI1_RXINTERVAL);
1593 D16(USB_EP_NI1_TXCOUNT);
1594 D16(USB_EP_NI2_TXMAXP);
1595 D16(USB_EP_NI2_TXCSR);
1596 D16(USB_EP_NI2_RXMAXP);
1597 D16(USB_EP_NI2_RXCSR);
1598 D16(USB_EP_NI2_RXCOUNT);
1599 D16(USB_EP_NI2_TXTYPE);
1600 D16(USB_EP_NI2_TXINTERVAL);
1601 D16(USB_EP_NI2_RXTYPE);
1602 D16(USB_EP_NI2_RXINTERVAL);
1603 D16(USB_EP_NI2_TXCOUNT);
1604 D16(USB_EP_NI3_TXMAXP);
1605 D16(USB_EP_NI3_TXCSR);
1606 D16(USB_EP_NI3_RXMAXP);
1607 D16(USB_EP_NI3_RXCSR);
1608 D16(USB_EP_NI3_RXCOUNT);
1609 D16(USB_EP_NI3_TXTYPE);
1610 D16(USB_EP_NI3_TXINTERVAL);
1611 D16(USB_EP_NI3_RXTYPE);
1612 D16(USB_EP_NI3_RXINTERVAL);
1613 D16(USB_EP_NI3_TXCOUNT);
1614 D16(USB_EP_NI4_TXMAXP);
1615 D16(USB_EP_NI4_TXCSR);
1616 D16(USB_EP_NI4_RXMAXP);
1617 D16(USB_EP_NI4_RXCSR);
1618 D16(USB_EP_NI4_RXCOUNT);
1619 D16(USB_EP_NI4_TXTYPE);
1620 D16(USB_EP_NI4_TXINTERVAL);
1621 D16(USB_EP_NI4_RXTYPE);
1622 D16(USB_EP_NI4_RXINTERVAL);
1623 D16(USB_EP_NI4_TXCOUNT);
1624 D16(USB_EP_NI5_TXMAXP);
1625 D16(USB_EP_NI5_TXCSR);
1626 D16(USB_EP_NI5_RXMAXP);
1627 D16(USB_EP_NI5_RXCSR);
1628 D16(USB_EP_NI5_RXCOUNT);
1629 D16(USB_EP_NI5_TXTYPE);
1630 D16(USB_EP_NI5_TXINTERVAL);
1631 D16(USB_EP_NI5_RXTYPE);
1632 D16(USB_EP_NI5_RXINTERVAL);
1633 D16(USB_EP_NI5_TXCOUNT);
1634 D16(USB_EP_NI6_TXMAXP);
1635 D16(USB_EP_NI6_TXCSR);
1636 D16(USB_EP_NI6_RXMAXP);
1637 D16(USB_EP_NI6_RXCSR);
1638 D16(USB_EP_NI6_RXCOUNT);
1639 D16(USB_EP_NI6_TXTYPE);
1640 D16(USB_EP_NI6_TXINTERVAL);
1641 D16(USB_EP_NI6_RXTYPE);
1642 D16(USB_EP_NI6_RXINTERVAL);
1643 D16(USB_EP_NI6_TXCOUNT);
1644 D16(USB_EP_NI7_TXMAXP);
1645 D16(USB_EP_NI7_TXCSR);
1646 D16(USB_EP_NI7_RXMAXP);
1647 D16(USB_EP_NI7_RXCSR);
1648 D16(USB_EP_NI7_RXCOUNT);
1649 D16(USB_EP_NI7_TXTYPE);
1650 D16(USB_EP_NI7_TXINTERVAL);
1651 D16(USB_EP_NI7_RXTYPE);
1652 D16(USB_EP_NI7_RXINTERVAL);
1653 D16(USB_EP_NI7_TXCOUNT);
1654 D16(USB_DMA_INTERRUPT);
1655 D16(USB_DMA0CONTROL);
1656 D16(USB_DMA0ADDRLOW);
1657 D16(USB_DMA0ADDRHIGH);
1658 D16(USB_DMA0COUNTLOW);
1659 D16(USB_DMA0COUNTHIGH);
1660 D16(USB_DMA1CONTROL);
1661 D16(USB_DMA1ADDRLOW);
1662 D16(USB_DMA1ADDRHIGH);
1663 D16(USB_DMA1COUNTLOW);
1664 D16(USB_DMA1COUNTHIGH);
1665 D16(USB_DMA2CONTROL);
1666 D16(USB_DMA2ADDRLOW);
1667 D16(USB_DMA2ADDRHIGH);
1668 D16(USB_DMA2COUNTLOW);
1669 D16(USB_DMA2COUNTHIGH);
1670 D16(USB_DMA3CONTROL);
1671 D16(USB_DMA3ADDRLOW);
1672 D16(USB_DMA3ADDRHIGH);
1673 D16(USB_DMA3COUNTLOW);
1674 D16(USB_DMA3COUNTHIGH);
1675 D16(USB_DMA4CONTROL);
1676 D16(USB_DMA4ADDRLOW);
1677 D16(USB_DMA4ADDRHIGH);
1678 D16(USB_DMA4COUNTLOW);
1679 D16(USB_DMA4COUNTHIGH);
1680 D16(USB_DMA5CONTROL);
1681 D16(USB_DMA5ADDRLOW);
1682 D16(USB_DMA5ADDRHIGH);
1683 D16(USB_DMA5COUNTLOW);
1684 D16(USB_DMA5COUNTHIGH);
1685 D16(USB_DMA6CONTROL);
1686 D16(USB_DMA6ADDRLOW);
1687 D16(USB_DMA6ADDRHIGH);
1688 D16(USB_DMA6COUNTLOW);
1689 D16(USB_DMA6COUNTHIGH);
1690 D16(USB_DMA7CONTROL);
1691 D16(USB_DMA7ADDRLOW);
1692 D16(USB_DMA7ADDRHIGH);
1693 D16(USB_DMA7COUNTLOW);
1694 D16(USB_DMA7COUNTHIGH);
1698 parent = debugfs_create_dir("watchdog", top);
1704 parent = debugfs_create_dir("watchdog", top);
1715 #define PORTFIO FIO_FLAG_D
1719 #define PORTFIO FIO0_FLAG_D
1722 #define PORTGIO FIO1_FLAG_D
1725 #define PORTHIO FIO2_FLAG_D
1727 parent = debugfs_create_dir("port", top);
1738 #ifdef __ADSPBF51x__
1741 D16(PORTF_HYSTERESIS);
1746 D16(PORTG_HYSTERESIS);
1751 D16(PORTH_HYSTERESIS);
1754 D16(MISCPORT_DRIVE);
1755 D16(MISCPORT_HYSTERESIS);
1758 #ifdef __ADSPBF52x__
1761 D16(PORTF_HYSTERESIS);
1767 D16(PORTG_HYSTERESIS);
1773 D16(PORTH_HYSTERESIS);
1777 D16(MISCPORT_DRIVE);
1778 D16(MISCPORT_HYSTERESIS);
1787 #endif /* BF534 BF536 BF537 */
1794 D16(PORTCIO_TOGGLE);
1804 D16(PORTDIO_TOGGLE);
1812 D16(PORTEIO_TOGGLE);
1813 #endif /* BF538 BF539 */
1815 #ifdef __ADSPBF54x__
1819 char *_buf, buf[32];
1822 for (num = 0; num < 10; ++num) {
1824 base += sizeof(struct bfin_gpio_regs);
1827 #define __PINT(uname, lname) __REGS(pint, #uname, lname)
1828 parent = debugfs_create_dir("pint", top);
1829 base = PINT0_MASK_SET;
1830 for (num = 0; num < 4; ++num) {
1831 _buf = REGS_STR_PFX(buf, PINT, num);
1832 __PINT(MASK_SET, mask_set);
1833 __PINT(MASK_CLEAR, mask_clear);
1835 __PINT(ASSIGN, assign);
1836 __PINT(EDGE_SET, edge_set);
1837 __PINT(EDGE_CLEAR, edge_clear);
1838 __PINT(INVERT_SET, invert_set);
1839 __PINT(INVERT_CLEAR, invert_clear);
1840 __PINT(PINSTATE, pinstate);
1841 __PINT(LATCH, latch);
1842 base += sizeof(struct bfin_pint_regs);
1848 debug_mmrs_dentry = top;
1852 module_init(bfin_debug_mmrs_init);
1854 static void __exit bfin_debug_mmrs_exit(void)
1856 debugfs_remove_recursive(debug_mmrs_dentry);
1858 module_exit(bfin_debug_mmrs_exit);
1860 MODULE_LICENSE("GPL");