arch/blackfin/kernel/setup.c

   1 /*
   2  * Copyright 2004-2010 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #include <linux/delay.h>
   8 #include <linux/console.h>
   9 #include <linux/bootmem.h>
  10 #include <linux/seq_file.h>
  11 #include <linux/cpu.h>
  12 #include <linux/mm.h>
  13 #include <linux/module.h>
  14 #include <linux/tty.h>
  15 #include <linux/pfn.h>
  16
  17 #ifdef CONFIG_MTD_UCLINUX
  18 #include <linux/mtd/map.h>
  19 #include <linux/ext2_fs.h>
  20 #include <linux/cramfs_fs.h>
  21 #include <linux/romfs_fs.h>
  22 #endif
  23
  24 #include <asm/cplb.h>
  25 #include <asm/cacheflush.h>
  26 #include <asm/blackfin.h>
  27 #include <asm/cplbinit.h>
  28 #include <asm/clocks.h>
  29 #include <asm/div64.h>
  30 #include <asm/cpu.h>
  31 #include <asm/fixed_code.h>
  32 #include <asm/early_printk.h>
  33 #include <asm/irq_handler.h>
  34 #include <asm/pda.h>
  35
  36 u16 _bfin_swrst;
  37 EXPORT_SYMBOL(_bfin_swrst);
  38
  39 unsigned long memory_start, memory_end, physical_mem_end;
  40 unsigned long _rambase, _ramstart, _ramend;
  41 unsigned long reserved_mem_dcache_on;
  42 unsigned long reserved_mem_icache_on;
  43 EXPORT_SYMBOL(memory_start);
  44 EXPORT_SYMBOL(memory_end);
  45 EXPORT_SYMBOL(physical_mem_end);
  46 EXPORT_SYMBOL(_ramend);
  47 EXPORT_SYMBOL(reserved_mem_dcache_on);
  48
  49 #ifdef CONFIG_MTD_UCLINUX
  50 extern struct map_info uclinux_ram_map;
  51 unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
  52 unsigned long _ebss;
  53 EXPORT_SYMBOL(memory_mtd_end);
  54 EXPORT_SYMBOL(memory_mtd_start);
  55 EXPORT_SYMBOL(mtd_size);
  56 #endif
  57
  58 char __initdata command_line[COMMAND_LINE_SIZE];
  59 struct blackfin_initial_pda __initdata initial_pda;
  60
  61 /* boot memmap, for parsing "memmap=" */
  62 #define BFIN_MEMMAP_MAX         128 /* number of entries in bfin_memmap */
  63 #define BFIN_MEMMAP_RAM         1
  64 #define BFIN_MEMMAP_RESERVED    2
  65 static struct bfin_memmap {
  66         int nr_map;
  67         struct bfin_memmap_entry {
  68                 unsigned long long addr; /* start of memory segment */
  69                 unsigned long long size;
  70                 unsigned long type;
  71         } map[BFIN_MEMMAP_MAX];
  72 } bfin_memmap __initdata;
  73
  74 /* for memmap sanitization */
  75 struct change_member {
  76         struct bfin_memmap_entry *pentry; /* pointer to original entry */
  77         unsigned long long addr; /* address for this change point */
  78 };
  79 static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
  80 static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
  81 static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
  82 static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
  83
  84 DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
  85
  86 static int early_init_clkin_hz(char *buf);
  87
  88 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
  89 void __init generate_cplb_tables(void)
  90 {
  91         unsigned int cpu;
  92
  93         generate_cplb_tables_all();
  94         /* Generate per-CPU I&D CPLB tables */
  95         for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
  96                 generate_cplb_tables_cpu(cpu);
  97 }
  98 #endif
  99
 100 void __cpuinit bfin_setup_caches(unsigned int cpu)
 101 {
 102 #ifdef CONFIG_BFIN_ICACHE
 103         bfin_icache_init(icplb_tbl[cpu]);
 104 #endif
 105
 106 #ifdef CONFIG_BFIN_DCACHE
 107         bfin_dcache_init(dcplb_tbl[cpu]);
 108 #endif
 109
 110         bfin_setup_cpudata(cpu);
 111
 112         /*
 113          * In cache coherence emulation mode, we need to have the
 114          * D-cache enabled before running any atomic operation which
 115          * might involve cache invalidation (i.e. spinlock, rwlock).
 116          * So printk's are deferred until then.
 117          */
 118 #ifdef CONFIG_BFIN_ICACHE
 119         printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
 120         printk(KERN_INFO "  External memory:"
 121 # ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
 122                " cacheable"
 123 # else
 124                " uncacheable"
 125 # endif
 126                " in instruction cache\n");
 127         if (L2_LENGTH)
 128                 printk(KERN_INFO "  L2 SRAM        :"
 129 # ifdef CONFIG_BFIN_L2_ICACHEABLE
 130                        " cacheable"
 131 # else
 132                        " uncacheable"
 133 # endif
 134                        " in instruction cache\n");
 135
 136 #else
 137         printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
 138 #endif
 139
 140 #ifdef CONFIG_BFIN_DCACHE
 141         printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
 142         printk(KERN_INFO "  External memory:"
 143 # if defined CONFIG_BFIN_EXTMEM_WRITEBACK
 144                " cacheable (write-back)"
 145 # elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
 146                " cacheable (write-through)"
 147 # else
 148                " uncacheable"
 149 # endif
 150                " in data cache\n");
 151         if (L2_LENGTH)
 152                 printk(KERN_INFO "  L2 SRAM        :"
 153 # if defined CONFIG_BFIN_L2_WRITEBACK
 154                        " cacheable (write-back)"
 155 # elif defined CONFIG_BFIN_L2_WRITETHROUGH
 156                        " cacheable (write-through)"
 157 # else
 158                        " uncacheable"
 159 # endif
 160                        " in data cache\n");
 161 #else
 162         printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
 163 #endif
 164 }
 165
 166 void __cpuinit bfin_setup_cpudata(unsigned int cpu)
 167 {
 168         struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
 169
 170         cpudata->imemctl = bfin_read_IMEM_CONTROL();
 171         cpudata->dmemctl = bfin_read_DMEM_CONTROL();
 172 }
 173
 174 void __init bfin_cache_init(void)
 175 {
 176 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
 177         generate_cplb_tables();
 178 #endif
 179         bfin_setup_caches(0);
 180 }
 181
 182 void __init bfin_relocate_l1_mem(void)
 183 {
 184         unsigned long text_l1_len = (unsigned long)_text_l1_len;
 185         unsigned long data_l1_len = (unsigned long)_data_l1_len;
 186         unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
 187         unsigned long l2_len = (unsigned long)_l2_len;
 188
 189         early_shadow_stamp();
 190
 191         /*
 192          * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
 193          * we know that everything about l1 text/data is nice and aligned,
 194          * so copy by 4 byte chunks, and don't worry about overlapping
 195          * src/dest.
 196          *
 197          * We can't use the dma_memcpy functions, since they can call
 198          * scheduler functions which might be in L1 :( and core writes
 199          * into L1 instruction cause bad access errors, so we are stuck,
 200          * we are required to use DMA, but can't use the common dma
 201          * functions. We can't use memcpy either - since that might be
 202          * going to be in the relocated L1
 203          */
 204
 205         blackfin_dma_early_init();
 206
 207         /* if necessary, copy L1 text to L1 instruction SRAM */
 208         if (L1_CODE_LENGTH && text_l1_len)
 209                 early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len);
 210
 211         /* if necessary, copy L1 data to L1 data bank A SRAM */
 212         if (L1_DATA_A_LENGTH && data_l1_len)
 213                 early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len);
 214
 215         /* if necessary, copy L1 data B to L1 data bank B SRAM */
 216         if (L1_DATA_B_LENGTH && data_b_l1_len)
 217                 early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len);
 218
 219         early_dma_memcpy_done();
 220
 221 #if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
 222         blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1;
 223 #endif
 224
 225         /* if necessary, copy L2 text/data to L2 SRAM */
 226         if (L2_LENGTH && l2_len)
 227                 memcpy(_stext_l2, _l2_lma, l2_len);
 228 }
 229
 230 #ifdef CONFIG_SMP
 231 void __init bfin_relocate_coreb_l1_mem(void)
 232 {
 233         unsigned long text_l1_len = (unsigned long)_text_l1_len;
 234         unsigned long data_l1_len = (unsigned long)_data_l1_len;
 235         unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
 236
 237         blackfin_dma_early_init();
 238
 239         /* if necessary, copy L1 text to L1 instruction SRAM */
 240         if (L1_CODE_LENGTH && text_l1_len)
 241                 early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
 242                                 text_l1_len);
 243
 244         /* if necessary, copy L1 data to L1 data bank A SRAM */
 245         if (L1_DATA_A_LENGTH && data_l1_len)
 246                 early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma,
 247                                 data_l1_len);
 248
 249         /* if necessary, copy L1 data B to L1 data bank B SRAM */
 250         if (L1_DATA_B_LENGTH && data_b_l1_len)
 251                 early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma,
 252                                 data_b_l1_len);
 253
 254         early_dma_memcpy_done();
 255
 256 #ifdef CONFIG_ICACHE_FLUSH_L1
 257         blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 -
 258                         (unsigned long)_stext_l1 + COREB_L1_CODE_START;
 259 #endif
 260 }
 261 #endif
 262
 263 #ifdef CONFIG_ROMKERNEL
 264 void __init bfin_relocate_xip_data(void)
 265 {
 266         early_shadow_stamp();
 267
 268         memcpy(_sdata, _data_lma, (unsigned long)_data_len - THREAD_SIZE + sizeof(struct thread_info));
 269         memcpy(_sinitdata, _init_data_lma, (unsigned long)_init_data_len);
 270 }
 271 #endif
 272
 273 /* add_memory_region to memmap */
 274 static void __init add_memory_region(unsigned long long start,
 275                               unsigned long long size, int type)
 276 {
 277         int i;
 278
 279         i = bfin_memmap.nr_map;
 280
 281         if (i == BFIN_MEMMAP_MAX) {
 282                 printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
 283                 return;
 284         }
 285
 286         bfin_memmap.map[i].addr = start;
 287         bfin_memmap.map[i].size = size;
 288         bfin_memmap.map[i].type = type;
 289         bfin_memmap.nr_map++;
 290 }
 291
 292 /*
 293  * Sanitize the boot memmap, removing overlaps.
 294  */
 295 static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
 296 {
 297         struct change_member *change_tmp;
 298         unsigned long current_type, last_type;
 299         unsigned long long last_addr;
 300         int chgidx, still_changing;
 301         int overlap_entries;
 302         int new_entry;
 303         int old_nr, new_nr, chg_nr;
 304         int i;
 305
 306         /*
 307                 Visually we're performing the following (1,2,3,4 = memory types)
 308
 309                 Sample memory map (w/overlaps):
 310                    ____22__________________
 311                    ______________________4_
 312                    ____1111________________
 313                    _44_____________________
 314                    11111111________________
 315                    ____________________33__
 316                    ___________44___________
 317                    __________33333_________
 318                    ______________22________
 319                    ___________________2222_
 320                    _________111111111______
 321                    _____________________11_
 322                    _________________4______
 323
 324                 Sanitized equivalent (no overlap):
 325                    1_______________________
 326                    _44_____________________
 327                    ___1____________________
 328                    ____22__________________
 329                    ______11________________
 330                    _________1______________
 331                    __________3_____________
 332                    ___________44___________
 333                    _____________33_________
 334                    _______________2________
 335                    ________________1_______
 336                    _________________4______
 337                    ___________________2____
 338                    ____________________33__
 339                    ______________________4_
 340         */
 341         /* if there's only one memory region, don't bother */
 342         if (*pnr_map < 2)
 343                 return -1;
 344
 345         old_nr = *pnr_map;
 346
 347         /* bail out if we find any unreasonable addresses in memmap */
 348         for (i = 0; i < old_nr; i++)
 349                 if (map[i].addr + map[i].size < map[i].addr)
 350                         return -1;
 351
 352         /* create pointers for initial change-point information (for sorting) */
 353         for (i = 0; i < 2*old_nr; i++)
 354                 change_point[i] = &change_point_list[i];
 355
 356         /* record all known change-points (starting and ending addresses),
 357            omitting those that are for empty memory regions */
 358         chgidx = 0;
 359         for (i = 0; i < old_nr; i++) {
 360                 if (map[i].size != 0) {
 361                         change_point[chgidx]->addr = map[i].addr;
 362                         change_point[chgidx++]->pentry = &map[i];
 363                         change_point[chgidx]->addr = map[i].addr + map[i].size;
 364                         change_point[chgidx++]->pentry = &map[i];
 365                 }
 366         }
 367         chg_nr = chgidx;        /* true number of change-points */
 368
 369         /* sort change-point list by memory addresses (low -> high) */
 370         still_changing = 1;
 371         while (still_changing) {
 372                 still_changing = 0;
 373                 for (i = 1; i < chg_nr; i++) {
 374                         /* if <current_addr> > <last_addr>, swap */
 375                         /* or, if current=<start_addr> & last=<end_addr>, swap */
 376                         if ((change_point[i]->addr < change_point[i-1]->addr) ||
 377                                 ((change_point[i]->addr == change_point[i-1]->addr) &&
 378                                  (change_point[i]->addr == change_point[i]->pentry->addr) &&
 379                                  (change_point[i-1]->addr != change_point[i-1]->pentry->addr))
 380                            ) {
 381                                 change_tmp = change_point[i];
 382                                 change_point[i] = change_point[i-1];
 383                                 change_point[i-1] = change_tmp;
 384                                 still_changing = 1;
 385                         }
 386                 }
 387         }
 388
 389         /* create a new memmap, removing overlaps */
 390         overlap_entries = 0;    /* number of entries in the overlap table */
 391         new_entry = 0;          /* index for creating new memmap entries */
 392         last_type = 0;          /* start with undefined memory type */
 393         last_addr = 0;          /* start with 0 as last starting address */
 394         /* loop through change-points, determining affect on the new memmap */
 395         for (chgidx = 0; chgidx < chg_nr; chgidx++) {
 396                 /* keep track of all overlapping memmap entries */
 397                 if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
 398                         /* add map entry to overlap list (> 1 entry implies an overlap) */
 399                         overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
 400                 } else {
 401                         /* remove entry from list (order independent, so swap with last) */
 402                         for (i = 0; i < overlap_entries; i++) {
 403                                 if (overlap_list[i] == change_point[chgidx]->pentry)
 404                                         overlap_list[i] = overlap_list[overlap_entries-1];
 405                         }
 406                         overlap_entries--;
 407                 }
 408                 /* if there are overlapping entries, decide which "type" to use */
 409                 /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
 410                 current_type = 0;
 411                 for (i = 0; i < overlap_entries; i++)
 412                         if (overlap_list[i]->type > current_type)
 413                                 current_type = overlap_list[i]->type;
 414                 /* continue building up new memmap based on this information */
 415                 if (current_type != last_type) {
 416                         if (last_type != 0) {
 417                                 new_map[new_entry].size =
 418                                         change_point[chgidx]->addr - last_addr;
 419                                 /* move forward only if the new size was non-zero */
 420                                 if (new_map[new_entry].size != 0)
 421                                         if (++new_entry >= BFIN_MEMMAP_MAX)
 422                                                 break;  /* no more space left for new entries */
 423                         }
 424                         if (current_type != 0) {
 425                                 new_map[new_entry].addr = change_point[chgidx]->addr;
 426                                 new_map[new_entry].type = current_type;
 427                                 last_addr = change_point[chgidx]->addr;
 428                         }
 429                         last_type = current_type;
 430                 }
 431         }
 432         new_nr = new_entry;     /* retain count for new entries */
 433
 434         /* copy new mapping into original location */
 435         memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
 436         *pnr_map = new_nr;
 437
 438         return 0;
 439 }
 440
 441 static void __init print_memory_map(char *who)
 442 {
 443         int i;
 444
 445         for (i = 0; i < bfin_memmap.nr_map; i++) {
 446                 printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
 447                         bfin_memmap.map[i].addr,
 448                         bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
 449                 switch (bfin_memmap.map[i].type) {
 450                 case BFIN_MEMMAP_RAM:
 451                         printk(KERN_CONT "(usable)\n");
 452                         break;
 453                 case BFIN_MEMMAP_RESERVED:
 454                         printk(KERN_CONT "(reserved)\n");
 455                         break;
 456                 default:
 457                         printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type);
 458                         break;
 459                 }
 460         }
 461 }
 462
 463 static __init int parse_memmap(char *arg)
 464 {
 465         unsigned long long start_at, mem_size;
 466
 467         if (!arg)
 468                 return -EINVAL;
 469
 470         mem_size = memparse(arg, &arg);
 471         if (*arg == '@') {
 472                 start_at = memparse(arg+1, &arg);
 473                 add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
 474         } else if (*arg == '$') {
 475                 start_at = memparse(arg+1, &arg);
 476                 add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
 477         }
 478
 479         return 0;
 480 }
 481
 482 /*
 483  * Initial parsing of the command line.  Currently, we support:
 484  *  - Controlling the linux memory size: mem=xxx[KMG]
 485  *  - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
 486  *       $ -> reserved memory is dcacheable
 487  *       # -> reserved memory is icacheable
 488  *  - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
 489  *       @ from <start> to <start>+<mem>, type RAM
 490  *       $ from <start> to <start>+<mem>, type RESERVED
 491  */
 492 static __init void parse_cmdline_early(char *cmdline_p)
 493 {
 494         char c = ' ', *to = cmdline_p;
 495         unsigned int memsize;
 496         for (;;) {
 497                 if (c == ' ') {
 498                         if (!memcmp(to, "mem=", 4)) {
 499                                 to += 4;
 500                                 memsize = memparse(to, &to);
 501                                 if (memsize)
 502                                         _ramend = memsize;
 503
 504                         } else if (!memcmp(to, "max_mem=", 8)) {
 505                                 to += 8;
 506                                 memsize = memparse(to, &to);
 507                                 if (memsize) {
 508                                         physical_mem_end = memsize;
 509                                         if (*to != ' ') {
 510                                                 if (*to == '$'
 511                                                     || *(to + 1) == '$')
 512                                                         reserved_mem_dcache_on = 1;
 513                                                 if (*to == '#'
 514                                                     || *(to + 1) == '#')
 515                                                         reserved_mem_icache_on = 1;
 516                                         }
 517                                 }
 518                         } else if (!memcmp(to, "clkin_hz=", 9)) {
 519                                 to += 9;
 520                                 early_init_clkin_hz(to);
 521 #ifdef CONFIG_EARLY_PRINTK
 522                         } else if (!memcmp(to, "earlyprintk=", 12)) {
 523                                 to += 12;
 524                                 setup_early_printk(to);
 525 #endif
 526                         } else if (!memcmp(to, "memmap=", 7)) {
 527                                 to += 7;
 528                                 parse_memmap(to);
 529                         }
 530                 }
 531                 c = *(to++);
 532                 if (!c)
 533                         break;
 534         }
 535 }
 536
 537 /*
 538  * Setup memory defaults from user config.
 539  * The physical memory layout looks like:
 540  *
 541  *  [_rambase, _ramstart]:              kernel image
 542  *  [memory_start, memory_end]:         dynamic memory managed by kernel
 543  *  [memory_end, _ramend]:              reserved memory
 544  *      [memory_mtd_start(memory_end),
 545  *              memory_mtd_start + mtd_size]:   rootfs (if any)
 546  *      [_ramend - DMA_UNCACHED_REGION,
 547  *              _ramend]:                       uncached DMA region
 548  *  [_ramend, physical_mem_end]:        memory not managed by kernel
 549  */
 550 static __init void memory_setup(void)
 551 {
 552 #ifdef CONFIG_MTD_UCLINUX
 553         unsigned long mtd_phys = 0;
 554 #endif
 555         unsigned long max_mem;
 556
 557         _rambase = CONFIG_BOOT_LOAD;
 558         _ramstart = (unsigned long)_end;
 559
 560         if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
 561                 console_init();
 562                 panic("DMA region exceeds memory limit: %lu.",
 563                         _ramend - _ramstart);
 564         }
 565         max_mem = memory_end = _ramend - DMA_UNCACHED_REGION;
 566
 567 #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
 568         /* Due to a Hardware Anomaly we need to limit the size of usable
 569          * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
 570          * 05000263 - Hardware loop corrupted when taking an ICPLB exception
 571          */
 572 # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
 573         if (max_mem >= 56 * 1024 * 1024)
 574                 max_mem = 56 * 1024 * 1024;
 575 # else
 576         if (max_mem >= 60 * 1024 * 1024)
 577                 max_mem = 60 * 1024 * 1024;
 578 # endif                         /* CONFIG_DEBUG_HUNT_FOR_ZERO */
 579 #endif                          /* ANOMALY_05000263 */
 580
 581
 582 #ifdef CONFIG_MPU
 583         /* Round up to multiple of 4MB */
 584         memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
 585 #else
 586         memory_start = PAGE_ALIGN(_ramstart);
 587 #endif
 588
 589 #if defined(CONFIG_MTD_UCLINUX)
 590         /* generic memory mapped MTD driver */
 591         memory_mtd_end = memory_end;
 592
 593         mtd_phys = _ramstart;
 594         mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
 595
 596 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
 597         if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
 598                 mtd_size =
 599                     PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
 600 # endif
 601
 602 # if defined(CONFIG_CRAMFS)
 603         if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
 604                 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
 605 # endif
 606
 607 # if defined(CONFIG_ROMFS_FS)
 608         if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
 609             && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) {
 610                 mtd_size =
 611                     PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
 612
 613                 /* ROM_FS is XIP, so if we found it, we need to limit memory */
 614                 if (memory_end > max_mem) {
 615                         pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
 616                                 (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
 617                         memory_end = max_mem;
 618                 }
 619         }
 620 # endif                         /* CONFIG_ROMFS_FS */
 621
 622         /* Since the default MTD_UCLINUX has no magic number, we just blindly
 623          * read 8 past the end of the kernel's image, and look at it.
 624          * When no image is attached, mtd_size is set to a random number
 625          * Do some basic sanity checks before operating on things
 626          */
 627         if (mtd_size == 0 || memory_end <= mtd_size) {
 628                 pr_emerg("Could not find valid ram mtd attached.\n");
 629         } else {
 630                 memory_end -= mtd_size;
 631
 632                 /* Relocate MTD image to the top of memory after the uncached memory area */
 633                 uclinux_ram_map.phys = memory_mtd_start = memory_end;
 634                 uclinux_ram_map.size = mtd_size;
 635                 pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n",
 636                         _end, mtd_size, (void *)memory_mtd_start);
 637                 dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
 638         }
 639 #endif                          /* CONFIG_MTD_UCLINUX */
 640
 641         /* We need lo limit memory, since everything could have a text section
 642          * of userspace in it, and expose anomaly 05000263. If the anomaly
 643          * doesn't exist, or we don't need to - then dont.
 644          */
 645         if (memory_end > max_mem) {
 646                 pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
 647                                 (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
 648                 memory_end = max_mem;
 649         }
 650
 651 #ifdef CONFIG_MPU
 652 #if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
 653         page_mask_nelts = (((_ramend + ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE -
 654                                         ASYNC_BANK0_BASE) >> PAGE_SHIFT) + 31) / 32;
 655 #else
 656         page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
 657 #endif
 658         page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
 659 #endif
 660
 661         init_mm.start_code = (unsigned long)_stext;
 662         init_mm.end_code = (unsigned long)_etext;
 663         init_mm.end_data = (unsigned long)_edata;
 664         init_mm.brk = (unsigned long)0;
 665
 666         printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
 667         printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
 668
 669         printk(KERN_INFO "Memory map:\n"
 670                "  fixedcode = 0x%p-0x%p\n"
 671                "  text      = 0x%p-0x%p\n"
 672                "  rodata    = 0x%p-0x%p\n"
 673                "  bss       = 0x%p-0x%p\n"
 674                "  data      = 0x%p-0x%p\n"
 675                "    stack   = 0x%p-0x%p\n"
 676                "  init      = 0x%p-0x%p\n"
 677                "  available = 0x%p-0x%p\n"
 678 #ifdef CONFIG_MTD_UCLINUX
 679                "  rootfs    = 0x%p-0x%p\n"
 680 #endif
 681 #if DMA_UNCACHED_REGION > 0
 682                "  DMA Zone  = 0x%p-0x%p\n"
 683 #endif
 684                 , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
 685                 _stext, _etext,
 686                 __start_rodata, __end_rodata,
 687                 __bss_start, __bss_stop,
 688                 _sdata, _edata,
 689                 (void *)&init_thread_union,
 690                 (void *)((int)(&init_thread_union) + THREAD_SIZE),
 691                 __init_begin, __init_end,
 692                 (void *)_ramstart, (void *)memory_end
 693 #ifdef CONFIG_MTD_UCLINUX
 694                 , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
 695 #endif
 696 #if DMA_UNCACHED_REGION > 0
 697                 , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
 698 #endif
 699                 );
 700 }
 701
 702 /*
 703  * Find the lowest, highest page frame number we have available
 704  */
 705 void __init find_min_max_pfn(void)
 706 {
 707         int i;
 708
 709         max_pfn = 0;
 710         min_low_pfn = PFN_DOWN(memory_end);
 711
 712         for (i = 0; i < bfin_memmap.nr_map; i++) {
 713                 unsigned long start, end;
 714                 /* RAM? */
 715                 if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
 716                         continue;
 717                 start = PFN_UP(bfin_memmap.map[i].addr);
 718                 end = PFN_DOWN(bfin_memmap.map[i].addr +
 719                                 bfin_memmap.map[i].size);
 720                 if (start >= end)
 721                         continue;
 722                 if (end > max_pfn)
 723                         max_pfn = end;
 724                 if (start < min_low_pfn)
 725                         min_low_pfn = start;
 726         }
 727 }
 728
 729 static __init void setup_bootmem_allocator(void)
 730 {
 731         int bootmap_size;
 732         int i;
 733         unsigned long start_pfn, end_pfn;
 734         unsigned long curr_pfn, last_pfn, size;
 735
 736         /* mark memory between memory_start and memory_end usable */
 737         add_memory_region(memory_start,
 738                 memory_end - memory_start, BFIN_MEMMAP_RAM);
 739         /* sanity check for overlap */
 740         sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
 741         print_memory_map("boot memmap");
 742
 743         /* initialize globals in linux/bootmem.h */
 744         find_min_max_pfn();
 745         /* pfn of the last usable page frame */
 746         if (max_pfn > memory_end >> PAGE_SHIFT)
 747                 max_pfn = memory_end >> PAGE_SHIFT;
 748         /* pfn of last page frame directly mapped by kernel */
 749         max_low_pfn = max_pfn;
 750         /* pfn of the first usable page frame after kernel image*/
 751         if (min_low_pfn < memory_start >> PAGE_SHIFT)
 752                 min_low_pfn = memory_start >> PAGE_SHIFT;
 753         start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
 754         end_pfn = memory_end >> PAGE_SHIFT;
 755
 756         /*
 757          * give all the memory to the bootmap allocator, tell it to put the
 758          * boot mem_map at the start of memory.
 759          */
 760         bootmap_size = init_bootmem_node(NODE_DATA(0),
 761                         memory_start >> PAGE_SHIFT,     /* map goes here */
 762                         start_pfn, end_pfn);
 763
 764         /* register the memmap regions with the bootmem allocator */
 765         for (i = 0; i < bfin_memmap.nr_map; i++) {
 766                 /*
 767                  * Reserve usable memory
 768                  */
 769                 if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
 770                         continue;
 771                 /*
 772                  * We are rounding up the start address of usable memory:
 773                  */
 774                 curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
 775                 if (curr_pfn >= end_pfn)
 776                         continue;
 777                 /*
 778                  * ... and at the end of the usable range downwards:
 779                  */
 780                 last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
 781                                          bfin_memmap.map[i].size);
 782
 783                 if (last_pfn > end_pfn)
 784                         last_pfn = end_pfn;
 785
 786                 /*
 787                  * .. finally, did all the rounding and playing
 788                  * around just make the area go away?
 789                  */
 790                 if (last_pfn <= curr_pfn)
 791                         continue;
 792
 793                 size = last_pfn - curr_pfn;
 794                 free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
 795         }
 796
 797         /* reserve memory before memory_start, including bootmap */
 798         reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
 799                 memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
 800                 BOOTMEM_DEFAULT);
 801 }
 802
 803 #define EBSZ_TO_MEG(ebsz) \
 804 ({ \
 805         int meg = 0; \
 806         switch (ebsz & 0xf) { \
 807                 case 0x1: meg =  16; break; \
 808                 case 0x3: meg =  32; break; \
 809                 case 0x5: meg =  64; break; \
 810                 case 0x7: meg = 128; break; \
 811                 case 0x9: meg = 256; break; \
 812                 case 0xb: meg = 512; break; \
 813         } \
 814         meg; \
 815 })
 816 static inline int __init get_mem_size(void)
 817 {
 818 #if defined(EBIU_SDBCTL)
 819 # if defined(BF561_FAMILY)
 820         int ret = 0;
 821         u32 sdbctl = bfin_read_EBIU_SDBCTL();
 822         ret += EBSZ_TO_MEG(sdbctl >>  0);
 823         ret += EBSZ_TO_MEG(sdbctl >>  8);
 824         ret += EBSZ_TO_MEG(sdbctl >> 16);
 825         ret += EBSZ_TO_MEG(sdbctl >> 24);
 826         return ret;
 827 # else
 828         return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
 829 # endif
 830 #elif defined(EBIU_DDRCTL1)
 831         u32 ddrctl = bfin_read_EBIU_DDRCTL1();
 832         int ret = 0;
 833         switch (ddrctl & 0xc0000) {
 834         case DEVSZ_64:
 835                 ret = 64 / 8;
 836                 break;
 837         case DEVSZ_128:
 838                 ret = 128 / 8;
 839                 break;
 840         case DEVSZ_256:
 841                 ret = 256 / 8;
 842                 break;
 843         case DEVSZ_512:
 844                 ret = 512 / 8;
 845                 break;
 846         }
 847         switch (ddrctl & 0x30000) {
 848         case DEVWD_4:
 849                 ret *= 2;
 850         case DEVWD_8:
 851                 ret *= 2;
 852         case DEVWD_16:
 853                 break;
 854         }
 855         if ((ddrctl & 0xc000) == 0x4000)
 856                 ret *= 2;
 857         return ret;
 858 #elif defined(CONFIG_BF60x)
 859         u32 ddrctl = bfin_read_DDR0_CFG();
 860         int ret;
 861         switch (ddrctl & 0xf00) {
 862         case DEVSZ_64:
 863                 ret = 64 / 8;
 864                 break;
 865         case DEVSZ_128:
 866                 ret = 128 / 8;
 867                 break;
 868         case DEVSZ_256:
 869                 ret = 256 / 8;
 870                 break;
 871         case DEVSZ_512:
 872                 ret = 512 / 8;
 873                 break;
 874         case DEVSZ_1G:
 875                 ret = 1024 / 8;
 876                 break;
 877         case DEVSZ_2G:
 878                 ret = 2048 / 8;
 879                 break;
 880         }
 881         return ret;
 882 #endif
 883         BUG();
 884 }
 885
 886 __attribute__((weak))
 887 void __init native_machine_early_platform_add_devices(void)
 888 {
 889 }
 890
 891 void __init setup_arch(char **cmdline_p)
 892 {
 893         u32 mmr;
 894         unsigned long sclk, cclk;
 895         struct clk *clk;
 896
 897         native_machine_early_platform_add_devices();
 898
 899         enable_shadow_console();
 900
 901         /* Check to make sure we are running on the right processor */
 902         mmr =  bfin_cpuid();
 903         if (unlikely(CPUID != bfin_cpuid()))
 904                 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
 905                         CPU, bfin_cpuid(), bfin_revid());
 906
 907 #ifdef CONFIG_DUMMY_CONSOLE
 908         conswitchp = &dummy_con;
 909 #endif
 910
 911 #if defined(CONFIG_CMDLINE_BOOL)
 912         strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
 913         command_line[sizeof(command_line) - 1] = 0;
 914 #endif
 915
 916         /* Keep a copy of command line */
 917         *cmdline_p = &command_line[0];
 918         memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
 919         boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
 920
 921         memset(&bfin_memmap, 0, sizeof(bfin_memmap));
 922
 923 #ifdef CONFIG_BF60x
 924         /* Should init clock device before parse command early */
 925         clk_init();
 926 #endif
 927         /* If the user does not specify things on the command line, use
 928          * what the bootloader set things up as
 929          */
 930         physical_mem_end = 0;
 931         parse_cmdline_early(&command_line[0]);
 932
 933         if (_ramend == 0)
 934                 _ramend = get_mem_size() * 1024 * 1024;
 935
 936         if (physical_mem_end == 0)
 937                 physical_mem_end = _ramend;
 938
 939         memory_setup();
 940
 941 #ifndef CONFIG_BF60x
 942         /* Initialize Async memory banks */
 943         bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
 944         bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
 945         bfin_write_EBIU_AMGCTL(AMGCTLVAL);
 946 #ifdef CONFIG_EBIU_MBSCTLVAL
 947         bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
 948         bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
 949         bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
 950 #endif
 951 #endif
 952 #ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
 953         bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
 954         bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
 955         bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15);
 956         bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() &
 957                                         ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
 958 #endif
 959
 960 #ifdef CONFIG_BF60x
 961         clk = clk_get(NULL, "CCLK");
 962         if (!IS_ERR(clk)) {
 963                 cclk = clk_get_rate(clk);
 964                 clk_put(clk);
 965         } else
 966                 cclk = 0;
 967
 968         clk = clk_get(NULL, "SCLK0");
 969         if (!IS_ERR(clk)) {
 970                 sclk = clk_get_rate(clk);
 971                 clk_put(clk);
 972         } else
 973                 sclk = 0;
 974 #else
 975         cclk = get_cclk();
 976         sclk = get_sclk();
 977 #endif
 978
 979         if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
 980                 panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
 981
 982 #ifdef BF561_FAMILY
 983         if (ANOMALY_05000266) {
 984                 bfin_read_IMDMA_D0_IRQ_STATUS();
 985                 bfin_read_IMDMA_D1_IRQ_STATUS();
 986         }
 987 #endif
 988
 989         mmr = bfin_read_TBUFCTL();
 990         printk(KERN_INFO "Hardware Trace %s and %sabled\n",
 991                 (mmr & 0x1) ? "active" : "off",
 992                 (mmr & 0x2) ? "en" : "dis");
 993 #ifndef CONFIG_BF60x
 994         mmr = bfin_read_SYSCR();
 995         printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
 996
 997         /* Newer parts mirror SWRST bits in SYSCR */
 998 #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
 999     defined(CONFIG_BF538) || defined(CONFIG_BF539)
1000         _bfin_swrst = bfin_read_SWRST();
1001 #else
1002         /* Clear boot mode field */
1003         _bfin_swrst = mmr & ~0xf;
1004 #endif
1005
1006 #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
1007         bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
1008 #endif
1009 #ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
1010         bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
1011 #endif
1012
1013 #ifdef CONFIG_SMP
1014         if (_bfin_swrst & SWRST_DBL_FAULT_A) {
1015 #else
1016         if (_bfin_swrst & RESET_DOUBLE) {
1017 #endif
1018                 printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
1019 #ifdef CONFIG_DEBUG_DOUBLEFAULT
1020                 /* We assume the crashing kernel, and the current symbol table match */
1021                 printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
1022                         initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE,
1023                         initial_pda.retx_doublefault);
1024                 printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n",
1025                         initial_pda.dcplb_doublefault_addr);
1026                 printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n",
1027                         initial_pda.icplb_doublefault_addr);
1028 #endif
1029                 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
1030                         initial_pda.retx);
1031         } else if (_bfin_swrst & RESET_WDOG)
1032                 printk(KERN_INFO "Recovering from Watchdog event\n");
1033         else if (_bfin_swrst & RESET_SOFTWARE)
1034                 printk(KERN_NOTICE "Reset caused by Software reset\n");
1035 #endif
1036         printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
1037         if (bfin_compiled_revid() == 0xffff)
1038                 printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
1039         else if (bfin_compiled_revid() == -1)
1040                 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
1041         else
1042                 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
1043
1044         if (likely(CPUID == bfin_cpuid())) {
1045                 if (bfin_revid() != bfin_compiled_revid()) {
1046                         if (bfin_compiled_revid() == -1)
1047                                 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
1048                                        bfin_revid());
1049                         else if (bfin_compiled_revid() != 0xffff) {
1050                                 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
1051                                        bfin_compiled_revid(), bfin_revid());
1052                                 if (bfin_compiled_revid() > bfin_revid())
1053                                         panic("Error: you are missing anomaly workarounds for this rev");
1054                         }
1055                 }
1056                 if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
1057                         printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
1058                                CPU, bfin_revid());
1059         }
1060
1061         printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
1062
1063         printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
1064                cclk / 1000000, sclk / 1000000);
1065
1066         setup_bootmem_allocator();
1067
1068         paging_init();
1069
1070         /* Copy atomic sequences to their fixed location, and sanity check that
1071            these locations are the ones that we advertise to userspace.  */
1072         memcpy((void *)FIXED_CODE_START, &fixed_code_start,
1073                FIXED_CODE_END - FIXED_CODE_START);
1074         BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
1075                != SIGRETURN_STUB - FIXED_CODE_START);
1076         BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
1077                != ATOMIC_XCHG32 - FIXED_CODE_START);
1078         BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
1079                != ATOMIC_CAS32 - FIXED_CODE_START);
1080         BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
1081                != ATOMIC_ADD32 - FIXED_CODE_START);
1082         BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
1083                != ATOMIC_SUB32 - FIXED_CODE_START);
1084         BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
1085                != ATOMIC_IOR32 - FIXED_CODE_START);
1086         BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
1087                != ATOMIC_AND32 - FIXED_CODE_START);
1088         BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
1089                != ATOMIC_XOR32 - FIXED_CODE_START);
1090         BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
1091                 != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
1092
1093 #ifdef CONFIG_SMP
1094         platform_init_cpus();
1095 #endif
1096         init_exception_vectors();
1097         bfin_cache_init();      /* Initialize caches for the boot CPU */
1098 }
1099
1100 static int __init topology_init(void)
1101 {
1102         unsigned int cpu;
1103
1104         for_each_possible_cpu(cpu) {
1105                 register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
1106         }
1107
1108         return 0;
1109 }
1110
1111 subsys_initcall(topology_init);
1112
1113 /* Get the input clock frequency */
1114 static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
1115 #ifndef CONFIG_BF60x
1116 static u_long get_clkin_hz(void)
1117 {
1118         return cached_clkin_hz;
1119 }
1120 #endif
1121 static int __init early_init_clkin_hz(char *buf)
1122 {
1123         cached_clkin_hz = simple_strtoul(buf, NULL, 0);
1124 #ifdef BFIN_KERNEL_CLOCK
1125         if (cached_clkin_hz != CONFIG_CLKIN_HZ)
1126                 panic("cannot change clkin_hz when reprogramming clocks");
1127 #endif
1128         return 1;
1129 }
1130 early_param("clkin_hz=", early_init_clkin_hz);
1131
1132 #ifndef CONFIG_BF60x
1133 /* Get the voltage input multiplier */
1134 static u_long get_vco(void)
1135 {
1136         static u_long cached_vco;
1137         u_long msel, pll_ctl;
1138
1139         /* The assumption here is that VCO never changes at runtime.
1140          * If, someday, we support that, then we'll have to change this.
1141          */
1142         if (cached_vco)
1143                 return cached_vco;
1144
1145         pll_ctl = bfin_read_PLL_CTL();
1146         msel = (pll_ctl >> 9) & 0x3F;
1147         if (0 == msel)
1148                 msel = 64;
1149
1150         cached_vco = get_clkin_hz();
1151         cached_vco >>= (1 & pll_ctl);   /* DF bit */
1152         cached_vco *= msel;
1153         return cached_vco;
1154 }
1155 #endif
1156
1157 /* Get the Core clock */
1158 u_long get_cclk(void)
1159 {
1160 #ifdef CONFIG_BF60x
1161         struct clk *cclk;
1162         u_long cclk_rate;
1163
1164         cclk = clk_get(NULL, "CCLK");
1165         if (IS_ERR(cclk))
1166                 return 0;
1167
1168         cclk_rate = clk_get_rate(cclk);
1169         clk_put(cclk);
1170         return cclk_rate;
1171 #else
1172         static u_long cached_cclk_pll_div, cached_cclk;
1173         u_long csel, ssel;
1174
1175         if (bfin_read_PLL_STAT() & 0x1)
1176                 return get_clkin_hz();
1177
1178         ssel = bfin_read_PLL_DIV();
1179         if (ssel == cached_cclk_pll_div)
1180                 return cached_cclk;
1181         else
1182                 cached_cclk_pll_div = ssel;
1183
1184         csel = ((ssel >> 4) & 0x03);
1185         ssel &= 0xf;
1186         if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
1187                 cached_cclk = get_vco() / ssel;
1188         else
1189                 cached_cclk = get_vco() >> csel;
1190         return cached_cclk;
1191 #endif
1192 }
1193 EXPORT_SYMBOL(get_cclk);
1194
1195 #ifdef CONFIG_BF60x
1196 /* Get the bf60x clock of SCLK0 domain */
1197 u_long get_sclk0(void)
1198 {
1199         struct clk *sclk0;
1200         u_long sclk0_rate;
1201
1202         sclk0 = clk_get(NULL, "SCLK0");
1203         if (IS_ERR(sclk0))
1204                 return 0;
1205
1206         sclk0_rate = clk_get_rate(sclk0);
1207         clk_put(sclk0);
1208         return sclk0_rate;
1209 }
1210 EXPORT_SYMBOL(get_sclk0);
1211
1212 /* Get the bf60x clock of SCLK1 domain */
1213 u_long get_sclk1(void)
1214 {
1215         struct clk *sclk1;
1216         u_long sclk1_rate;
1217
1218         sclk1 = clk_get(NULL, "SCLK1");
1219         if (IS_ERR(sclk1))
1220                 return 0;
1221
1222         sclk1_rate = clk_get_rate(sclk1);
1223         clk_put(sclk1);
1224         return sclk1_rate;
1225 }
1226 EXPORT_SYMBOL(get_sclk1);
1227
1228 /* Get the bf60x DRAM clock */
1229 u_long get_dclk(void)
1230 {
1231         struct clk *dclk;
1232         u_long dclk_rate;
1233
1234         dclk = clk_get(NULL, "DCLK");
1235         if (IS_ERR(dclk))
1236                 return 0;
1237
1238         dclk_rate = clk_get_rate(dclk);
1239         clk_put(dclk);
1240         return dclk_rate;
1241 }
1242 EXPORT_SYMBOL(get_dclk);
1243 #endif
1244
1245 /* Get the System clock */
1246 u_long get_sclk(void)
1247 {
1248 #ifdef CONFIG_BF60x
1249         return get_sclk0();
1250 #else
1251         static u_long cached_sclk;
1252         u_long ssel;
1253
1254         /* The assumption here is that SCLK never changes at runtime.
1255          * If, someday, we support that, then we'll have to change this.
1256          */
1257         if (cached_sclk)
1258                 return cached_sclk;
1259
1260         if (bfin_read_PLL_STAT() & 0x1)
1261                 return get_clkin_hz();
1262
1263         ssel = bfin_read_PLL_DIV() & 0xf;
1264         if (0 == ssel) {
1265                 printk(KERN_WARNING "Invalid System Clock\n");
1266                 ssel = 1;
1267         }
1268
1269         cached_sclk = get_vco() / ssel;
1270         return cached_sclk;
1271 #endif
1272 }
1273 EXPORT_SYMBOL(get_sclk);
1274
1275 unsigned long sclk_to_usecs(unsigned long sclk)
1276 {
1277         u64 tmp = USEC_PER_SEC * (u64)sclk;
1278         do_div(tmp, get_sclk());
1279         return tmp;
1280 }
1281 EXPORT_SYMBOL(sclk_to_usecs);
1282
1283 unsigned long usecs_to_sclk(unsigned long usecs)
1284 {
1285         u64 tmp = get_sclk() * (u64)usecs;
1286         do_div(tmp, USEC_PER_SEC);
1287         return tmp;
1288 }
1289 EXPORT_SYMBOL(usecs_to_sclk);
1290
1291 /*
1292  *      Get CPU information for use by the procfs.
1293  */
1294 static int show_cpuinfo(struct seq_file *m, void *v)
1295 {
1296         char *cpu, *mmu, *fpu, *vendor, *cache;
1297         uint32_t revid;
1298         int cpu_num = *(unsigned int *)v;
1299         u_long sclk, cclk;
1300         u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
1301         struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
1302
1303         cpu = CPU;
1304         mmu = "none";
1305         fpu = "none";
1306         revid = bfin_revid();
1307
1308         sclk = get_sclk();
1309         cclk = get_cclk();
1310
1311         switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
1312         case 0xca:
1313                 vendor = "Analog Devices";
1314                 break;
1315         default:
1316                 vendor = "unknown";
1317                 break;
1318         }
1319
1320         seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
1321
1322         if (CPUID == bfin_cpuid())
1323                 seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
1324         else
1325                 seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
1326                         CPUID, bfin_cpuid());
1327
1328         seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
1329                 "stepping\t: %d ",
1330                 cpu, cclk/1000000, sclk/1000000,
1331 #ifdef CONFIG_MPU
1332                 "mpu on",
1333 #else
1334                 "mpu off",
1335 #endif
1336                 revid);
1337
1338         if (bfin_revid() != bfin_compiled_revid()) {
1339                 if (bfin_compiled_revid() == -1)
1340                         seq_printf(m, "(Compiled for Rev none)");
1341                 else if (bfin_compiled_revid() == 0xffff)
1342                         seq_printf(m, "(Compiled for Rev any)");
1343                 else
1344                         seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
1345         }
1346
1347         seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
1348                 cclk/1000000, cclk%1000000,
1349                 sclk/1000000, sclk%1000000);
1350         seq_printf(m, "bogomips\t: %lu.%02lu\n"
1351                 "Calibration\t: %lu loops\n",
1352                 (loops_per_jiffy * HZ) / 500000,
1353                 ((loops_per_jiffy * HZ) / 5000) % 100,
1354                 (loops_per_jiffy * HZ));
1355
1356         /* Check Cache configutation */
1357         switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
1358         case ACACHE_BSRAM:
1359                 cache = "dbank-A/B\t: cache/sram";
1360                 dcache_size = 16;
1361                 dsup_banks = 1;
1362                 break;
1363         case ACACHE_BCACHE:
1364                 cache = "dbank-A/B\t: cache/cache";
1365                 dcache_size = 32;
1366                 dsup_banks = 2;
1367                 break;
1368         case ASRAM_BSRAM:
1369                 cache = "dbank-A/B\t: sram/sram";
1370                 dcache_size = 0;
1371                 dsup_banks = 0;
1372                 break;
1373         default:
1374                 cache = "unknown";
1375                 dcache_size = 0;
1376                 dsup_banks = 0;
1377                 break;
1378         }
1379
1380         /* Is it turned on? */
1381         if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
1382                 dcache_size = 0;
1383
1384         if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
1385                 icache_size = 0;
1386
1387         seq_printf(m, "cache size\t: %d KB(L1 icache) "
1388                 "%d KB(L1 dcache) %d KB(L2 cache)\n",
1389                 icache_size, dcache_size, 0);
1390         seq_printf(m, "%s\n", cache);
1391         seq_printf(m, "external memory\t: "
1392 #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
1393                    "cacheable"
1394 #else
1395                    "uncacheable"
1396 #endif
1397                    " in instruction cache\n");
1398         seq_printf(m, "external memory\t: "
1399 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
1400                       "cacheable (write-back)"
1401 #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
1402                       "cacheable (write-through)"
1403 #else
1404                       "uncacheable"
1405 #endif
1406                       " in data cache\n");
1407
1408         if (icache_size)
1409                 seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
1410                            BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
1411         else
1412                 seq_printf(m, "icache setup\t: off\n");
1413
1414         seq_printf(m,
1415                    "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
1416                    dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
1417                    BFIN_DLINES);
1418 #ifdef __ARCH_SYNC_CORE_DCACHE
1419         seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]);
1420 #endif
1421 #ifdef __ARCH_SYNC_CORE_ICACHE
1422         seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]);
1423 #endif
1424
1425         seq_printf(m, "\n");
1426
1427         if (cpu_num != num_possible_cpus() - 1)
1428                 return 0;
1429
1430         if (L2_LENGTH) {
1431                 seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
1432                 seq_printf(m, "L2 SRAM\t\t: "
1433 #if defined(CONFIG_BFIN_L2_ICACHEABLE)
1434                               "cacheable"
1435 #else
1436                               "uncacheable"
1437 #endif
1438                               " in instruction cache\n");
1439                 seq_printf(m, "L2 SRAM\t\t: "
1440 #if defined(CONFIG_BFIN_L2_WRITEBACK)
1441                               "cacheable (write-back)"
1442 #elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
1443                               "cacheable (write-through)"
1444 #else
1445                               "uncacheable"
1446 #endif
1447                               " in data cache\n");
1448         }
1449         seq_printf(m, "board name\t: %s\n", bfin_board_name);
1450         seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
1451                 physical_mem_end >> 10, 0ul, physical_mem_end);
1452         seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
1453                 ((int)memory_end - (int)_rambase) >> 10,
1454                 _rambase, memory_end);
1455
1456         return 0;
1457 }
1458
1459 static void *c_start(struct seq_file *m, loff_t *pos)
1460 {
1461         if (*pos == 0)
1462                 *pos = cpumask_first(cpu_online_mask);
1463         if (*pos >= num_online_cpus())
1464                 return NULL;
1465
1466         return pos;
1467 }
1468
1469 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1470 {
1471         *pos = cpumask_next(*pos, cpu_online_mask);
1472
1473         return c_start(m, pos);
1474 }
1475
1476 static void c_stop(struct seq_file *m, void *v)
1477 {
1478 }
1479
1480 const struct seq_operations cpuinfo_op = {
1481         .start = c_start,
1482         .next = c_next,
1483         .stop = c_stop,
1484         .show = show_cpuinfo,
1485 };
1486
1487 void __init cmdline_init(const char *r0)
1488 {
1489         early_shadow_stamp();
1490         if (r0)
1491                 strncpy(command_line, r0, COMMAND_LINE_SIZE);
1492 }