2 * Based on arm clockevents implementation and old bfin time tick.
4 * Copyright 2008-2009 Analog Devics Inc.
8 * Licensed under the GPL-2
11 #include <linux/module.h>
12 #include <linux/profile.h>
13 #include <linux/interrupt.h>
14 #include <linux/time.h>
15 #include <linux/timex.h>
16 #include <linux/irq.h>
17 #include <linux/clocksource.h>
18 #include <linux/clockchips.h>
19 #include <linux/cpufreq.h>
21 #include <asm/blackfin.h>
23 #include <asm/gptimers.h>
25 /* Accelerators for sched_clock()
26 * convert from cycles(64bits) => nanoseconds (64bits)
28 * ns = cycles / (freq / ns_per_sec)
29 * ns = cycles * (ns_per_sec / freq)
30 * ns = cycles * (10^9 / (cpu_khz * 10^3))
31 * ns = cycles * (10^6 / cpu_khz)
33 * Then we use scaling math (suggested by george@mvista.com) to get:
34 * ns = cycles * (10^6 * SC / cpu_khz) / SC
35 * ns = cycles * cyc2ns_scale / SC
37 * And since SC is a constant power of two, we can convert the div
40 * We can use khz divisor instead of mhz to keep a better precision, since
41 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
42 * (mathieu.desnoyers@polymtl.ca)
44 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
47 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
49 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
51 static notrace cycle_t bfin_read_cycles(struct clocksource *cs)
53 return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
56 static struct clocksource bfin_cs_cycles = {
57 .name = "bfin_cs_cycles",
59 .read = bfin_read_cycles,
60 .mask = CLOCKSOURCE_MASK(64),
61 .shift = CYC2NS_SCALE_FACTOR,
62 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
65 static inline unsigned long long bfin_cs_cycles_sched_clock(void)
67 return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
68 bfin_cs_cycles.mult, bfin_cs_cycles.shift);
71 static int __init bfin_cs_cycles_init(void)
73 bfin_cs_cycles.mult = \
74 clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift);
76 if (clocksource_register(&bfin_cs_cycles))
77 panic("failed to register clocksource");
82 # define bfin_cs_cycles_init()
85 #ifdef CONFIG_GPTMR0_CLOCKSOURCE
87 void __init setup_gptimer0(void)
89 disable_gptimers(TIMER0bit);
91 set_gptimer_config(TIMER0_id, \
92 TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
93 set_gptimer_period(TIMER0_id, -1);
94 set_gptimer_pwidth(TIMER0_id, -2);
96 enable_gptimers(TIMER0bit);
99 static cycle_t bfin_read_gptimer0(struct clocksource *cs)
101 return bfin_read_TIMER0_COUNTER();
104 static struct clocksource bfin_cs_gptimer0 = {
105 .name = "bfin_cs_gptimer0",
107 .read = bfin_read_gptimer0,
108 .mask = CLOCKSOURCE_MASK(32),
109 .shift = CYC2NS_SCALE_FACTOR,
110 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
113 static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
115 return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
116 bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
119 static int __init bfin_cs_gptimer0_init(void)
123 bfin_cs_gptimer0.mult = \
124 clocksource_hz2mult(get_sclk(), bfin_cs_gptimer0.shift);
126 if (clocksource_register(&bfin_cs_gptimer0))
127 panic("failed to register clocksource");
132 # define bfin_cs_gptimer0_init()
136 #if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
137 /* prefer to use cycles since it has higher rating */
138 notrace unsigned long long sched_clock(void)
140 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
141 return bfin_cs_cycles_sched_clock();
143 return bfin_cs_gptimer0_sched_clock();
148 #ifdef CONFIG_CORE_TIMER_IRQ_L1
149 __attribute__((l1_text))
151 irqreturn_t timer_interrupt(int irq, void *dev_id);
153 static int bfin_timer_set_next_event(unsigned long, \
154 struct clock_event_device *);
156 static void bfin_timer_set_mode(enum clock_event_mode, \
157 struct clock_event_device *);
159 static struct clock_event_device clockevent_bfin = {
160 #if defined(CONFIG_TICKSOURCE_GPTMR0)
161 .name = "bfin_gptimer0",
165 .name = "bfin_core_timer",
170 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
171 .set_next_event = bfin_timer_set_next_event,
172 .set_mode = bfin_timer_set_mode,
175 static struct irqaction bfin_timer_irq = {
176 #if defined(CONFIG_TICKSOURCE_GPTMR0)
177 .name = "Blackfin GPTimer0",
179 .name = "Blackfin CoreTimer",
181 .flags = IRQF_DISABLED | IRQF_TIMER | \
182 IRQF_IRQPOLL | IRQF_PERCPU,
183 .handler = timer_interrupt,
184 .dev_id = &clockevent_bfin,
187 #if defined(CONFIG_TICKSOURCE_GPTMR0)
188 static int bfin_timer_set_next_event(unsigned long cycles,
189 struct clock_event_device *evt)
191 disable_gptimers(TIMER0bit);
193 /* it starts counting three SCLK cycles after the TIMENx bit is set */
194 set_gptimer_pwidth(TIMER0_id, cycles - 3);
195 enable_gptimers(TIMER0bit);
199 static void bfin_timer_set_mode(enum clock_event_mode mode,
200 struct clock_event_device *evt)
203 case CLOCK_EVT_MODE_PERIODIC: {
204 set_gptimer_config(TIMER0_id, \
205 TIMER_OUT_DIS | TIMER_IRQ_ENA | \
206 TIMER_PERIOD_CNT | TIMER_MODE_PWM);
207 set_gptimer_period(TIMER0_id, get_sclk() / HZ);
208 set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
209 enable_gptimers(TIMER0bit);
212 case CLOCK_EVT_MODE_ONESHOT:
213 disable_gptimers(TIMER0bit);
214 set_gptimer_config(TIMER0_id, \
215 TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
216 set_gptimer_period(TIMER0_id, 0);
218 case CLOCK_EVT_MODE_UNUSED:
219 case CLOCK_EVT_MODE_SHUTDOWN:
220 disable_gptimers(TIMER0bit);
222 case CLOCK_EVT_MODE_RESUME:
227 static void bfin_timer_ack(void)
229 set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0);
232 static void __init bfin_timer_init(void)
234 disable_gptimers(TIMER0bit);
237 static unsigned long __init bfin_clockevent_check(void)
239 setup_irq(IRQ_TIMER0, &bfin_timer_irq);
243 #else /* CONFIG_TICKSOURCE_CORETMR */
245 static int bfin_timer_set_next_event(unsigned long cycles,
246 struct clock_event_device *evt)
248 bfin_write_TCNTL(TMPWR);
250 bfin_write_TCOUNT(cycles);
252 bfin_write_TCNTL(TMPWR | TMREN);
256 static void bfin_timer_set_mode(enum clock_event_mode mode,
257 struct clock_event_device *evt)
260 case CLOCK_EVT_MODE_PERIODIC: {
261 unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
262 bfin_write_TCNTL(TMPWR);
264 bfin_write_TSCALE(TIME_SCALE - 1);
265 bfin_write_TPERIOD(tcount);
266 bfin_write_TCOUNT(tcount);
268 bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
271 case CLOCK_EVT_MODE_ONESHOT:
272 bfin_write_TCNTL(TMPWR);
274 bfin_write_TSCALE(TIME_SCALE - 1);
275 bfin_write_TPERIOD(0);
276 bfin_write_TCOUNT(0);
278 case CLOCK_EVT_MODE_UNUSED:
279 case CLOCK_EVT_MODE_SHUTDOWN:
283 case CLOCK_EVT_MODE_RESUME:
288 static void bfin_timer_ack(void)
292 static void __init bfin_timer_init(void)
294 /* power up the timer, but don't enable it just yet */
295 bfin_write_TCNTL(TMPWR);
299 * the TSCALE prescaler counter.
301 bfin_write_TSCALE(TIME_SCALE - 1);
302 bfin_write_TPERIOD(0);
303 bfin_write_TCOUNT(0);
308 static unsigned long __init bfin_clockevent_check(void)
310 setup_irq(IRQ_CORETMR, &bfin_timer_irq);
311 return get_cclk() / TIME_SCALE;
314 void __init setup_core_timer(void)
317 bfin_timer_set_mode(CLOCK_EVT_MODE_PERIODIC, NULL);
319 #endif /* CONFIG_TICKSOURCE_GPTMR0 */
322 * timer_interrupt() needs to keep up the real-time clock,
323 * as well as call the "do_timer()" routine every clocktick
325 irqreturn_t timer_interrupt(int irq, void *dev_id)
327 struct clock_event_device *evt = dev_id;
329 evt->event_handler(evt);
334 static int __init bfin_clockevent_init(void)
336 unsigned long timer_clk;
338 timer_clk = bfin_clockevent_check();
342 clockevent_bfin.mult = div_sc(timer_clk, NSEC_PER_SEC, clockevent_bfin.shift);
343 clockevent_bfin.max_delta_ns = clockevent_delta2ns(-1, &clockevent_bfin);
344 clockevent_bfin.min_delta_ns = clockevent_delta2ns(100, &clockevent_bfin);
345 clockevent_bfin.cpumask = cpumask_of(0);
346 clockevents_register_device(&clockevent_bfin);
351 void __init time_init(void)
353 time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
355 #ifdef CONFIG_RTC_DRV_BFIN
356 /* [#2663] hack to filter junk RTC values that would cause
357 * userspace to have to deal with time values greater than
358 * 2^31 seconds (which uClibc cannot cope with yet)
360 if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
361 printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
362 bfin_write_RTC_STAT(0);
366 /* Initialize xtime. From now on, xtime is updated with timer interrupts */
367 xtime.tv_sec = secs_since_1970;
369 set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
371 bfin_cs_cycles_init();
372 bfin_cs_gptimer0_init();
373 bfin_clockevent_init();