2 * This is the configuration for SSV Dil/NetPC DNP/5370 board.
4 * DIL module: http://www.dilnetpc.com/dnp0086.htm
5 * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
7 * Copyright 2010 3ality Digital Systems
8 * Copyright 2005 National ICT Australia (NICTA)
9 * Copyright 2004-2006 Analog Devices Inc.
11 * Licensed under the GPL-2 or later.
14 #include <linux/device.h>
15 #include <linux/kernel.h>
16 #include <linux/platform_device.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/mtd/plat-ram.h>
22 #include <linux/mtd/physmap.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spi/flash.h>
25 #include <linux/irq.h>
26 #include <linux/interrupt.h>
27 #include <linux/i2c.h>
28 #include <linux/spi/mmc_spi.h>
29 #include <linux/phy.h>
31 #include <asm/bfin5xx_spi.h>
32 #include <asm/reboot.h>
33 #include <asm/portmux.h>
37 * Name the Board for the /proc/cpuinfo
39 const char bfin_board_name[] = "DNP/5370";
40 #define FLASH_MAC 0x202f0000
41 #define CONFIG_MTD_PHYSMAP_LEN 0x300000
43 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
44 static struct platform_device rtc_device = {
50 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
51 #include <linux/bfin_mac.h>
52 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
54 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
57 .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
61 static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
63 .phydev_data = bfin_phydev_data,
64 .phy_mode = PHY_INTERFACE_MODE_RMII,
65 .mac_peripherals = bfin_mac_peripherals,
68 static struct platform_device bfin_mii_bus = {
69 .name = "bfin_mii_bus",
71 .platform_data = &bfin_mii_bus_data,
75 static struct platform_device bfin_mac_device = {
78 .platform_data = &bfin_mii_bus,
83 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
84 static struct mtd_partition asmb_flash_partitions[] = {
86 .name = "bootloader(nor)",
90 .name = "linux kernel and rootfs(nor)",
91 .size = 0x300000 - 0x30000 - 0x10000,
92 .offset = MTDPART_OFS_APPEND,
94 .name = "MAC address(nor)",
96 .offset = MTDPART_OFS_APPEND,
97 .mask_flags = MTD_WRITEABLE,
101 static struct physmap_flash_data asmb_flash_data = {
103 .parts = asmb_flash_partitions,
104 .nr_parts = ARRAY_SIZE(asmb_flash_partitions),
107 static struct resource asmb_flash_resource = {
110 .flags = IORESOURCE_MEM,
113 /* 4 MB NOR flash attached to async memory banks 0-2,
114 * therefore only 3 MB visible.
116 static struct platform_device asmb_flash_device = {
117 .name = "physmap-flash",
120 .platform_data = &asmb_flash_data,
123 .resource = &asmb_flash_resource,
127 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
129 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
131 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
132 .enable_dma = 0, /* use no dma transfer with this chip*/
137 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
138 /* This mapping is for at45db642 it has 1056 page size,
139 * partition size and offset should be page aligned
141 static struct mtd_partition bfin_spi_dataflash_partitions[] = {
143 .name = "JFFS2 dataflash(nor)",
144 #ifdef CONFIG_MTD_PAGESIZE_1024
154 static struct flash_platform_data bfin_spi_dataflash_data = {
155 .name = "mtd_dataflash",
156 .parts = bfin_spi_dataflash_partitions,
157 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
158 .type = "mtd_dataflash",
161 static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
162 .enable_dma = 0, /* use no dma transfer with this chip*/
166 static struct spi_board_info bfin_spi_board_info[] __initdata = {
167 /* SD/MMC card reader at SPI bus */
168 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
170 .modalias = "mmc_spi",
171 .max_speed_hz = 20000000,
174 .controller_data = &mmc_spi_chip_info,
179 /* 8 Megabyte Atmel NOR flash chip at SPI bus */
180 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
182 .modalias = "mtd_dataflash",
183 .max_speed_hz = 16700000,
186 .platform_data = &bfin_spi_dataflash_data,
187 .controller_data = &spi_dataflash_chip_info,
188 .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
193 /* SPI controller data */
195 static struct resource bfin_spi0_resource[] = {
197 .start = SPI0_REGBASE,
198 .end = SPI0_REGBASE + 0xFF,
199 .flags = IORESOURCE_MEM,
204 .flags = IORESOURCE_DMA,
209 .flags = IORESOURCE_IRQ,
213 static struct bfin5xx_spi_master spi_bfin_master_info = {
215 .enable_dma = 1, /* master has the ability to do dma transfer */
216 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
219 static struct platform_device spi_bfin_master_device = {
221 .id = 0, /* Bus number */
222 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
223 .resource = bfin_spi0_resource,
225 .platform_data = &spi_bfin_master_info, /* Passed to driver */
230 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
231 #ifdef CONFIG_SERIAL_BFIN_UART0
232 static struct resource bfin_uart0_resources[] = {
236 .flags = IORESOURCE_MEM,
239 .start = IRQ_UART0_RX,
240 .end = IRQ_UART0_RX+1,
241 .flags = IORESOURCE_IRQ,
244 .start = IRQ_UART0_ERROR,
245 .end = IRQ_UART0_ERROR,
246 .flags = IORESOURCE_IRQ,
249 .start = CH_UART0_TX,
251 .flags = IORESOURCE_DMA,
254 .start = CH_UART0_RX,
256 .flags = IORESOURCE_DMA,
260 static unsigned short bfin_uart0_peripherals[] = {
261 P_UART0_TX, P_UART0_RX, 0
264 static struct platform_device bfin_uart0_device = {
267 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
268 .resource = bfin_uart0_resources,
270 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
275 #ifdef CONFIG_SERIAL_BFIN_UART1
276 static struct resource bfin_uart1_resources[] = {
280 .flags = IORESOURCE_MEM,
283 .start = IRQ_UART1_RX,
284 .end = IRQ_UART1_RX+1,
285 .flags = IORESOURCE_IRQ,
288 .start = IRQ_UART1_ERROR,
289 .end = IRQ_UART1_ERROR,
290 .flags = IORESOURCE_IRQ,
293 .start = CH_UART1_TX,
295 .flags = IORESOURCE_DMA,
298 .start = CH_UART1_RX,
300 .flags = IORESOURCE_DMA,
304 static unsigned short bfin_uart1_peripherals[] = {
305 P_UART1_TX, P_UART1_RX, 0
308 static struct platform_device bfin_uart1_device = {
311 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
312 .resource = bfin_uart1_resources,
314 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
320 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
321 static struct resource bfin_twi0_resource[] = {
323 .start = TWI0_REGBASE,
324 .end = TWI0_REGBASE + 0xff,
325 .flags = IORESOURCE_MEM,
330 .flags = IORESOURCE_IRQ,
334 static struct platform_device i2c_bfin_twi_device = {
335 .name = "i2c-bfin-twi",
337 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
338 .resource = bfin_twi0_resource,
342 static struct platform_device *dnp5370_devices[] __initdata = {
344 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
345 #ifdef CONFIG_SERIAL_BFIN_UART0
348 #ifdef CONFIG_SERIAL_BFIN_UART1
353 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
357 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
362 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
363 &spi_bfin_master_device,
366 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
367 &i2c_bfin_twi_device,
370 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
376 static int __init dnp5370_init(void)
378 printk(KERN_INFO "DNP/5370: registering device resources\n");
379 platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
380 printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
381 ARRAY_SIZE(bfin_spi_board_info));
382 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
383 printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
386 arch_initcall(dnp5370_init);
389 * Currently the MAC address is saved in Flash by U-Boot
391 void bfin_get_ether_addr(char *addr)
393 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
394 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
396 EXPORT_SYMBOL(bfin_get_ether_addr);