2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Cambridge Signal Processing
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
7 * Licensed under the GPL-2 or later.
10 #include <linux/device.h>
11 #include <linux/platform_device.h>
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/partitions.h>
14 #include <linux/spi/spi.h>
15 #include <linux/spi/flash.h>
16 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
17 #include <linux/usb/isp1362.h>
19 #include <linux/ata_platform.h>
20 #include <linux/irq.h>
21 #include <linux/interrupt.h>
22 #include <linux/usb/sl811.h>
24 #include <asm/bfin5xx_spi.h>
25 #include <asm/reboot.h>
26 #include <asm/portmux.h>
27 #include <linux/spi/ad7877.h>
30 * Name the Board for the /proc/cpuinfo
32 const char bfin_board_name[] = "CamSig Minotaur BF537";
34 #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
35 static struct resource bfin_pcmcia_cf_resources[] = {
37 .start = 0x20310000, /* IO PORT */
39 .flags = IORESOURCE_MEM,
41 .start = 0x20311000, /* Attribute Memory */
43 .flags = IORESOURCE_MEM,
47 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
49 .start = IRQ_PF6, /* Card Detect PF6 */
51 .flags = IORESOURCE_IRQ,
55 static struct platform_device bfin_pcmcia_cf_device = {
56 .name = "bfin_cf_pcmcia",
58 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
59 .resource = bfin_pcmcia_cf_resources,
63 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
64 static struct platform_device rtc_device = {
70 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
71 #include <linux/bfin_mac.h>
72 static const unsigned short bfin_mac_peripherals[] = P_MII0;
74 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
77 .irq = IRQ_MAC_PHYINT,
81 static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
83 .phydev_data = bfin_phydev_data,
84 .phy_mode = PHY_INTERFACE_MODE_MII,
85 .mac_peripherals = bfin_mac_peripherals,
88 static struct platform_device bfin_mii_bus = {
89 .name = "bfin_mii_bus",
91 .platform_data = &bfin_mii_bus_data,
95 static struct platform_device bfin_mac_device = {
98 .platform_data = &bfin_mii_bus,
103 #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
104 static struct resource net2272_bfin_resources[] = {
107 .end = 0x20300000 + 0x100,
108 .flags = IORESOURCE_MEM,
112 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
116 static struct platform_device net2272_bfin_device = {
119 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
120 .resource = net2272_bfin_resources,
124 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
125 /* all SPI peripherals info goes here */
127 #if defined(CONFIG_MTD_M25P80) \
128 || defined(CONFIG_MTD_M25P80_MODULE)
130 /* Partition sizes */
131 #define FLASH_SIZE 0x00400000
132 #define PSIZE_UBOOT 0x00030000
133 #define PSIZE_INITRAMFS 0x00240000
135 static struct mtd_partition bfin_spi_flash_partitions[] = {
137 .name = "bootloader(spi)",
140 .mask_flags = MTD_CAP_ROM
142 .name = "initramfs(spi)",
143 .size = PSIZE_INITRAMFS,
144 .offset = PSIZE_UBOOT
147 .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS),
148 .offset = PSIZE_UBOOT + PSIZE_INITRAMFS,
152 static struct flash_platform_data bfin_spi_flash_data = {
154 .parts = bfin_spi_flash_partitions,
155 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
159 /* SPI flash chip (m25p64) */
160 static struct bfin5xx_spi_chip spi_flash_chip_info = {
161 .enable_dma = 0, /* use dma transfer with this chip*/
165 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
166 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
171 static struct spi_board_info bfin_spi_board_info[] __initdata = {
172 #if defined(CONFIG_MTD_M25P80) \
173 || defined(CONFIG_MTD_M25P80_MODULE)
175 /* the modalias must be the same as spi device driver name */
176 .modalias = "m25p80", /* Name of spi_driver for this device */
177 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
178 .bus_num = 0, /* Framework bus number */
179 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
180 .platform_data = &bfin_spi_flash_data,
181 .controller_data = &spi_flash_chip_info,
186 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
188 .modalias = "mmc_spi",
189 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
192 .controller_data = &mmc_spi_chip_info,
198 /* SPI controller data */
199 static struct bfin5xx_spi_master bfin_spi0_info = {
201 .enable_dma = 1, /* master has the ability to do dma transfer */
205 static struct resource bfin_spi0_resource[] = {
207 .start = SPI0_REGBASE,
208 .end = SPI0_REGBASE + 0xFF,
209 .flags = IORESOURCE_MEM,
214 .flags = IORESOURCE_DMA,
219 .flags = IORESOURCE_IRQ,
223 static struct platform_device bfin_spi0_device = {
225 .id = 0, /* Bus number */
226 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
227 .resource = bfin_spi0_resource,
229 .platform_data = &bfin_spi0_info, /* Passed to driver */
232 #endif /* spi master and devices */
234 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
235 #ifdef CONFIG_SERIAL_BFIN_UART0
236 static struct resource bfin_uart0_resources[] = {
240 .flags = IORESOURCE_MEM,
243 .start = IRQ_UART0_RX,
244 .end = IRQ_UART0_RX+1,
245 .flags = IORESOURCE_IRQ,
248 .start = IRQ_UART0_ERROR,
249 .end = IRQ_UART0_ERROR,
250 .flags = IORESOURCE_IRQ,
253 .start = CH_UART0_TX,
255 .flags = IORESOURCE_DMA,
258 .start = CH_UART0_RX,
260 .flags = IORESOURCE_DMA,
264 static unsigned short bfin_uart0_peripherals[] = {
265 P_UART0_TX, P_UART0_RX, 0
268 static struct platform_device bfin_uart0_device = {
271 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
272 .resource = bfin_uart0_resources,
274 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
278 #ifdef CONFIG_SERIAL_BFIN_UART1
279 static struct resource bfin_uart1_resources[] = {
283 .flags = IORESOURCE_MEM,
286 .start = IRQ_UART1_RX,
287 .end = IRQ_UART1_RX+1,
288 .flags = IORESOURCE_IRQ,
291 .start = IRQ_UART1_ERROR,
292 .end = IRQ_UART1_ERROR,
293 .flags = IORESOURCE_IRQ,
296 .start = CH_UART1_TX,
298 .flags = IORESOURCE_DMA,
301 .start = CH_UART1_RX,
303 .flags = IORESOURCE_DMA,
307 static unsigned short bfin_uart1_peripherals[] = {
308 P_UART1_TX, P_UART1_RX, 0
311 static struct platform_device bfin_uart1_device = {
314 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
315 .resource = bfin_uart1_resources,
317 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
323 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
324 #ifdef CONFIG_BFIN_SIR0
325 static struct resource bfin_sir0_resources[] = {
329 .flags = IORESOURCE_MEM,
332 .start = IRQ_UART0_RX,
333 .end = IRQ_UART0_RX+1,
334 .flags = IORESOURCE_IRQ,
337 .start = CH_UART0_RX,
338 .end = CH_UART0_RX+1,
339 .flags = IORESOURCE_DMA,
343 static struct platform_device bfin_sir0_device = {
346 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
347 .resource = bfin_sir0_resources,
350 #ifdef CONFIG_BFIN_SIR1
351 static struct resource bfin_sir1_resources[] = {
355 .flags = IORESOURCE_MEM,
358 .start = IRQ_UART1_RX,
359 .end = IRQ_UART1_RX+1,
360 .flags = IORESOURCE_IRQ,
363 .start = CH_UART1_RX,
364 .end = CH_UART1_RX+1,
365 .flags = IORESOURCE_DMA,
369 static struct platform_device bfin_sir1_device = {
372 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
373 .resource = bfin_sir1_resources,
378 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
379 static struct resource bfin_twi0_resource[] = {
381 .start = TWI0_REGBASE,
382 .end = TWI0_REGBASE + 0xFF,
383 .flags = IORESOURCE_MEM,
388 .flags = IORESOURCE_IRQ,
392 static struct platform_device i2c_bfin_twi_device = {
393 .name = "i2c-bfin-twi",
395 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
396 .resource = bfin_twi0_resource,
400 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
401 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
402 static struct resource bfin_sport0_uart_resources[] = {
404 .start = SPORT0_TCR1,
405 .end = SPORT0_MRCS3+4,
406 .flags = IORESOURCE_MEM,
409 .start = IRQ_SPORT0_RX,
410 .end = IRQ_SPORT0_RX+1,
411 .flags = IORESOURCE_IRQ,
414 .start = IRQ_SPORT0_ERROR,
415 .end = IRQ_SPORT0_ERROR,
416 .flags = IORESOURCE_IRQ,
420 static unsigned short bfin_sport0_peripherals[] = {
421 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
422 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
425 static struct platform_device bfin_sport0_uart_device = {
426 .name = "bfin-sport-uart",
428 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
429 .resource = bfin_sport0_uart_resources,
431 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
435 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
436 static struct resource bfin_sport1_uart_resources[] = {
438 .start = SPORT1_TCR1,
439 .end = SPORT1_MRCS3+4,
440 .flags = IORESOURCE_MEM,
443 .start = IRQ_SPORT1_RX,
444 .end = IRQ_SPORT1_RX+1,
445 .flags = IORESOURCE_IRQ,
448 .start = IRQ_SPORT1_ERROR,
449 .end = IRQ_SPORT1_ERROR,
450 .flags = IORESOURCE_IRQ,
454 static unsigned short bfin_sport1_peripherals[] = {
455 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
456 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
459 static struct platform_device bfin_sport1_uart_device = {
460 .name = "bfin-sport-uart",
462 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
463 .resource = bfin_sport1_uart_resources,
465 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
471 static struct platform_device *minotaur_devices[] __initdata = {
472 #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
473 &bfin_pcmcia_cf_device,
476 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
480 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
485 #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
486 &net2272_bfin_device,
489 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
493 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
494 #ifdef CONFIG_SERIAL_BFIN_UART0
497 #ifdef CONFIG_SERIAL_BFIN_UART1
502 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
503 #ifdef CONFIG_BFIN_SIR0
506 #ifdef CONFIG_BFIN_SIR1
511 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
512 &i2c_bfin_twi_device,
515 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
516 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
517 &bfin_sport0_uart_device,
519 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
520 &bfin_sport1_uart_device,
526 static int __init minotaur_init(void)
528 printk(KERN_INFO "%s(): registering device resources\n", __func__);
529 platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
530 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
531 spi_register_board_info(bfin_spi_board_info,
532 ARRAY_SIZE(bfin_spi_board_info));
538 arch_initcall(minotaur_init);
540 static struct platform_device *minotaur_early_devices[] __initdata = {
541 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
542 #ifdef CONFIG_SERIAL_BFIN_UART0
545 #ifdef CONFIG_SERIAL_BFIN_UART1
550 #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
551 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
552 &bfin_sport0_uart_device,
554 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
555 &bfin_sport1_uart_device,
560 void __init native_machine_early_platform_add_devices(void)
562 printk(KERN_INFO "register early platform devices\n");
563 early_platform_add_devices(minotaur_early_devices,
564 ARRAY_SIZE(minotaur_early_devices));
567 void native_machine_restart(char *cmd)
569 /* workaround reboot hang when booting from SPI */
570 if ((bfin_read_SYSCR() & 0x7) == 0x3)
571 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);