2 * File: arch/blackfin/mach-bf537/head.S
3 * Based on: arch/blackfin/mach-bf533/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
7 * Description: Startup code for Blackfin BF537
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/linkage.h>
31 #include <linux/init.h>
32 #include <asm/blackfin.h>
33 #include <asm/trace.h>
35 #if CONFIG_BFIN_KERNEL_CLOCK
36 #include <asm/mach/mem_init.h>
44 .extern _bf53x_relocate_l1_mem
46 #define INITIAL_STACK 0xFFB01000
51 /* R0: argument of command line string, passed from uboot, save it */
53 /* Set the SYSCFG register:
54 * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
60 /* Clear Out All the data and pointer Registers */
82 /* Clear Out All the DAG Registers */
98 trace_buffer_start(p0,r0);
102 /* Turn off the icache */
103 p0.l = (IMEM_CONTROL & 0xFFFF);
104 p0.h = (IMEM_CONTROL >> 16);
109 /* Anomaly 05000125 */
120 /* Turn off the dcache */
121 p0.l = (DMEM_CONTROL & 0xFFFF);
122 p0.h = (DMEM_CONTROL >> 16);
127 /* Anomaly 05000125 */
138 /* Initialise General-Purpose I/O Modules on BF537 */
139 /* Rev 0.0 Anomaly 05000212 - PORTx_FER,
140 * PORT_MUX Registers Do Not accept "writes" correctly:
142 p0.h = hi(BFIN_PORT_MUX);
143 p0.l = lo(BFIN_PORT_MUX);
145 R0.L = W[P0]; /* Read */
148 R0 = (PGDE_UART | PFTE_UART)(Z);
150 W[P0] = R0.L; /* Write */
153 W[P0] = R0.L; /* Enable both UARTS */
156 p0.h = hi(PORTF_FER);
157 p0.l = lo(PORTF_FER);
159 R0.L = W[P0]; /* Read */
164 W[P0] = R0.L; /* Write */
167 /* Enable peripheral function of PORTF for UART0 and UART1 */
171 #if !defined(CONFIG_BF534)
172 p0.h = hi(EMAC_SYSTAT);
173 p0.l = lo(EMAC_SYSTAT);
174 R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
180 #ifdef CONFIG_BF537_PORT_H
181 p0.h = hi(PORTH_FER);
182 p0.l = lo(PORTH_FER);
183 R0.L = W[P0]; /* Read */
186 W[P0] = R0.L; /* Write */
188 W[P0] = R0.L; /* Disable peripheral function of PORTH */
192 /* Initialise UART - when booting from u-boot, the UART is not disabled
193 * so if we dont initalize here, our serial console gets hosed */
197 w[p0] = r0.L; /* To enable DLL writes */
212 p0.h = hi(UART_GCTL);
213 p0.l = lo(UART_GCTL);
215 w[p0] = r0.L; /* To enable UART clock */
218 /* Initialize stack pointer */
219 sp.l = lo(INITIAL_STACK);
220 sp.h = hi(INITIAL_STACK);
224 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
225 call _bf53x_relocate_l1_mem;
226 #if CONFIG_BFIN_KERNEL_CLOCK
227 call _start_dma_code;
230 /* Code for initializing Async memory banks */
232 p2.h = hi(EBIU_AMBCTL1);
233 p2.l = lo(EBIU_AMBCTL1);
234 r0.h = hi(AMBCTL1VAL);
235 r0.l = lo(AMBCTL1VAL);
239 p2.h = hi(EBIU_AMBCTL0);
240 p2.l = lo(EBIU_AMBCTL0);
241 r0.h = hi(AMBCTL0VAL);
242 r0.l = lo(AMBCTL0VAL);
246 p2.h = hi(EBIU_AMGCTL);
247 p2.l = lo(EBIU_AMGCTL);
252 /* This section keeps the processor in supervisor mode
253 * during kernel boot. Switches to user mode at end of boot.
254 * See page 3-9 of Hardware Reference manual for documentation.
257 /* EVT15 = _real_start */
291 w[p0] = r0; /* watchdog off for now */
294 /* Code update for BSS size == 0
295 * Zero out the bss region.
304 lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
308 /* In case there is a NULL pointer reference
309 * Zero out region before stext
319 lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
323 /* pass the uboot arguments to the global value command line */
342 * load the current thread pointer and stack
344 r1.l = _init_thread_union;
345 r1.h = _init_thread_union;
353 jump.l _start_kernel;
359 #if CONFIG_BFIN_KERNEL_CLOCK
360 ENTRY(_start_dma_code)
362 /* Enable PHY CLK buffer output */
379 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
380 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
381 * - [7] = output delay (add 200ps of delay to mem signals)
382 * - [6] = input delay (add 200ps of input delay to mem signals)
383 * - [5] = PDWN : 1=All Clocks off
384 * - [3] = STOPCK : 1=Core Clock off
385 * - [1] = PLL_OFF : 1=Disable Power to PLL
386 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
387 * all other bits set to zero
390 p0.h = hi(PLL_LOCKCNT);
391 p0.l = lo(PLL_LOCKCNT);
396 P2.H = hi(EBIU_SDGCTL);
397 P2.L = lo(EBIU_SDGCTL);
403 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
404 r0 = r0 << 9; /* Shift it over, */
405 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
407 r1 = PLL_BYPASS; /* Bypass the PLL? */
408 r1 = r1 << 8; /* Shift it over */
409 r0 = r1 | r0; /* add them all together */
412 p0.l = lo(PLL_CTL); /* Load the address */
413 cli r2; /* Disable interrupts */
415 w[p0] = r0.l; /* Set the value */
416 idle; /* Wait for the PLL to stablize */
417 sti r2; /* Enable interrupts */
424 if ! CC jump .Lcheck_again;
426 /* Configure SCLK & CCLK Dividers */
427 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
433 p0.l = lo(EBIU_SDRRC);
434 p0.h = hi(EBIU_SDRRC);
439 p0.l = (EBIU_SDBCTL & 0xFFFF);
440 p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
445 P2.H = hi(EBIU_SDGCTL);
446 P2.L = lo(EBIU_SDGCTL);
449 p0.h = hi(EBIU_SDSTAT);
450 p0.l = lo(EBIU_SDSTAT);
460 R0.L = lo(mem_SDGCTL);
461 R0.H = hi(mem_SDGCTL);
469 r0.l = lo(IWR_ENABLE_ALL);
470 r0.h = hi(IWR_ENABLE_ALL);
475 ENDPROC(_start_dma_code)
476 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
479 /* No more interrupts to be handled*/
483 #if defined(CONFIG_MTD_M25P80)
485 * The following code fix the SPI flash reboot issue,
486 * /CS signal of the chip which is using PF10 return to GPIO mode
488 p0.h = hi(PORTF_FER);
489 p0.l = lo(PORTF_FER);
494 /* /CS return to high */
501 /* Delay some time, This is necessary */
505 lsetup (.L_delay_lab1, .L_delay_lab1_end) lc1 = p1;
510 lsetup (.L_delay_lab0, .L_delay_lab0_end) lc0 = p0;
519 /* Clear the IMASK register */
525 /* Clear the ILAT register */
532 /* make sure SYSCR is set to use BMODE */
539 /* issue a system soft reset */
546 /* clear system soft reset */
551 /* issue core reset */
560 * Set up the usable of RAM stuff. Size of RAM is determined then
561 * an initial stack set up at the end.