2 * BF561 coreB bootstrap file
4 * Copyright 2007-2009 Analog Devices Inc.
5 * Philippe Gerum <rpm@xenomai.org>
7 * Licensed under the GPL-2 or later.
10 #include <linux/linkage.h>
11 #include <linux/init.h>
12 #include <asm/blackfin.h>
13 #include <asm/asm-offsets.h>
14 #include <asm/trace.h>
18 /* Lay the initial stack into the L1 scratch area of Core B */
19 #define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
21 ENTRY(_coreb_trampoline_start)
22 /* Set the SYSCFG register */
24 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
27 /*Clear Out All the data and pointer Registers*/
50 /* Clear Out All the DAG Registers*/
66 trace_buffer_init(p0,r0);
68 /* Turn off the icache */
69 p0.l = LO(IMEM_CONTROL);
70 p0.h = HI(IMEM_CONTROL);
75 /* Disabling of CPLBs should be proceeded by a CSYNC */
80 /* Turn off the dcache */
81 p0.l = LO(DMEM_CONTROL);
82 p0.h = HI(DMEM_CONTROL);
87 /* Disabling of CPLBs should be proceeded by a CSYNC */
92 /* in case of double faults, save a few things */
93 p0.l = _init_retx_coreb;
94 p0.h = _init_retx_coreb;
98 #ifdef CONFIG_DEBUG_DOUBLEFAULT
99 /* Only save these if we are storing them,
100 * This happens here, since L1 gets clobbered
104 r7 = [p0 + PDA_DF_RETX];
105 p1.l = _init_saved_retx_coreb;
106 p1.h = _init_saved_retx_coreb;
109 r7 = [p0 + PDA_DF_DCPLB];
110 p1.l = _init_saved_dcplb_fault_addr_coreb;
111 p1.h = _init_saved_dcplb_fault_addr_coreb;
114 r7 = [p0 + PDA_DF_ICPLB];
115 p1.l = _init_saved_icplb_fault_addr_coreb;
116 p1.h = _init_saved_icplb_fault_addr_coreb;
119 r7 = [p0 + PDA_DF_SEQSTAT];
120 p1.l = _init_saved_seqstat_coreb;
121 p1.h = _init_saved_seqstat_coreb;
125 /* Initialize stack pointer */
126 sp.l = lo(INITIAL_STACK);
127 sp.h = hi(INITIAL_STACK);
131 /* This section keeps the processor in supervisor mode
132 * during core B startup. Branches to the idle task.
135 /* EVT15 = _real_start */
155 #if defined(ANOMALY_05000281)
162 ENDPROC(_coreb_trampoline_start)
163 ENTRY(_coreb_trampoline_end)
167 P0.H = hi(SICB_IWR0);
168 P0.L = lo(SICB_IWR0);
169 P1.H = hi(SICB_IWR1);
170 P1.L = lo(SICB_IWR1);
175 ENDPROC(_set_sicb_iwr)
178 sp.l = lo(INITIAL_STACK);
179 sp.h = hi(INITIAL_STACK);
190 R0 = IWR_DISABLE_ALL;
191 R1 = IWR_DISABLE_ALL;
194 p0.h = hi(COREB_L1_CODE_START);
195 p0.l = lo(COREB_L1_CODE_START);
197 ENDPROC(_coreb_sleep)
203 p0.l = lo(WDOGB_CTL);
204 p0.h = hi(WDOGB_CTL);
206 w[p0] = r0; /* Clear the watchdog. */
210 * switch to IDLE stack.
212 p0.l = _secondary_stack;
213 p0.h = _secondary_stack;
217 #ifdef CONFIG_HOTPLUG_CPU
218 p0.l = _hotplug_coreb;
219 p0.h = _hotplug_coreb;
227 #ifdef CONFIG_HOTPLUG_CPU
230 call _secondary_start_kernel;
233 ENDPROC(_coreb_start)