2 * File: arch/blackfin/mach-bf561/secondary.S
3 * Based on: arch/blackfin/mach-bf561/head.S
4 * Author: Philippe Gerum <rpm@xenomai.org>
6 * Copyright 2007 Analog Devices Inc.
8 * Description: BF561 coreB bootstrap file
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, see the file COPYING, or write
22 * to the Free Software Foundation, Inc.,
23 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 #include <linux/linkage.h>
27 #include <linux/init.h>
28 #include <asm/blackfin.h>
29 #include <asm/asm-offsets.h>
33 /* Lay the initial stack into the L1 scratch area of Core B */
34 #define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
36 ENTRY(_coreb_trampoline_start)
37 /* Set the SYSCFG register */
39 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
42 /*Clear Out All the data and pointer Registers*/
65 /* Clear Out All the DAG Registers*/
81 /* Turn off the icache */
82 p0.l = LO(IMEM_CONTROL);
83 p0.h = HI(IMEM_CONTROL);
88 /* Disabling of CPLBs should be proceeded by a CSYNC */
93 /* Turn off the dcache */
94 p0.l = LO(DMEM_CONTROL);
95 p0.h = HI(DMEM_CONTROL);
100 /* Disabling of CPLBs should be proceeded by a CSYNC */
105 /* in case of double faults, save a few things */
106 p0.l = _init_retx_coreb;
107 p0.h = _init_retx_coreb;
111 #ifdef CONFIG_DEBUG_DOUBLEFAULT
112 /* Only save these if we are storing them,
113 * This happens here, since L1 gets clobbered
117 r7 = [p0 + PDA_DF_RETX];
118 p1.l = _init_saved_retx_coreb;
119 p1.h = _init_saved_retx_coreb;
122 r7 = [p0 + PDA_DF_DCPLB];
123 p1.l = _init_saved_dcplb_fault_addr_coreb;
124 p1.h = _init_saved_dcplb_fault_addr_coreb;
127 r7 = [p0 + PDA_DF_ICPLB];
128 p1.l = _init_saved_icplb_fault_addr_coreb;
129 p1.h = _init_saved_icplb_fault_addr_coreb;
132 r7 = [p0 + PDA_DF_SEQSTAT];
133 p1.l = _init_saved_seqstat_coreb;
134 p1.h = _init_saved_seqstat_coreb;
138 /* Initialize stack pointer */
139 sp.l = lo(INITIAL_STACK);
140 sp.h = hi(INITIAL_STACK);
144 /* This section keeps the processor in supervisor mode
145 * during core B startup. Branches to the idle task.
148 /* EVT15 = _real_start */
168 #if defined(ANOMALY_05000281)
175 ENDPROC(_coreb_trampoline_start)
176 ENTRY(_coreb_trampoline_end)
181 p0.l = lo(WDOGB_CTL);
182 p0.h = hi(WDOGB_CTL);
184 w[p0] = r0; /* Clear the watchdog. */
188 * switch to IDLE stack.
190 p0.l = _secondary_stack;
191 p0.h = _secondary_stack;
198 call _secondary_start_kernel;
201 ENDPROC(_coreb_start)