2 * File: arch/blackfin/mach-bf561/smp.c
3 * Author: Philippe Gerum <rpm@xenomai.org>
5 * Copyright 2007 Analog Devices Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see the file COPYING, or write
19 * to the Free Software Foundation, Inc.,
20 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/delay.h>
30 #define COREB_SRAM_BASE 0xff600000
31 #define COREB_SRAM_SIZE 0x4000
33 extern char coreb_trampoline_start, coreb_trampoline_end;
35 static DEFINE_SPINLOCK(boot_lock);
37 static cpumask_t cpu_callin_map;
40 * platform_init_cpus() - Tell the world about how many cores we
41 * have. This is called while setting up the architecture support
42 * (setup_arch()), so don't be too demanding here with respect to
43 * available kernel services.
46 void __init platform_init_cpus(void)
48 cpu_set(0, cpu_possible_map); /* CoreA */
49 cpu_set(1, cpu_possible_map); /* CoreB */
52 void __init platform_prepare_cpus(unsigned int max_cpus)
56 len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
57 BUG_ON(len > COREB_SRAM_SIZE);
59 dma_memcpy((void *)COREB_SRAM_BASE, &coreb_trampoline_start, len);
61 /* Both cores ought to be present on a bf561! */
62 cpu_set(0, cpu_present_map); /* CoreA */
63 cpu_set(1, cpu_present_map); /* CoreB */
65 printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_SRAM_BASE);
68 int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
73 void __cpuinit platform_secondary_init(unsigned int cpu)
77 /* Clone setup for peripheral interrupt sources from CoreA. */
78 bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
79 bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
82 /* Clone setup for IARs from CoreA. */
83 bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
84 bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
85 bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
86 bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
87 bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
88 bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
89 bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
90 bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
95 /* Calibrate loops per jiffy value. */
98 /* Store CPU-private information to the cpu_data array. */
99 bfin_setup_cpudata(cpu);
101 /* We are done with local CPU inits, unblock the boot CPU. */
102 cpu_set(cpu, cpu_callin_map);
103 spin_lock(&boot_lock);
104 spin_unlock(&boot_lock);
107 int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
109 unsigned long timeout;
111 /* CoreB already running?! */
112 BUG_ON((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0);
114 printk(KERN_INFO "Booting Core B.\n");
116 spin_lock(&boot_lock);
118 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
120 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT);
123 timeout = jiffies + 1 * HZ;
124 while (time_before(jiffies, timeout)) {
125 if (cpu_isset(cpu, cpu_callin_map))
131 spin_unlock(&boot_lock);
133 return cpu_isset(cpu, cpu_callin_map) ? 0 : -ENOSYS;
136 void __init platform_request_ipi(irq_handler_t handler)
140 ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
141 "SMP interrupt", handler);
143 panic("Cannot request supplemental interrupt 0 for IPI service\n");
146 void platform_send_ipi(cpumask_t callmap)
150 for_each_cpu_mask(cpu, callmap) {
153 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
158 void platform_send_ipi_cpu(unsigned int cpu)
162 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
166 void platform_clear_ipi(unsigned int cpu)
170 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu)));