2 * Copyright 2007-2009 Analog Devices Inc.
3 * Philippe Gerum <rpm@xenomai.org>
5 * Licensed under the GPL-2 or later.
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/delay.h>
15 static DEFINE_SPINLOCK(boot_lock);
17 static cpumask_t cpu_callin_map;
20 * platform_init_cpus() - Tell the world about how many cores we
21 * have. This is called while setting up the architecture support
22 * (setup_arch()), so don't be too demanding here with respect to
23 * available kernel services.
26 void __init platform_init_cpus(void)
28 cpu_set(0, cpu_possible_map); /* CoreA */
29 cpu_set(1, cpu_possible_map); /* CoreB */
32 void __init platform_prepare_cpus(unsigned int max_cpus)
36 len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
37 BUG_ON(len > L1_CODE_LENGTH);
39 dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
41 /* Both cores ought to be present on a bf561! */
42 cpu_set(0, cpu_present_map); /* CoreA */
43 cpu_set(1, cpu_present_map); /* CoreB */
45 printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
48 int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
53 void __cpuinit platform_secondary_init(unsigned int cpu)
55 /* Clone setup for peripheral interrupt sources from CoreA. */
56 bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
57 bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
60 /* Clone setup for IARs from CoreA. */
61 bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
62 bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
63 bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
64 bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
65 bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
66 bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
67 bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
68 bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
71 /* Store CPU-private information to the cpu_data array. */
72 bfin_setup_cpudata(cpu);
74 /* We are done with local CPU inits, unblock the boot CPU. */
75 cpu_set(cpu, cpu_callin_map);
76 spin_lock(&boot_lock);
77 spin_unlock(&boot_lock);
80 int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
82 unsigned long timeout;
84 /* CoreB already running?! */
85 BUG_ON((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0);
87 printk(KERN_INFO "Booting Core B.\n");
89 spin_lock(&boot_lock);
91 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
93 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT);
96 timeout = jiffies + 1 * HZ;
97 while (time_before(jiffies, timeout)) {
98 if (cpu_isset(cpu, cpu_callin_map))
104 if (cpu_isset(cpu, cpu_callin_map)) {
105 cpu_set(cpu, cpu_online_map);
106 /* release the lock and let coreb run */
107 spin_unlock(&boot_lock);
110 panic("CPU%u: processor failed to boot\n", cpu);
113 void __init platform_request_ipi(irq_handler_t handler)
117 ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
118 "Supplemental Interrupt0", handler);
120 panic("Cannot request supplemental interrupt 0 for IPI service");
123 void platform_send_ipi(cpumask_t callmap)
127 for_each_cpu_mask(cpu, callmap) {
130 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
135 void platform_send_ipi_cpu(unsigned int cpu)
139 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
143 void platform_clear_ipi(unsigned int cpu)
147 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu)));