arch/blackfin/mach-bf609/boards/ezkit.c

   1 /*
   2  * Copyright 2004-2009 Analog Devices Inc.
   3  *                2005 National ICT Australia (NICTA)
   4  *                      Aidan Williams <aidan@nicta.com.au>
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/mtd/mtd.h>
  12 #include <linux/mtd/partitions.h>
  13 #include <linux/mtd/physmap.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/spi/flash.h>
  16 #include <linux/irq.h>
  17 #include <linux/i2c.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/usb/musb.h>
  20 #include <asm/bfin_spi3.h>
  21 #include <asm/dma.h>
  22 #include <asm/gpio.h>
  23 #include <asm/nand.h>
  24 #include <asm/dpmc.h>
  25 #include <asm/portmux.h>
  26 #include <asm/bfin_sdh.h>
  27 #include <linux/input.h>
  28 #include <linux/spi/ad7877.h>
  29
  30 /*
  31  * Name the Board for the /proc/cpuinfo
  32  */
  33 const char bfin_board_name[] = "ADI BF609-EZKIT";
  34
  35 /*
  36  *  Driver needs to know address, irq and flag pin.
  37  */
  38
  39 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
  40 #include <linux/usb/isp1760.h>
  41 static struct resource bfin_isp1760_resources[] = {
  42         [0] = {
  43                 .start  = 0x2C0C0000,
  44                 .end    = 0x2C0C0000 + 0xfffff,
  45                 .flags  = IORESOURCE_MEM,
  46         },
  47         [1] = {
  48                 .start  = IRQ_PG7,
  49                 .end    = IRQ_PG7,
  50                 .flags  = IORESOURCE_IRQ,
  51         },
  52 };
  53
  54 static struct isp1760_platform_data isp1760_priv = {
  55         .is_isp1761 = 0,
  56         .bus_width_16 = 1,
  57         .port1_otg = 0,
  58         .analog_oc = 0,
  59         .dack_polarity_high = 0,
  60         .dreq_polarity_high = 0,
  61 };
  62
  63 static struct platform_device bfin_isp1760_device = {
  64         .name           = "isp1760",
  65         .id             = 0,
  66         .dev = {
  67                 .platform_data = &isp1760_priv,
  68         },
  69         .num_resources  = ARRAY_SIZE(bfin_isp1760_resources),
  70         .resource       = bfin_isp1760_resources,
  71 };
  72 #endif
  73
  74 #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
  75 #include <asm/bfin_rotary.h>
  76
  77 static struct bfin_rotary_platform_data bfin_rotary_data = {
  78         /*.rotary_up_key     = KEY_UP,*/
  79         /*.rotary_down_key   = KEY_DOWN,*/
  80         .rotary_rel_code   = REL_WHEEL,
  81         .rotary_button_key = KEY_ENTER,
  82         .debounce          = 10,        /* 0..17 */
  83         .mode              = ROT_QUAD_ENC | ROT_DEBE,
  84 };
  85
  86 static struct resource bfin_rotary_resources[] = {
  87         {
  88                 .start = IRQ_CNT,
  89                 .end = IRQ_CNT,
  90                 .flags = IORESOURCE_IRQ,
  91         },
  92 };
  93
  94 static struct platform_device bfin_rotary_device = {
  95         .name           = "bfin-rotary",
  96         .id             = -1,
  97         .num_resources  = ARRAY_SIZE(bfin_rotary_resources),
  98         .resource       = bfin_rotary_resources,
  99         .dev            = {
 100                 .platform_data = &bfin_rotary_data,
 101         },
 102 };
 103 #endif
 104
 105 #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
 106 #include <linux/stmmac.h>
 107 #include <linux/phy.h>
 108
 109 static unsigned short pins[] = P_RMII0;
 110
 111 static struct stmmac_mdio_bus_data phy_private_data = {
 112         .phy_mask = 1,
 113 };
 114
 115 static struct stmmac_dma_cfg eth_dma_cfg = {
 116         .pbl    = 2,
 117 };
 118
 119 int stmmac_ptp_clk_init(struct platform_device *pdev)
 120 {
 121         bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
 122         return 0;
 123 }
 124
 125 static struct plat_stmmacenet_data eth_private_data = {
 126         .has_gmac = 1,
 127         .bus_id   = 0,
 128         .enh_desc = 1,
 129         .phy_addr = 1,
 130         .mdio_bus_data = &phy_private_data,
 131         .dma_cfg  = &eth_dma_cfg,
 132         .force_thresh_dma_mode = 1,
 133         .interface = PHY_INTERFACE_MODE_RMII,
 134         .init = stmmac_ptp_clk_init,
 135 };
 136
 137 static struct platform_device bfin_eth_device = {
 138         .name           = "stmmaceth",
 139         .id             = 0,
 140         .num_resources  = 2,
 141         .resource       = (struct resource[]) {
 142                 {
 143                         .start  = EMAC0_MACCFG,
 144                         .end    = EMAC0_MACCFG + 0x1274,
 145                         .flags  = IORESOURCE_MEM,
 146                 },
 147                 {
 148                         .name   = "macirq",
 149                         .start  = IRQ_EMAC0_STAT,
 150                         .end    = IRQ_EMAC0_STAT,
 151                         .flags  = IORESOURCE_IRQ,
 152                 },
 153         },
 154         .dev = {
 155                 .power.can_wakeup = 1,
 156                 .platform_data = &eth_private_data,
 157         }
 158 };
 159 #endif
 160
 161 #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
 162 #include <linux/input/adxl34x.h>
 163 static const struct adxl34x_platform_data adxl34x_info = {
 164         .x_axis_offset = 0,
 165         .y_axis_offset = 0,
 166         .z_axis_offset = 0,
 167         .tap_threshold = 0x31,
 168         .tap_duration = 0x10,
 169         .tap_latency = 0x60,
 170         .tap_window = 0xF0,
 171         .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
 172         .act_axis_control = 0xFF,
 173         .activity_threshold = 5,
 174         .inactivity_threshold = 3,
 175         .inactivity_time = 4,
 176         .free_fall_threshold = 0x7,
 177         .free_fall_time = 0x20,
 178         .data_rate = 0x8,
 179         .data_range = ADXL_FULL_RES,
 180
 181         .ev_type = EV_ABS,
 182         .ev_code_x = ABS_X,             /* EV_REL */
 183         .ev_code_y = ABS_Y,             /* EV_REL */
 184         .ev_code_z = ABS_Z,             /* EV_REL */
 185
 186         .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
 187
 188 /*      .ev_code_ff = KEY_F,*/          /* EV_KEY */
 189 /*      .ev_code_act_inactivity = KEY_A,*/      /* EV_KEY */
 190         .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
 191         .fifo_mode = ADXL_FIFO_STREAM,
 192         .orientation_enable = ADXL_EN_ORIENTATION_3D,
 193         .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
 194         .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
 195         /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
 196         .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
 197 };
 198 #endif
 199
 200 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
 201 static struct platform_device rtc_device = {
 202         .name = "rtc-bfin",
 203         .id   = -1,
 204 };
 205 #endif
 206
 207 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 208 #ifdef CONFIG_SERIAL_BFIN_UART0
 209 static struct resource bfin_uart0_resources[] = {
 210         {
 211                 .start = UART0_REVID,
 212                 .end = UART0_RXDIV+4,
 213                 .flags = IORESOURCE_MEM,
 214         },
 215         {
 216                 .start = IRQ_UART0_TX,
 217                 .end = IRQ_UART0_TX,
 218                 .flags = IORESOURCE_IRQ,
 219         },
 220         {
 221                 .start = IRQ_UART0_RX,
 222                 .end = IRQ_UART0_RX,
 223                 .flags = IORESOURCE_IRQ,
 224         },
 225         {
 226                 .start = IRQ_UART0_STAT,
 227                 .end = IRQ_UART0_STAT,
 228                 .flags = IORESOURCE_IRQ,
 229         },
 230         {
 231                 .start = CH_UART0_TX,
 232                 .end = CH_UART0_TX,
 233                 .flags = IORESOURCE_DMA,
 234         },
 235         {
 236                 .start = CH_UART0_RX,
 237                 .end = CH_UART0_RX,
 238                 .flags = IORESOURCE_DMA,
 239         },
 240 #ifdef CONFIG_BFIN_UART0_CTSRTS
 241         {       /* CTS pin -- 0 means not supported */
 242                 .start = GPIO_PD10,
 243                 .end = GPIO_PD10,
 244                 .flags = IORESOURCE_IO,
 245         },
 246         {       /* RTS pin -- 0 means not supported */
 247                 .start = GPIO_PD9,
 248                 .end = GPIO_PD9,
 249                 .flags = IORESOURCE_IO,
 250         },
 251 #endif
 252 };
 253
 254 static unsigned short bfin_uart0_peripherals[] = {
 255         P_UART0_TX, P_UART0_RX,
 256 #ifdef CONFIG_BFIN_UART0_CTSRTS
 257         P_UART0_RTS, P_UART0_CTS,
 258 #endif
 259         0
 260 };
 261
 262 static struct platform_device bfin_uart0_device = {
 263         .name = "bfin-uart",
 264         .id = 0,
 265         .num_resources = ARRAY_SIZE(bfin_uart0_resources),
 266         .resource = bfin_uart0_resources,
 267         .dev = {
 268                 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
 269         },
 270 };
 271 #endif
 272 #ifdef CONFIG_SERIAL_BFIN_UART1
 273 static struct resource bfin_uart1_resources[] = {
 274         {
 275                 .start = UART1_REVID,
 276                 .end = UART1_RXDIV+4,
 277                 .flags = IORESOURCE_MEM,
 278         },
 279         {
 280                 .start = IRQ_UART1_TX,
 281                 .end = IRQ_UART1_TX,
 282                 .flags = IORESOURCE_IRQ,
 283         },
 284         {
 285                 .start = IRQ_UART1_RX,
 286                 .end = IRQ_UART1_RX,
 287                 .flags = IORESOURCE_IRQ,
 288         },
 289         {
 290                 .start = IRQ_UART1_STAT,
 291                 .end = IRQ_UART1_STAT,
 292                 .flags = IORESOURCE_IRQ,
 293         },
 294         {
 295                 .start = CH_UART1_TX,
 296                 .end = CH_UART1_TX,
 297                 .flags = IORESOURCE_DMA,
 298         },
 299         {
 300                 .start = CH_UART1_RX,
 301                 .end = CH_UART1_RX,
 302                 .flags = IORESOURCE_DMA,
 303         },
 304 #ifdef CONFIG_BFIN_UART1_CTSRTS
 305         {       /* CTS pin -- 0 means not supported */
 306                 .start = GPIO_PG13,
 307                 .end = GPIO_PG13,
 308                 .flags = IORESOURCE_IO,
 309         },
 310         {       /* RTS pin -- 0 means not supported */
 311                 .start = GPIO_PG10,
 312                 .end = GPIO_PG10,
 313                 .flags = IORESOURCE_IO,
 314         },
 315 #endif
 316 };
 317
 318 static unsigned short bfin_uart1_peripherals[] = {
 319         P_UART1_TX, P_UART1_RX,
 320 #ifdef CONFIG_BFIN_UART1_CTSRTS
 321         P_UART1_RTS, P_UART1_CTS,
 322 #endif
 323         0
 324 };
 325
 326 static struct platform_device bfin_uart1_device = {
 327         .name = "bfin-uart",
 328         .id = 1,
 329         .num_resources = ARRAY_SIZE(bfin_uart1_resources),
 330         .resource = bfin_uart1_resources,
 331         .dev = {
 332                 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
 333         },
 334 };
 335 #endif
 336 #endif
 337
 338 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
 339 #ifdef CONFIG_BFIN_SIR0
 340 static struct resource bfin_sir0_resources[] = {
 341         {
 342                 .start = 0xFFC00400,
 343                 .end = 0xFFC004FF,
 344                 .flags = IORESOURCE_MEM,
 345         },
 346         {
 347                 .start = IRQ_UART0_TX,
 348                 .end = IRQ_UART0_TX+1,
 349                 .flags = IORESOURCE_IRQ,
 350         },
 351         {
 352                 .start = CH_UART0_TX,
 353                 .end = CH_UART0_TX+1,
 354                 .flags = IORESOURCE_DMA,
 355         },
 356 };
 357 static struct platform_device bfin_sir0_device = {
 358         .name = "bfin_sir",
 359         .id = 0,
 360         .num_resources = ARRAY_SIZE(bfin_sir0_resources),
 361         .resource = bfin_sir0_resources,
 362 };
 363 #endif
 364 #ifdef CONFIG_BFIN_SIR1
 365 static struct resource bfin_sir1_resources[] = {
 366         {
 367                 .start = 0xFFC02000,
 368                 .end = 0xFFC020FF,
 369                 .flags = IORESOURCE_MEM,
 370         },
 371         {
 372                 .start = IRQ_UART1_TX,
 373                 .end = IRQ_UART1_TX+1,
 374                 .flags = IORESOURCE_IRQ,
 375         },
 376         {
 377                 .start = CH_UART1_TX,
 378                 .end = CH_UART1_TX+1,
 379                 .flags = IORESOURCE_DMA,
 380         },
 381 };
 382 static struct platform_device bfin_sir1_device = {
 383         .name = "bfin_sir",
 384         .id = 1,
 385         .num_resources = ARRAY_SIZE(bfin_sir1_resources),
 386         .resource = bfin_sir1_resources,
 387 };
 388 #endif
 389 #endif
 390
 391 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
 392 static struct resource musb_resources[] = {
 393         [0] = {
 394                 .start  = 0xFFCC1000,
 395                 .end    = 0xFFCC1398,
 396                 .flags  = IORESOURCE_MEM,
 397         },
 398         [1] = { /* general IRQ */
 399                 .start  = IRQ_USB_STAT,
 400                 .end    = IRQ_USB_STAT,
 401                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 402                 .name   = "mc"
 403         },
 404         [2] = { /* DMA IRQ */
 405                 .start  = IRQ_USB_DMA,
 406                 .end    = IRQ_USB_DMA,
 407                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 408                 .name   = "dma"
 409         },
 410 };
 411
 412 static struct musb_hdrc_config musb_config = {
 413         .multipoint     = 1,
 414         .dyn_fifo       = 0,
 415         .dma            = 1,
 416         .num_eps        = 16,
 417         .dma_channels   = 8,
 418         .clkin          = 48,           /* musb CLKIN in MHZ */
 419 };
 420
 421 static struct musb_hdrc_platform_data musb_plat = {
 422 #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
 423         .mode           = MUSB_OTG,
 424 #elif defined(CONFIG_USB_MUSB_HDRC)
 425         .mode           = MUSB_HOST,
 426 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
 427         .mode           = MUSB_PERIPHERAL,
 428 #endif
 429         .config         = &musb_config,
 430 };
 431
 432 static u64 musb_dmamask = ~(u32)0;
 433
 434 static struct platform_device musb_device = {
 435         .name           = "musb-blackfin",
 436         .id             = 0,
 437         .dev = {
 438                 .dma_mask               = &musb_dmamask,
 439                 .coherent_dma_mask      = 0xffffffff,
 440                 .platform_data          = &musb_plat,
 441         },
 442         .num_resources  = ARRAY_SIZE(musb_resources),
 443         .resource       = musb_resources,
 444 };
 445 #endif
 446
 447 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 448 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 449 static struct resource bfin_sport0_uart_resources[] = {
 450         {
 451                 .start = SPORT0_TCR1,
 452                 .end = SPORT0_MRCS3+4,
 453                 .flags = IORESOURCE_MEM,
 454         },
 455         {
 456                 .start = IRQ_SPORT0_RX,
 457                 .end = IRQ_SPORT0_RX+1,
 458                 .flags = IORESOURCE_IRQ,
 459         },
 460         {
 461                 .start = IRQ_SPORT0_ERROR,
 462                 .end = IRQ_SPORT0_ERROR,
 463                 .flags = IORESOURCE_IRQ,
 464         },
 465 };
 466
 467 static unsigned short bfin_sport0_peripherals[] = {
 468         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
 469         P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 470 };
 471
 472 static struct platform_device bfin_sport0_uart_device = {
 473         .name = "bfin-sport-uart",
 474         .id = 0,
 475         .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
 476         .resource = bfin_sport0_uart_resources,
 477         .dev = {
 478                 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
 479         },
 480 };
 481 #endif
 482 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 483 static struct resource bfin_sport1_uart_resources[] = {
 484         {
 485                 .start = SPORT1_TCR1,
 486                 .end = SPORT1_MRCS3+4,
 487                 .flags = IORESOURCE_MEM,
 488         },
 489         {
 490                 .start = IRQ_SPORT1_RX,
 491                 .end = IRQ_SPORT1_RX+1,
 492                 .flags = IORESOURCE_IRQ,
 493         },
 494         {
 495                 .start = IRQ_SPORT1_ERROR,
 496                 .end = IRQ_SPORT1_ERROR,
 497                 .flags = IORESOURCE_IRQ,
 498         },
 499 };
 500
 501 static unsigned short bfin_sport1_peripherals[] = {
 502         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
 503         P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 504 };
 505
 506 static struct platform_device bfin_sport1_uart_device = {
 507         .name = "bfin-sport-uart",
 508         .id = 1,
 509         .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
 510         .resource = bfin_sport1_uart_resources,
 511         .dev = {
 512                 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
 513         },
 514 };
 515 #endif
 516 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
 517 static struct resource bfin_sport2_uart_resources[] = {
 518         {
 519                 .start = SPORT2_TCR1,
 520                 .end = SPORT2_MRCS3+4,
 521                 .flags = IORESOURCE_MEM,
 522         },
 523         {
 524                 .start = IRQ_SPORT2_RX,
 525                 .end = IRQ_SPORT2_RX+1,
 526                 .flags = IORESOURCE_IRQ,
 527         },
 528         {
 529                 .start = IRQ_SPORT2_ERROR,
 530                 .end = IRQ_SPORT2_ERROR,
 531                 .flags = IORESOURCE_IRQ,
 532         },
 533 };
 534
 535 static unsigned short bfin_sport2_peripherals[] = {
 536         P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
 537         P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
 538 };
 539
 540 static struct platform_device bfin_sport2_uart_device = {
 541         .name = "bfin-sport-uart",
 542         .id = 2,
 543         .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
 544         .resource = bfin_sport2_uart_resources,
 545         .dev = {
 546                 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
 547         },
 548 };
 549 #endif
 550 #endif
 551
 552 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
 553
 554 static unsigned short bfin_can0_peripherals[] = {
 555         P_CAN0_RX, P_CAN0_TX, 0
 556 };
 557
 558 static struct resource bfin_can0_resources[] = {
 559         {
 560                 .start = 0xFFC00A00,
 561                 .end = 0xFFC00FFF,
 562                 .flags = IORESOURCE_MEM,
 563         },
 564         {
 565                 .start = IRQ_CAN0_RX,
 566                 .end = IRQ_CAN0_RX,
 567                 .flags = IORESOURCE_IRQ,
 568         },
 569         {
 570                 .start = IRQ_CAN0_TX,
 571                 .end = IRQ_CAN0_TX,
 572                 .flags = IORESOURCE_IRQ,
 573         },
 574         {
 575                 .start = IRQ_CAN0_STAT,
 576                 .end = IRQ_CAN0_STAT,
 577                 .flags = IORESOURCE_IRQ,
 578         },
 579 };
 580
 581 static struct platform_device bfin_can0_device = {
 582         .name = "bfin_can",
 583         .id = 0,
 584         .num_resources = ARRAY_SIZE(bfin_can0_resources),
 585         .resource = bfin_can0_resources,
 586         .dev = {
 587                 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
 588         },
 589 };
 590
 591 #endif
 592
 593 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
 594 static struct mtd_partition partition_info[] = {
 595         {
 596                 .name = "bootloader(nand)",
 597                 .offset = 0,
 598                 .size = 0x80000,
 599         }, {
 600                 .name = "linux kernel(nand)",
 601                 .offset = MTDPART_OFS_APPEND,
 602                 .size = 4 * 1024 * 1024,
 603         },
 604         {
 605                 .name = "file system(nand)",
 606                 .offset = MTDPART_OFS_APPEND,
 607                 .size = MTDPART_SIZ_FULL,
 608         },
 609 };
 610
 611 static struct bf5xx_nand_platform bfin_nand_platform = {
 612         .data_width = NFC_NWIDTH_8,
 613         .partitions = partition_info,
 614         .nr_partitions = ARRAY_SIZE(partition_info),
 615         .rd_dly = 3,
 616         .wr_dly = 3,
 617 };
 618
 619 static struct resource bfin_nand_resources[] = {
 620         {
 621                 .start = 0xFFC03B00,
 622                 .end = 0xFFC03B4F,
 623                 .flags = IORESOURCE_MEM,
 624         },
 625         {
 626                 .start = CH_NFC,
 627                 .end = CH_NFC,
 628                 .flags = IORESOURCE_IRQ,
 629         },
 630 };
 631
 632 static struct platform_device bfin_nand_device = {
 633         .name = "bfin-nand",
 634         .id = 0,
 635         .num_resources = ARRAY_SIZE(bfin_nand_resources),
 636         .resource = bfin_nand_resources,
 637         .dev = {
 638                 .platform_data = &bfin_nand_platform,
 639         },
 640 };
 641 #endif
 642
 643 #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
 644
 645 static struct bfin_sd_host bfin_sdh_data = {
 646         .dma_chan = CH_RSI,
 647         .irq_int0 = IRQ_RSI_INT0,
 648         .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
 649 };
 650
 651 static struct platform_device bfin_sdh_device = {
 652         .name = "bfin-sdh",
 653         .id = 0,
 654         .dev = {
 655                 .platform_data = &bfin_sdh_data,
 656         },
 657 };
 658 #endif
 659
 660 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
 661 static struct mtd_partition ezkit_partitions[] = {
 662         {
 663                 .name       = "bootloader(nor)",
 664                 .size       = 0x80000,
 665                 .offset     = 0,
 666         }, {
 667                 .name       = "linux kernel(nor)",
 668                 .size       = 0x400000,
 669                 .offset     = MTDPART_OFS_APPEND,
 670         }, {
 671                 .name       = "file system(nor)",
 672                 .size       = 0x1000000 - 0x80000 - 0x400000,
 673                 .offset     = MTDPART_OFS_APPEND,
 674         },
 675 };
 676
 677 int bf609_nor_flash_init(struct platform_device *dev)
 678 {
 679 #define CONFIG_SMC_GCTL_VAL     0x00000010
 680         const unsigned short pins[] = {
 681                 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
 682                 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
 683                 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
 684         };
 685
 686         peripheral_request_list(pins, "smc0");
 687
 688         bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
 689         bfin_write32(SMC_B0CTL, 0x01002011);
 690         bfin_write32(SMC_B0TIM, 0x08170977);
 691         bfin_write32(SMC_B0ETIM, 0x00092231);
 692         return 0;
 693 }
 694
 695 void bf609_nor_flash_exit(struct platform_device *dev)
 696 {
 697         const unsigned short pins[] = {
 698                 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
 699                 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
 700                 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
 701         };
 702
 703         peripheral_free_list(pins);
 704
 705         bfin_write32(SMC_GCTL, 0);
 706 }
 707
 708 static struct physmap_flash_data ezkit_flash_data = {
 709         .width      = 2,
 710         .parts      = ezkit_partitions,
 711         .init       = bf609_nor_flash_init,
 712         .exit       = bf609_nor_flash_exit,
 713         .nr_parts   = ARRAY_SIZE(ezkit_partitions),
 714 #ifdef CONFIG_ROMKERNEL
 715         .probe_type = "map_rom",
 716 #endif
 717 };
 718
 719 static struct resource ezkit_flash_resource = {
 720         .start = 0xb0000000,
 721         .end   = 0xb0ffffff,
 722         .flags = IORESOURCE_MEM,
 723 };
 724
 725 static struct platform_device ezkit_flash_device = {
 726         .name          = "physmap-flash",
 727         .id            = 0,
 728         .dev = {
 729                 .platform_data = &ezkit_flash_data,
 730         },
 731         .num_resources = 1,
 732         .resource      = &ezkit_flash_resource,
 733 };
 734 #endif
 735
 736 #if defined(CONFIG_MTD_M25P80) \
 737         || defined(CONFIG_MTD_M25P80_MODULE)
 738 /* SPI flash chip (w25q32) */
 739 static struct mtd_partition bfin_spi_flash_partitions[] = {
 740         {
 741                 .name = "bootloader(spi)",
 742                 .size = 0x00080000,
 743                 .offset = 0,
 744                 .mask_flags = MTD_CAP_ROM
 745         }, {
 746                 .name = "linux kernel(spi)",
 747                 .size = 0x00180000,
 748                 .offset = MTDPART_OFS_APPEND,
 749         }, {
 750                 .name = "file system(spi)",
 751                 .size = MTDPART_SIZ_FULL,
 752                 .offset = MTDPART_OFS_APPEND,
 753         }
 754 };
 755
 756 static struct flash_platform_data bfin_spi_flash_data = {
 757         .name = "m25p80",
 758         .parts = bfin_spi_flash_partitions,
 759         .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
 760         .type = "w25q32",
 761 };
 762
 763 static struct bfin_spi3_chip spi_flash_chip_info = {
 764         .enable_dma = true,         /* use dma transfer with this chip*/
 765 };
 766 #endif
 767
 768 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 769 static struct bfin_spi3_chip spidev_chip_info = {
 770         .enable_dma = true,
 771 };
 772 #endif
 773
 774 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
 775 static struct platform_device bfin_i2s_pcm = {
 776         .name = "bfin-i2s-pcm-audio",
 777         .id = -1,
 778 };
 779 #endif
 780
 781 #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
 782         defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
 783 #include <asm/bfin_sport3.h>
 784 static struct resource bfin_snd_resources[] = {
 785         {
 786                 .start = SPORT0_CTL_A,
 787                 .end = SPORT0_CTL_A,
 788                 .flags = IORESOURCE_MEM,
 789         },
 790         {
 791                 .start = SPORT0_CTL_B,
 792                 .end = SPORT0_CTL_B,
 793                 .flags = IORESOURCE_MEM,
 794         },
 795         {
 796                 .start = CH_SPORT0_TX,
 797                 .end = CH_SPORT0_TX,
 798                 .flags = IORESOURCE_DMA,
 799         },
 800         {
 801                 .start = CH_SPORT0_RX,
 802                 .end = CH_SPORT0_RX,
 803                 .flags = IORESOURCE_DMA,
 804         },
 805         {
 806                 .start = IRQ_SPORT0_TX_STAT,
 807                 .end = IRQ_SPORT0_TX_STAT,
 808                 .flags = IORESOURCE_IRQ,
 809         },
 810         {
 811                 .start = IRQ_SPORT0_RX_STAT,
 812                 .end = IRQ_SPORT0_RX_STAT,
 813                 .flags = IORESOURCE_IRQ,
 814         },
 815 };
 816
 817 static const unsigned short bfin_snd_pin[] = {
 818         P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
 819         P_SPORT0_BFS, P_SPORT0_BD0, 0,
 820 };
 821
 822 static struct bfin_snd_platform_data bfin_snd_data = {
 823         .pin_req = bfin_snd_pin,
 824 };
 825
 826 static struct platform_device bfin_i2s = {
 827         .name = "bfin-i2s",
 828         .num_resources = ARRAY_SIZE(bfin_snd_resources),
 829         .resource = bfin_snd_resources,
 830         .dev = {
 831                 .platform_data = &bfin_snd_data,
 832         },
 833 };
 834 #endif
 835
 836 #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
 837                 || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
 838 static const char * const ad1836_link[] = {
 839         "bfin-i2s.0",
 840         "spi0.76",
 841 };
 842 static struct platform_device bfin_ad1836_machine = {
 843         .name = "bfin-snd-ad1836",
 844         .id = -1,
 845         .dev = {
 846                 .platform_data = (void *)ad1836_link,
 847         },
 848 };
 849 #endif
 850
 851 #if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
 852         defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
 853 static struct platform_device adau1761_device = {
 854         .name = "bfin-eval-adau1x61",
 855 };
 856 #endif
 857
 858 #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
 859 #include <sound/adau17x1.h>
 860 static struct adau1761_platform_data adau1761_info = {
 861         .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
 862         .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
 863 };
 864 #endif
 865
 866 #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
 867         || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
 868 #include <linux/videodev2.h>
 869 #include <media/blackfin/bfin_capture.h>
 870 #include <media/blackfin/ppi.h>
 871
 872 static const unsigned short ppi_req[] = {
 873         P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
 874         P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
 875         P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
 876         P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
 877 #if !defined(CONFIG_VIDEO_VS6624) && !defined(CONFIG_VIDEO_VS6624_MODULE)
 878         P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
 879         P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
 880 #endif
 881         P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
 882         0,
 883 };
 884
 885 static const struct ppi_info ppi_info = {
 886         .type = PPI_TYPE_EPPI3,
 887         .dma_ch = CH_EPPI0_CH0,
 888         .irq_err = IRQ_EPPI0_STAT,
 889         .base = (void __iomem *)EPPI0_STAT,
 890         .pin_req = ppi_req,
 891 };
 892
 893 #if defined(CONFIG_VIDEO_VS6624) \
 894         || defined(CONFIG_VIDEO_VS6624_MODULE)
 895 static struct v4l2_input vs6624_inputs[] = {
 896         {
 897                 .index = 0,
 898                 .name = "Camera",
 899                 .type = V4L2_INPUT_TYPE_CAMERA,
 900                 .std = V4L2_STD_UNKNOWN,
 901         },
 902 };
 903
 904 static struct bcap_route vs6624_routes[] = {
 905         {
 906                 .input = 0,
 907                 .output = 0,
 908         },
 909 };
 910
 911 static const unsigned vs6624_ce_pin = GPIO_PE4;
 912
 913 static struct bfin_capture_config bfin_capture_data = {
 914         .card_name = "BF609",
 915         .inputs = vs6624_inputs,
 916         .num_inputs = ARRAY_SIZE(vs6624_inputs),
 917         .routes = vs6624_routes,
 918         .i2c_adapter_id = 0,
 919         .board_info = {
 920                 .type = "vs6624",
 921                 .addr = 0x10,
 922                 .platform_data = (void *)&vs6624_ce_pin,
 923         },
 924         .ppi_info = &ppi_info,
 925         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
 926                         | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
 927         .blank_pixels = 4,
 928 };
 929 #endif
 930
 931 #if defined(CONFIG_VIDEO_ADV7842) \
 932         || defined(CONFIG_VIDEO_ADV7842_MODULE)
 933 #include <media/adv7842.h>
 934
 935 static struct v4l2_input adv7842_inputs[] = {
 936         {
 937                 .index = 0,
 938                 .name = "Composite",
 939                 .type = V4L2_INPUT_TYPE_CAMERA,
 940                 .std = V4L2_STD_ALL,
 941                 .capabilities = V4L2_IN_CAP_STD,
 942         },
 943         {
 944                 .index = 1,
 945                 .name = "S-Video",
 946                 .type = V4L2_INPUT_TYPE_CAMERA,
 947                 .std = V4L2_STD_ALL,
 948                 .capabilities = V4L2_IN_CAP_STD,
 949         },
 950         {
 951                 .index = 2,
 952                 .name = "Component",
 953                 .type = V4L2_INPUT_TYPE_CAMERA,
 954                 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
 955         },
 956         {
 957                 .index = 3,
 958                 .name = "VGA",
 959                 .type = V4L2_INPUT_TYPE_CAMERA,
 960                 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
 961         },
 962         {
 963                 .index = 4,
 964                 .name = "HDMI",
 965                 .type = V4L2_INPUT_TYPE_CAMERA,
 966                 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
 967         },
 968 };
 969
 970 static struct bcap_route adv7842_routes[] = {
 971         {
 972                 .input = 3,
 973                 .output = 0,
 974                 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
 975                                 | EPPI_CTL_ACTIVE656),
 976         },
 977         {
 978                 .input = 4,
 979                 .output = 0,
 980         },
 981         {
 982                 .input = 2,
 983                 .output = 0,
 984         },
 985         {
 986                 .input = 1,
 987                 .output = 0,
 988         },
 989         {
 990                 .input = 0,
 991                 .output = 1,
 992                 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
 993                                 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
 994                                 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
 995         },
 996 };
 997
 998 static struct adv7842_output_format adv7842_opf[] = {
 999         {
1000                 .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
1001                 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
1002                 .op_656_range = 1,
1003                 .blank_data = 1,
1004                 .insert_av_codes = 1,
1005         },
1006         {
1007                 .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
1008                 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
1009                 .op_656_range = 1,
1010                 .blank_data = 1,
1011         },
1012 };
1013
1014 static struct adv7842_platform_data adv7842_data = {
1015         .opf = adv7842_opf,
1016         .num_opf = ARRAY_SIZE(adv7842_opf),
1017         .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
1018         .prim_mode = ADV7842_PRIM_MODE_SDP,
1019         .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
1020         .inp_color_space = ADV7842_INP_COLOR_SPACE_AUTO,
1021         .i2c_sdp_io = 0x40,
1022         .i2c_sdp = 0x41,
1023         .i2c_cp = 0x42,
1024         .i2c_vdp = 0x43,
1025         .i2c_afe = 0x44,
1026         .i2c_hdmi = 0x45,
1027         .i2c_repeater = 0x46,
1028         .i2c_edid = 0x47,
1029         .i2c_infoframe = 0x48,
1030         .i2c_cec = 0x49,
1031         .i2c_avlink = 0x4a,
1032         .i2c_ex = 0x26,
1033 };
1034
1035 static struct bfin_capture_config bfin_capture_data = {
1036         .card_name = "BF609",
1037         .inputs = adv7842_inputs,
1038         .num_inputs = ARRAY_SIZE(adv7842_inputs),
1039         .routes = adv7842_routes,
1040         .i2c_adapter_id = 0,
1041         .board_info = {
1042                 .type = "adv7842",
1043                 .addr = 0x20,
1044                 .platform_data = (void *)&adv7842_data,
1045         },
1046         .ppi_info = &ppi_info,
1047         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
1048                         | EPPI_CTL_ACTIVE656),
1049 };
1050 #endif
1051
1052 static struct platform_device bfin_capture_device = {
1053         .name = "bfin_capture",
1054         .dev = {
1055                 .platform_data = &bfin_capture_data,
1056         },
1057 };
1058 #endif
1059
1060 #if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
1061         || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
1062 #include <linux/videodev2.h>
1063 #include <media/blackfin/bfin_display.h>
1064 #include <media/blackfin/ppi.h>
1065
1066 static const unsigned short ppi_req_disp[] = {
1067         P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
1068         P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
1069         P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
1070         P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
1071         P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
1072         0,
1073 };
1074
1075 static const struct ppi_info ppi_info = {
1076         .type = PPI_TYPE_EPPI3,
1077         .dma_ch = CH_EPPI0_CH0,
1078         .irq_err = IRQ_EPPI0_STAT,
1079         .base = (void __iomem *)EPPI0_STAT,
1080         .pin_req = ppi_req_disp,
1081 };
1082
1083 #if defined(CONFIG_VIDEO_ADV7511) \
1084         || defined(CONFIG_VIDEO_ADV7511_MODULE)
1085 #include <media/adv7511.h>
1086
1087 static struct v4l2_output adv7511_outputs[] = {
1088         {
1089                 .index = 0,
1090                 .name = "HDMI",
1091                 .type = V4L2_INPUT_TYPE_CAMERA,
1092                 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
1093         },
1094 };
1095
1096 static struct disp_route adv7511_routes[] = {
1097         {
1098                 .output = 0,
1099         },
1100 };
1101
1102 static struct adv7511_platform_data adv7511_data = {
1103         .edid_addr = 0x7e,
1104         .i2c_ex = 0x25,
1105 };
1106
1107 static struct bfin_display_config bfin_display_data = {
1108         .card_name = "BF609",
1109         .outputs = adv7511_outputs,
1110         .num_outputs = ARRAY_SIZE(adv7511_outputs),
1111         .routes = adv7511_routes,
1112         .i2c_adapter_id = 0,
1113         .board_info = {
1114                 .type = "adv7511",
1115                 .addr = 0x39,
1116                 .platform_data = (void *)&adv7511_data,
1117         },
1118         .ppi_info = &ppi_info,
1119         .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
1120                         | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
1121                         | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
1122                         | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1123 };
1124 #endif
1125
1126 #if IS_ENABLED(CONFIG_VIDEO_ADV7343)
1127 #include <media/adv7343.h>
1128
1129 static struct v4l2_output adv7343_outputs[] = {
1130         {
1131                 .index = 0,
1132                 .name = "Composite",
1133                 .type = V4L2_OUTPUT_TYPE_ANALOG,
1134                 .std = V4L2_STD_ALL,
1135                 .capabilities = V4L2_OUT_CAP_STD,
1136         },
1137         {
1138                 .index = 1,
1139                 .name = "S-Video",
1140                 .type = V4L2_OUTPUT_TYPE_ANALOG,
1141                 .std = V4L2_STD_ALL,
1142                 .capabilities = V4L2_OUT_CAP_STD,
1143         },
1144         {
1145                 .index = 2,
1146                 .name = "Component",
1147                 .type = V4L2_OUTPUT_TYPE_ANALOG,
1148                 .std = V4L2_STD_ALL,
1149                 .capabilities = V4L2_OUT_CAP_STD,
1150         },
1151
1152 };
1153
1154 static struct disp_route adv7343_routes[] = {
1155         {
1156                 .output = ADV7343_COMPOSITE_ID,
1157         },
1158         {
1159                 .output = ADV7343_SVIDEO_ID,
1160         },
1161         {
1162                 .output = ADV7343_COMPONENT_ID,
1163         },
1164 };
1165
1166 static struct adv7343_platform_data adv7343_data = {
1167         .mode_config = {
1168                 .sleep_mode = false,
1169                 .pll_control = false,
1170                 .dac_1 = true,
1171                 .dac_2 = true,
1172                 .dac_3 = true,
1173                 .dac_4 = true,
1174                 .dac_5 = true,
1175                 .dac_6 = true,
1176         },
1177         .sd_config = {
1178                 .sd_dac_out1 = false,
1179                 .sd_dac_out2 = false,
1180         },
1181 };
1182
1183 static struct bfin_display_config bfin_display_data = {
1184         .card_name = "BF609",
1185         .outputs = adv7343_outputs,
1186         .num_outputs = ARRAY_SIZE(adv7343_outputs),
1187         .routes = adv7343_routes,
1188         .i2c_adapter_id = 0,
1189         .board_info = {
1190                 .type = "adv7343",
1191                 .addr = 0x2b,
1192                 .platform_data = (void *)&adv7343_data,
1193         },
1194         .ppi_info = &ppi_info_disp,
1195         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
1196                         | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
1197                         | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1198 };
1199 #endif
1200
1201 static struct platform_device bfin_display_device = {
1202         .name = "bfin_display",
1203         .dev = {
1204                 .platform_data = &bfin_display_data,
1205         },
1206 };
1207 #endif
1208
1209 #if defined(CONFIG_BFIN_CRC)
1210 #define BFIN_CRC_NAME "bfin-crc"
1211
1212 static struct resource bfin_crc0_resources[] = {
1213         {
1214                 .start = REG_CRC0_CTL,
1215                 .end = REG_CRC0_REVID+4,
1216                 .flags = IORESOURCE_MEM,
1217         },
1218         {
1219                 .start = IRQ_CRC0_DCNTEXP,
1220                 .end = IRQ_CRC0_DCNTEXP,
1221                 .flags = IORESOURCE_IRQ,
1222         },
1223         {
1224                 .start = CH_MEM_STREAM0_SRC_CRC0,
1225                 .end = CH_MEM_STREAM0_SRC_CRC0,
1226                 .flags = IORESOURCE_DMA,
1227         },
1228         {
1229                 .start = CH_MEM_STREAM0_DEST_CRC0,
1230                 .end = CH_MEM_STREAM0_DEST_CRC0,
1231                 .flags = IORESOURCE_DMA,
1232         },
1233 };
1234
1235 static struct platform_device bfin_crc0_device = {
1236         .name = BFIN_CRC_NAME,
1237         .id = 0,
1238         .num_resources = ARRAY_SIZE(bfin_crc0_resources),
1239         .resource = bfin_crc0_resources,
1240 };
1241
1242 static struct resource bfin_crc1_resources[] = {
1243         {
1244                 .start = REG_CRC1_CTL,
1245                 .end = REG_CRC1_REVID+4,
1246                 .flags = IORESOURCE_MEM,
1247         },
1248         {
1249                 .start = IRQ_CRC1_DCNTEXP,
1250                 .end = IRQ_CRC1_DCNTEXP,
1251                 .flags = IORESOURCE_IRQ,
1252         },
1253         {
1254                 .start = CH_MEM_STREAM1_SRC_CRC1,
1255                 .end = CH_MEM_STREAM1_SRC_CRC1,
1256                 .flags = IORESOURCE_DMA,
1257         },
1258         {
1259                 .start = CH_MEM_STREAM1_DEST_CRC1,
1260                 .end = CH_MEM_STREAM1_DEST_CRC1,
1261                 .flags = IORESOURCE_DMA,
1262         },
1263 };
1264
1265 static struct platform_device bfin_crc1_device = {
1266         .name = BFIN_CRC_NAME,
1267         .id = 1,
1268         .num_resources = ARRAY_SIZE(bfin_crc1_resources),
1269         .resource = bfin_crc1_resources,
1270 };
1271 #endif
1272
1273 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1274 #define BFIN_CRYPTO_CRC_NAME            "bfin-hmac-crc"
1275 #define BFIN_CRYPTO_CRC_POLY_DATA       0x5c5c5c5c
1276
1277 static struct resource bfin_crypto_crc_resources[] = {
1278         {
1279                 .start = REG_CRC0_CTL,
1280                 .end = REG_CRC0_REVID+4,
1281                 .flags = IORESOURCE_MEM,
1282         },
1283         {
1284                 .start = IRQ_CRC0_DCNTEXP,
1285                 .end = IRQ_CRC0_DCNTEXP,
1286                 .flags = IORESOURCE_IRQ,
1287         },
1288         {
1289                 .start = CH_MEM_STREAM0_SRC_CRC0,
1290                 .end = CH_MEM_STREAM0_SRC_CRC0,
1291                 .flags = IORESOURCE_DMA,
1292         },
1293 };
1294
1295 static struct platform_device bfin_crypto_crc_device = {
1296         .name = BFIN_CRYPTO_CRC_NAME,
1297         .id = 0,
1298         .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
1299         .resource = bfin_crypto_crc_resources,
1300         .dev = {
1301                 .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
1302         },
1303 };
1304 #endif
1305
1306 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1307 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1308         .model                  = 7877,
1309         .vref_delay_usecs       = 50,   /* internal, no capacitor */
1310         .x_plate_ohms           = 419,
1311         .y_plate_ohms           = 486,
1312         .pressure_max           = 1000,
1313         .pressure_min           = 0,
1314         .stopacq_polarity       = 1,
1315         .first_conversion_delay = 3,
1316         .acquisition_time       = 1,
1317         .averaging              = 1,
1318         .pen_down_acc_interval  = 1,
1319 };
1320 #endif
1321
1322 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1323 #include <linux/input.h>
1324 #include <linux/gpio_keys.h>
1325
1326 static struct gpio_keys_button bfin_gpio_keys_table[] = {
1327         {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
1328         {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
1329 };
1330
1331 static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1332         .buttons        = bfin_gpio_keys_table,
1333         .nbuttons       = ARRAY_SIZE(bfin_gpio_keys_table),
1334 };
1335
1336 static struct platform_device bfin_device_gpiokeys = {
1337         .name      = "gpio-keys",
1338         .dev = {
1339                 .platform_data = &bfin_gpio_keys_data,
1340         },
1341 };
1342 #endif
1343
1344 static struct spi_board_info bfin_spi_board_info[] __initdata = {
1345 #if defined(CONFIG_MTD_M25P80) \
1346         || defined(CONFIG_MTD_M25P80_MODULE)
1347         {
1348                 /* the modalias must be the same as spi device driver name */
1349                 .modalias = "m25p80", /* Name of spi_driver for this device */
1350                 .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
1351                 .bus_num = 0, /* Framework bus number */
1352                 .chip_select = 1, /* SPI_SSEL1*/
1353                 .platform_data = &bfin_spi_flash_data,
1354                 .controller_data = &spi_flash_chip_info,
1355                 .mode = SPI_MODE_3,
1356         },
1357 #endif
1358 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1359         {
1360                 .modalias               = "ad7877",
1361                 .platform_data          = &bfin_ad7877_ts_info,
1362                 .irq                    = IRQ_PD9,
1363                 .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
1364                 .bus_num                = 0,
1365                 .chip_select            = 4,
1366         },
1367 #endif
1368 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1369         {
1370                 .modalias = "spidev",
1371                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
1372                 .bus_num = 0,
1373                 .chip_select = 1,
1374                 .controller_data = &spidev_chip_info,
1375         },
1376 #endif
1377 #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1378         {
1379                 .modalias               = "adxl34x",
1380                 .platform_data          = &adxl34x_info,
1381                 .irq                    = IRQ_PC5,
1382                 .max_speed_hz           = 5000000,     /* max spi clock (SCK) speed in HZ */
1383                 .bus_num                = 1,
1384                 .chip_select            = 2,
1385                 .mode = SPI_MODE_3,
1386         },
1387 #endif
1388 };
1389 #if IS_ENABLED(CONFIG_SPI_BFIN_V3)
1390 /* SPI (0) */
1391 static struct resource bfin_spi0_resource[] = {
1392         {
1393                 .start = SPI0_REGBASE,
1394                 .end   = SPI0_REGBASE + 0xFF,
1395                 .flags = IORESOURCE_MEM,
1396         },
1397         {
1398                 .start = CH_SPI0_TX,
1399                 .end   = CH_SPI0_TX,
1400                 .flags = IORESOURCE_DMA,
1401         },
1402         {
1403                 .start = CH_SPI0_RX,
1404                 .end   = CH_SPI0_RX,
1405                 .flags = IORESOURCE_DMA,
1406         },
1407 };
1408
1409 /* SPI (1) */
1410 static struct resource bfin_spi1_resource[] = {
1411         {
1412                 .start = SPI1_REGBASE,
1413                 .end   = SPI1_REGBASE + 0xFF,
1414                 .flags = IORESOURCE_MEM,
1415         },
1416         {
1417                 .start = CH_SPI1_TX,
1418                 .end   = CH_SPI1_TX,
1419                 .flags = IORESOURCE_DMA,
1420         },
1421         {
1422                 .start = CH_SPI1_RX,
1423                 .end   = CH_SPI1_RX,
1424                 .flags = IORESOURCE_DMA,
1425         },
1426
1427 };
1428
1429 /* SPI controller data */
1430 static struct bfin_spi3_master bf60x_spi_master_info0 = {
1431         .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1432         .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1433 };
1434
1435 static struct platform_device bf60x_spi_master0 = {
1436         .name = "bfin-spi3",
1437         .id = 0, /* Bus number */
1438         .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1439         .resource = bfin_spi0_resource,
1440         .dev = {
1441                 .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
1442         },
1443 };
1444
1445 static struct bfin_spi3_master bf60x_spi_master_info1 = {
1446         .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1447         .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1448 };
1449
1450 static struct platform_device bf60x_spi_master1 = {
1451         .name = "bfin-spi3",
1452         .id = 1, /* Bus number */
1453         .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1454         .resource = bfin_spi1_resource,
1455         .dev = {
1456                 .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
1457         },
1458 };
1459 #endif  /* spi master and devices */
1460
1461 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1462 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1463
1464 static struct resource bfin_twi0_resource[] = {
1465         [0] = {
1466                 .start = TWI0_CLKDIV,
1467                 .end   = TWI0_CLKDIV + 0xFF,
1468                 .flags = IORESOURCE_MEM,
1469         },
1470         [1] = {
1471                 .start = IRQ_TWI0,
1472                 .end   = IRQ_TWI0,
1473                 .flags = IORESOURCE_IRQ,
1474         },
1475 };
1476
1477 static struct platform_device i2c_bfin_twi0_device = {
1478         .name = "i2c-bfin-twi",
1479         .id = 0,
1480         .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1481         .resource = bfin_twi0_resource,
1482         .dev = {
1483                 .platform_data = &bfin_twi0_pins,
1484         },
1485 };
1486
1487 static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1488
1489 static struct resource bfin_twi1_resource[] = {
1490         [0] = {
1491                 .start = TWI1_CLKDIV,
1492                 .end   = TWI1_CLKDIV + 0xFF,
1493                 .flags = IORESOURCE_MEM,
1494         },
1495         [1] = {
1496                 .start = IRQ_TWI1,
1497                 .end   = IRQ_TWI1,
1498                 .flags = IORESOURCE_IRQ,
1499         },
1500 };
1501
1502 static struct platform_device i2c_bfin_twi1_device = {
1503         .name = "i2c-bfin-twi",
1504         .id = 1,
1505         .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1506         .resource = bfin_twi1_resource,
1507         .dev = {
1508                 .platform_data = &bfin_twi1_pins,
1509         },
1510 };
1511 #endif
1512
1513 static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1514 #if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1515         {
1516                 I2C_BOARD_INFO("adxl34x", 0x53),
1517                 .irq = IRQ_PC5,
1518                 .platform_data = (void *)&adxl34x_info,
1519         },
1520 #endif
1521 #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
1522         {
1523                 I2C_BOARD_INFO("adau1761", 0x38),
1524                 .platform_data = (void *)&adau1761_info
1525         },
1526 #endif
1527 #if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
1528         {
1529                 I2C_BOARD_INFO("ssm2602", 0x1b),
1530         },
1531 #endif
1532 };
1533
1534 static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1535 };
1536
1537 static const unsigned int cclk_vlev_datasheet[] =
1538 {
1539 /*
1540  * Internal VLEV BF54XSBBC1533
1541  ****temporarily using these values until data sheet is updated
1542  */
1543         VRPAIR(VLEV_085, 150000000),
1544         VRPAIR(VLEV_090, 250000000),
1545         VRPAIR(VLEV_110, 276000000),
1546         VRPAIR(VLEV_115, 301000000),
1547         VRPAIR(VLEV_120, 525000000),
1548         VRPAIR(VLEV_125, 550000000),
1549         VRPAIR(VLEV_130, 600000000),
1550 };
1551
1552 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1553         .tuple_tab = cclk_vlev_datasheet,
1554         .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1555         .vr_settling_time = 25 /* us */,
1556 };
1557
1558 static struct platform_device bfin_dpmc = {
1559         .name = "bfin dpmc",
1560         .dev = {
1561                 .platform_data = &bfin_dmpc_vreg_data,
1562         },
1563 };
1564
1565 static struct platform_device *ezkit_devices[] __initdata = {
1566
1567         &bfin_dpmc,
1568
1569 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1570         &rtc_device,
1571 #endif
1572
1573 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1574 #ifdef CONFIG_SERIAL_BFIN_UART0
1575         &bfin_uart0_device,
1576 #endif
1577 #ifdef CONFIG_SERIAL_BFIN_UART1
1578         &bfin_uart1_device,
1579 #endif
1580 #endif
1581
1582 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
1583 #ifdef CONFIG_BFIN_SIR0
1584         &bfin_sir0_device,
1585 #endif
1586 #ifdef CONFIG_BFIN_SIR1
1587         &bfin_sir1_device,
1588 #endif
1589 #endif
1590
1591 #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1592         &bfin_eth_device,
1593 #endif
1594
1595 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1596         &musb_device,
1597 #endif
1598
1599 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1600         &bfin_isp1760_device,
1601 #endif
1602
1603 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1604 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1605         &bfin_sport0_uart_device,
1606 #endif
1607 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1608         &bfin_sport1_uart_device,
1609 #endif
1610 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1611         &bfin_sport2_uart_device,
1612 #endif
1613 #endif
1614
1615 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1616         &bfin_can0_device,
1617 #endif
1618
1619 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1620         &bfin_nand_device,
1621 #endif
1622
1623 #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
1624         &bfin_sdh_device,
1625 #endif
1626
1627 #if IS_ENABLED(CONFIG_SPI_BFIN_V3)
1628         &bf60x_spi_master0,
1629         &bf60x_spi_master1,
1630 #endif
1631
1632 #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
1633         &bfin_rotary_device,
1634 #endif
1635
1636 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1637         &i2c_bfin_twi0_device,
1638 #if !defined(CONFIG_BF542)
1639         &i2c_bfin_twi1_device,
1640 #endif
1641 #endif
1642
1643 #if defined(CONFIG_BFIN_CRC)
1644         &bfin_crc0_device,
1645         &bfin_crc1_device,
1646 #endif
1647 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1648         &bfin_crypto_crc_device,
1649 #endif
1650
1651 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1652         &bfin_device_gpiokeys,
1653 #endif
1654
1655 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
1656         &ezkit_flash_device,
1657 #endif
1658 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1659         &bfin_i2s_pcm,
1660 #endif
1661 #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
1662         defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
1663         &bfin_i2s,
1664 #endif
1665 #if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \
1666         defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
1667         &bfin_ad1836_machine,
1668 #endif
1669 #if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
1670         defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
1671         &adau1761_device,
1672 #endif
1673 #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
1674         || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
1675         &bfin_capture_device,
1676 #endif
1677 #if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
1678         || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
1679         &bfin_display_device,
1680 #endif
1681
1682 };
1683
1684 static int __init ezkit_init(void)
1685 {
1686         printk(KERN_INFO "%s(): registering device resources\n", __func__);
1687
1688         i2c_register_board_info(0, bfin_i2c_board_info0,
1689                                 ARRAY_SIZE(bfin_i2c_board_info0));
1690         i2c_register_board_info(1, bfin_i2c_board_info1,
1691                                 ARRAY_SIZE(bfin_i2c_board_info1));
1692
1693 #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1694         if (!peripheral_request_list(pins, "emac0"))
1695                 printk(KERN_ERR "%s(): request emac pins failed\n", __func__);
1696 #endif
1697
1698         platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
1699
1700         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
1701
1702         return 0;
1703 }
1704
1705 arch_initcall(ezkit_init);
1706
1707 static struct platform_device *ezkit_early_devices[] __initdata = {
1708 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1709 #ifdef CONFIG_SERIAL_BFIN_UART0
1710         &bfin_uart0_device,
1711 #endif
1712 #ifdef CONFIG_SERIAL_BFIN_UART1
1713         &bfin_uart1_device,
1714 #endif
1715 #endif
1716
1717 #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1718 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1719         &bfin_sport0_uart_device,
1720 #endif
1721 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1722         &bfin_sport1_uart_device,
1723 #endif
1724 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1725         &bfin_sport2_uart_device,
1726 #endif
1727 #endif
1728 };
1729
1730 void __init native_machine_early_platform_add_devices(void)
1731 {
1732         printk(KERN_INFO "register early platform devices\n");
1733         early_platform_add_devices(ezkit_early_devices,
1734                 ARRAY_SIZE(ezkit_early_devices));
1735 }