2 * Blackfin cache control code
4 * Copyright 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #include <linux/linkage.h>
10 #include <asm/blackfin.h>
11 #include <asm/cache.h>
14 #ifdef CONFIG_CACHE_FLUSH_L1
20 /* 05000443 - IFLUSH cannot be last instruction in hardware loop */
22 # define BROK_FLUSH_INST "IFLUSH"
24 # define BROK_FLUSH_INST "no anomaly! yeah!"
27 /* Since all L1 caches work the same way, we use the same method for flushing
28 * them. Only the actual flush instruction differs. We write this in asm as
29 * GCC can be hard to coax into writing nice hardware loops.
31 * Also, we assume the following register setup:
35 .macro do_flush flushins:req label
39 /* start = (start & -L1_CACHE_BYTES) */
42 /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
47 /* count = (end - start) >> L1_CACHE_SHIFT */
49 R2 >>= L1_CACHE_SHIFT;
57 LSETUP (1f, 2f) LC1 = P1;
59 .ifeqs "\flushins", BROK_FLUSH_INST
71 /* Invalidate all instruction cache lines assocoiated with this memory area */
72 ENTRY(_blackfin_icache_flush_range)
74 ENDPROC(_blackfin_icache_flush_range)
76 /* Throw away all D-cached data in specified region without any obligation to
77 * write them back. Since the Blackfin ISA does not have an "invalidate"
78 * instruction, we use flush/invalidate. Perhaps as a speed optimization we
79 * could bang on the DTEST MMRs ...
81 ENTRY(_blackfin_dcache_invalidate_range)
83 ENDPROC(_blackfin_dcache_invalidate_range)
85 /* Flush all data cache lines assocoiated with this memory area */
86 ENTRY(_blackfin_dcache_flush_range)
88 ENDPROC(_blackfin_dcache_flush_range)
90 /* Our headers convert the page structure to an address, so just need to flush
91 * its contents like normal. We know the start address is page aligned (which
92 * greater than our cache alignment), as is the end address. So just jump into
93 * the middle of the dcache flush function.
95 ENTRY(_blackfin_dflush_page)
96 P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
98 ENDPROC(_blackfin_dflush_page)