2 * File: arch/blackfin/mach-common/dpmc.S
4 * Author: LG Soft India
7 * Description: Watchdog Timer APIs
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/linkage.h>
31 #include <asm/blackfin.h>
32 #include <asm/mach/irq.h>
36 ENTRY(_unmask_wdog_wakeup_evt)
37 [--SP] = ( R7:0, P5:0 );
38 #if defined(CONFIG_BF561)
41 #elif defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
49 #if defined(CONFIG_BF561)
52 BITSET(R7,(IRQ_WATCH - IVG7));
57 ( R7:0, P5:0 ) = [SP++];
61 /* When watch dog timer is enabled, a write to STAT will load the
62 * contents of CNT to STAT
65 #if defined(CONFIG_BF561)
66 P0.h = HI(WDOGA_STAT);
67 P0.l = LO(WDOGA_STAT);
74 JUMP .LSKIP_WRITE_TO_STAT;
76 ENTRY(_program_wdog_timer)
77 [--SP] = ( R7:0, P5:0 );
78 #if defined(CONFIG_BF561)
88 #if defined(CONFIG_BF561)
97 if !CC JUMP .LWRITE_TO_STAT;
99 if !CC JUMP .LWRITE_TO_STAT;
101 .LSKIP_WRITE_TO_STAT:
102 #if defined(CONFIG_BF561)
103 P0.h = HI(WDOGA_CTL);
104 P0.l = LO(WDOGA_CTL);
110 BITCLR(R7,1); /* Enable GP event */
117 BITCLR(R7,4); /* Enable the wdog counter */
121 ( R7:0, P5:0 ) = [SP++];
124 ENTRY(_clear_wdog_wakeup_evt)
125 [--SP] = ( R7:0, P5:0 );
127 #if defined(CONFIG_BF561)
128 P0.h = HI(WDOGA_CTL);
129 P0.l = LO(WDOGA_CTL);
149 ( R7:0, P5:0 ) = [SP++];
152 ENTRY(_disable_wdog_timer)
153 [--SP] = ( R7:0, P5:0 );
154 #if defined(CONFIG_BF561)
155 P0.h = HI(WDOGA_CTL);
156 P0.l = LO(WDOGA_CTL);
164 ( R7:0, P5:0 ) = [SP++];
167 #if !defined(CONFIG_BF561)
172 [--SP] = ( R7:0, P5:0 );
191 call _test_pll_locked;
203 call _test_pll_locked;
206 ( R7:0, P5:0 ) = [SP++];
209 ENTRY(_hibernate_mode)
210 [--SP] = ( R7:0, P5:0 );
230 /* Actually, adding anything may not be necessary...SDRAM contents
235 [--SP] = ( R7:0, P5:0 );
244 /* Clear all the interrupts,bits sticky */
254 call _test_pll_locked;
259 call _unset_dram_srfs;
261 call _test_pll_locked;
274 call _test_pll_locked;
279 ( R7:0, P5:0 ) = [SP++];
283 [--SP] = ( R7:0, P5:0 );
293 /* Clear all the interrupts,bits sticky */
306 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
312 call _test_pll_locked;
322 R2 = DEPOSIT(R7, R1);
328 call _test_pll_locked;
342 call _test_pll_locked;
354 call _test_pll_locked;
364 call _test_pll_locked;
366 call _unset_dram_srfs;
371 ( R7:0, P5:0 ) = [SP++];
374 ENTRY(_set_dram_srfs)
375 /* set the dram to self refresh mode */
376 #if defined(CONFIG_BF54x)
377 P0.H = hi(EBIU_RSTCTL);
378 P0.L = lo(EBIU_RSTCTL);
383 P0.H = hi(EBIU_SDGCTL);
384 P0.L = lo(EBIU_SDGCTL);
392 #if defined(CONFIG_BF54x)
396 if !CC JUMP .LSRR_MODE;
400 ENTRY(_unset_dram_srfs)
401 /* set the dram out of self refresh mode */
402 #if defined(CONFIG_BF54x)
403 P0.H = hi(EBIU_RSTCTL);
404 P0.L = lo(EBIU_RSTCTL);
409 P0.H = hi(EBIU_SDGCTL);
410 P0.L = lo(EBIU_SDGCTL);
422 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
433 ENTRY(_set_rtc_istat)
434 P0.H = hi(RTC_ISTAT);
435 P0.L = lo(RTC_ISTAT);
440 ENTRY(_test_pll_locked)