2 * Set up the interrupt priorities
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
11 * Licensed under the GPL-2
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
19 #include <linux/ipipe.h>
22 #include <linux/kgdb.h>
24 #include <asm/traps.h>
25 #include <asm/blackfin.h>
27 #include <asm/irq_handler.h>
29 #include <asm/bfin5xx_spi.h>
30 #include <asm/bfin_sport.h>
31 #include <asm/bfin_can.h>
33 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
36 # define BF537_GENERIC_ERROR_INT_DEMUX
37 # define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
38 # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
39 # define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
40 # define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
41 # define UART_ERR_MASK (0x6) /* UART_IIR */
42 # define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
44 # undef BF537_GENERIC_ERROR_INT_DEMUX
49 * - we have separated the physical Hardware interrupt from the
50 * levels that the LINUX kernel sees (see the description in irq.h)
55 /* Initialize this to an actual value to force it into the .data
56 * section so that we know it is properly initialized at entry into
57 * the kernel but before bss is initialized to zero (which is where
58 * it would live otherwise). The 0x1f magic represents the IRQs we
59 * cannot actually mask out in hardware.
61 unsigned long bfin_irq_flags = 0x1f;
62 EXPORT_SYMBOL(bfin_irq_flags);
65 /* The number of spurious interrupts */
66 atomic_t num_spurious;
69 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
74 /* irq number for request_irq, available in mach-bf5xx/irq.h */
76 /* corresponding bit in the SIC_ISR register */
78 } ivg_table[NR_PERI_INTS];
81 /* position of first irq in ivg_table for given ivg */
84 } ivg7_13[IVG13 - IVG7 + 1];
88 * Search SIC_IAR and fill tables with the irqvalues
89 * and their positions in the SIC_ISR register.
91 static void __init search_IAR(void)
93 unsigned ivg, irq_pos = 0;
94 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
97 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
99 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
101 u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
102 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
103 defined(CONFIG_BF538) || defined(CONFIG_BF539)
104 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
110 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
111 int iar_shift = (irqn & 7) * 4;
112 if (ivg == (0xf & (iar >> iar_shift))) {
113 ivg_table[irq_pos].irqno = IVG7 + irqn;
114 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
115 ivg7_13[ivg].istop++;
124 * This is for core internal IRQs
127 static void bfin_ack_noop(unsigned int irq)
129 /* Dummy function. */
132 static void bfin_core_mask_irq(unsigned int irq)
134 bfin_irq_flags &= ~(1 << irq);
135 if (!hard_irqs_disabled())
136 hard_local_irq_enable();
139 static void bfin_core_unmask_irq(unsigned int irq)
141 bfin_irq_flags |= 1 << irq;
143 * If interrupts are enabled, IMASK must contain the same value
144 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
145 * are currently disabled we need not do anything; one of the
146 * callers will take care of setting IMASK to the proper value
147 * when reenabling interrupts.
148 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
151 if (!hard_irqs_disabled())
152 hard_local_irq_enable();
156 static void bfin_internal_mask_irq(unsigned int irq)
161 flags = hard_local_irq_save();
162 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
163 ~(1 << SIC_SYSIRQ(irq)));
165 unsigned mask_bank, mask_bit;
166 flags = hard_local_irq_save();
167 mask_bank = SIC_SYSIRQ(irq) / 32;
168 mask_bit = SIC_SYSIRQ(irq) % 32;
169 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
172 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
176 hard_local_irq_restore(flags);
180 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
181 const struct cpumask *affinity)
183 static void bfin_internal_unmask_irq(unsigned int irq)
189 flags = hard_local_irq_save();
190 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
191 (1 << SIC_SYSIRQ(irq)));
193 unsigned mask_bank, mask_bit;
194 flags = hard_local_irq_save();
195 mask_bank = SIC_SYSIRQ(irq) / 32;
196 mask_bit = SIC_SYSIRQ(irq) % 32;
198 if (cpumask_test_cpu(0, affinity))
200 bfin_write_SIC_IMASK(mask_bank,
201 bfin_read_SIC_IMASK(mask_bank) |
204 if (cpumask_test_cpu(1, affinity))
205 bfin_write_SICB_IMASK(mask_bank,
206 bfin_read_SICB_IMASK(mask_bank) |
210 hard_local_irq_restore(flags);
214 static void bfin_internal_unmask_irq(unsigned int irq)
216 struct irq_desc *desc = irq_to_desc(irq);
217 bfin_internal_unmask_irq_affinity(irq, desc->affinity);
220 static int bfin_internal_set_affinity(unsigned int irq, const struct cpumask *mask)
222 bfin_internal_mask_irq(irq);
223 bfin_internal_unmask_irq_affinity(irq, mask);
230 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
232 u32 bank, bit, wakeup = 0;
234 bank = SIC_SYSIRQ(irq) / 32;
235 bit = SIC_SYSIRQ(irq) % 32;
267 flags = hard_local_irq_save();
270 bfin_sic_iwr[bank] |= (1 << bit);
274 bfin_sic_iwr[bank] &= ~(1 << bit);
275 vr_wakeup &= ~wakeup;
278 hard_local_irq_restore(flags);
284 static struct irq_chip bfin_core_irqchip = {
286 .ack = bfin_ack_noop,
287 .mask = bfin_core_mask_irq,
288 .unmask = bfin_core_unmask_irq,
291 static struct irq_chip bfin_internal_irqchip = {
293 .ack = bfin_ack_noop,
294 .mask = bfin_internal_mask_irq,
295 .unmask = bfin_internal_unmask_irq,
296 .mask_ack = bfin_internal_mask_irq,
297 .disable = bfin_internal_mask_irq,
298 .enable = bfin_internal_unmask_irq,
300 .set_affinity = bfin_internal_set_affinity,
303 .set_wake = bfin_internal_set_wake,
307 static void bfin_handle_irq(unsigned irq)
310 struct pt_regs regs; /* Contents not used. */
311 ipipe_trace_irq_entry(irq);
312 __ipipe_handle_irq(irq, ®s);
313 ipipe_trace_irq_exit(irq);
314 #else /* !CONFIG_IPIPE */
315 struct irq_desc *desc = irq_desc + irq;
316 desc->handle_irq(irq, desc);
317 #endif /* !CONFIG_IPIPE */
320 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
321 static int error_int_mask;
323 static void bfin_generic_error_mask_irq(unsigned int irq)
325 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
327 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
330 static void bfin_generic_error_unmask_irq(unsigned int irq)
332 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
333 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
336 static struct irq_chip bfin_generic_error_irqchip = {
338 .ack = bfin_ack_noop,
339 .mask_ack = bfin_generic_error_mask_irq,
340 .mask = bfin_generic_error_mask_irq,
341 .unmask = bfin_generic_error_unmask_irq,
344 static void bfin_demux_error_irq(unsigned int int_err_irq,
345 struct irq_desc *inta_desc)
349 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
350 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
354 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
355 irq = IRQ_SPORT0_ERROR;
356 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
357 irq = IRQ_SPORT1_ERROR;
358 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
360 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
362 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
364 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
365 irq = IRQ_UART0_ERROR;
366 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
367 irq = IRQ_UART1_ERROR;
370 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
371 bfin_handle_irq(irq);
376 bfin_write_PPI_STATUS(PPI_ERR_MASK);
378 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
380 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
383 case IRQ_SPORT0_ERROR:
384 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
387 case IRQ_SPORT1_ERROR:
388 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
392 bfin_write_CAN_GIS(CAN_ERR_MASK);
396 bfin_write_SPI_STAT(SPI_ERR_MASK);
404 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
409 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
410 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
411 __func__, __FILE__, __LINE__);
414 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
416 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
417 static int mac_stat_int_mask;
419 static void bfin_mac_status_ack_irq(unsigned int irq)
423 bfin_write_EMAC_MMC_TIRQS(
424 bfin_read_EMAC_MMC_TIRQE() &
425 bfin_read_EMAC_MMC_TIRQS());
426 bfin_write_EMAC_MMC_RIRQS(
427 bfin_read_EMAC_MMC_RIRQE() &
428 bfin_read_EMAC_MMC_RIRQS());
430 case IRQ_MAC_RXFSINT:
431 bfin_write_EMAC_RX_STKY(
432 bfin_read_EMAC_RX_IRQE() &
433 bfin_read_EMAC_RX_STKY());
435 case IRQ_MAC_TXFSINT:
436 bfin_write_EMAC_TX_STKY(
437 bfin_read_EMAC_TX_IRQE() &
438 bfin_read_EMAC_TX_STKY());
440 case IRQ_MAC_WAKEDET:
441 bfin_write_EMAC_WKUP_CTL(
442 bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
445 /* These bits are W1C */
446 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
451 static void bfin_mac_status_mask_irq(unsigned int irq)
453 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
454 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
457 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
463 if (!mac_stat_int_mask)
464 bfin_internal_mask_irq(IRQ_MAC_ERROR);
466 bfin_mac_status_ack_irq(irq);
469 static void bfin_mac_status_unmask_irq(unsigned int irq)
471 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
474 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
480 if (!mac_stat_int_mask)
481 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
483 mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
487 int bfin_mac_status_set_wake(unsigned int irq, unsigned int state)
489 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
490 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
492 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
497 static struct irq_chip bfin_mac_status_irqchip = {
499 .ack = bfin_ack_noop,
500 .mask_ack = bfin_mac_status_mask_irq,
501 .mask = bfin_mac_status_mask_irq,
502 .unmask = bfin_mac_status_unmask_irq,
504 .set_wake = bfin_mac_status_set_wake,
508 static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
509 struct irq_desc *inta_desc)
512 u32 status = bfin_read_EMAC_SYSTAT();
514 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
515 if (status & (1L << i)) {
516 irq = IRQ_MAC_PHYINT + i;
521 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
522 bfin_handle_irq(irq);
524 bfin_mac_status_ack_irq(irq);
526 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
531 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
532 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
533 "(EMAC_SYSTAT=0x%X)\n",
534 __func__, __FILE__, __LINE__, status);
538 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
541 _set_irq_handler(irq, handle_level_irq);
543 struct irq_desc *desc = irq_desc + irq;
544 /* May not call generic set_irq_handler() due to spinlock
546 desc->handle_irq = handle;
550 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
551 extern void bfin_gpio_irq_prepare(unsigned gpio);
553 #if !defined(CONFIG_BF54x)
555 static void bfin_gpio_ack_irq(unsigned int irq)
557 /* AFAIK ack_irq in case mask_ack is provided
558 * get's only called for edge sense irqs
560 set_gpio_data(irq_to_gpio(irq), 0);
563 static void bfin_gpio_mask_ack_irq(unsigned int irq)
565 struct irq_desc *desc = irq_desc + irq;
566 u32 gpionr = irq_to_gpio(irq);
568 if (desc->handle_irq == handle_edge_irq)
569 set_gpio_data(gpionr, 0);
571 set_gpio_maska(gpionr, 0);
574 static void bfin_gpio_mask_irq(unsigned int irq)
576 set_gpio_maska(irq_to_gpio(irq), 0);
579 static void bfin_gpio_unmask_irq(unsigned int irq)
581 set_gpio_maska(irq_to_gpio(irq), 1);
584 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
586 u32 gpionr = irq_to_gpio(irq);
588 if (__test_and_set_bit(gpionr, gpio_enabled))
589 bfin_gpio_irq_prepare(gpionr);
591 bfin_gpio_unmask_irq(irq);
596 static void bfin_gpio_irq_shutdown(unsigned int irq)
598 u32 gpionr = irq_to_gpio(irq);
600 bfin_gpio_mask_irq(irq);
601 __clear_bit(gpionr, gpio_enabled);
602 bfin_gpio_irq_free(gpionr);
605 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
609 u32 gpionr = irq_to_gpio(irq);
611 if (type == IRQ_TYPE_PROBE) {
612 /* only probe unenabled GPIO interrupt lines */
613 if (test_bit(gpionr, gpio_enabled))
615 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
618 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
619 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
621 snprintf(buf, 16, "gpio-irq%d", irq);
622 ret = bfin_gpio_irq_request(gpionr, buf);
626 if (__test_and_set_bit(gpionr, gpio_enabled))
627 bfin_gpio_irq_prepare(gpionr);
630 __clear_bit(gpionr, gpio_enabled);
634 set_gpio_inen(gpionr, 0);
635 set_gpio_dir(gpionr, 0);
637 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
638 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
639 set_gpio_both(gpionr, 1);
641 set_gpio_both(gpionr, 0);
643 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
644 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
646 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
648 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
649 set_gpio_edge(gpionr, 1);
650 set_gpio_inen(gpionr, 1);
651 set_gpio_data(gpionr, 0);
654 set_gpio_edge(gpionr, 0);
655 set_gpio_inen(gpionr, 1);
658 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
659 bfin_set_irq_handler(irq, handle_edge_irq);
661 bfin_set_irq_handler(irq, handle_level_irq);
667 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
669 return gpio_pm_wakeup_ctrl(irq_to_gpio(irq), state);
673 static void bfin_demux_gpio_irq(unsigned int inta_irq,
674 struct irq_desc *desc)
676 unsigned int i, gpio, mask, irq, search = 0;
679 #if defined(CONFIG_BF53x)
684 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
689 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
693 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
703 #elif defined(CONFIG_BF561)
720 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
723 mask = get_gpiop_data(i) & get_gpiop_maska(i);
727 bfin_handle_irq(irq);
733 gpio = irq_to_gpio(irq);
734 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
738 bfin_handle_irq(irq);
746 #else /* CONFIG_BF54x */
748 #define NR_PINT_SYS_IRQS 4
749 #define NR_PINT_BITS 32
751 #define IRQ_NOT_AVAIL 0xFF
753 #define PINT_2_BANK(x) ((x) >> 5)
754 #define PINT_2_BIT(x) ((x) & 0x1F)
755 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
757 static unsigned char irq2pint_lut[NR_PINTS];
758 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
761 unsigned int mask_set;
762 unsigned int mask_clear;
763 unsigned int request;
765 unsigned int edge_set;
766 unsigned int edge_clear;
767 unsigned int invert_set;
768 unsigned int invert_clear;
769 unsigned int pinstate;
773 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
774 (struct pin_int_t *)PINT0_MASK_SET,
775 (struct pin_int_t *)PINT1_MASK_SET,
776 (struct pin_int_t *)PINT2_MASK_SET,
777 (struct pin_int_t *)PINT3_MASK_SET,
780 inline unsigned int get_irq_base(u32 bank, u8 bmap)
782 unsigned int irq_base;
784 if (bank < 2) { /*PA-PB */
785 irq_base = IRQ_PA0 + bmap * 16;
787 irq_base = IRQ_PC0 + bmap * 16;
793 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
794 void init_pint_lut(void)
796 u16 bank, bit, irq_base, bit_pos;
800 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
802 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
804 pint_assign = pint[bank]->assign;
806 for (bit = 0; bit < NR_PINT_BITS; bit++) {
808 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
810 irq_base = get_irq_base(bank, bmap);
812 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
813 bit_pos = bit + bank * NR_PINT_BITS;
815 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
816 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
821 static void bfin_gpio_ack_irq(unsigned int irq)
823 struct irq_desc *desc = irq_desc + irq;
824 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
825 u32 pintbit = PINT_BIT(pint_val);
826 u32 bank = PINT_2_BANK(pint_val);
828 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
829 if (pint[bank]->invert_set & pintbit)
830 pint[bank]->invert_clear = pintbit;
832 pint[bank]->invert_set = pintbit;
834 pint[bank]->request = pintbit;
838 static void bfin_gpio_mask_ack_irq(unsigned int irq)
840 struct irq_desc *desc = irq_desc + irq;
841 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
842 u32 pintbit = PINT_BIT(pint_val);
843 u32 bank = PINT_2_BANK(pint_val);
845 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
846 if (pint[bank]->invert_set & pintbit)
847 pint[bank]->invert_clear = pintbit;
849 pint[bank]->invert_set = pintbit;
852 pint[bank]->request = pintbit;
853 pint[bank]->mask_clear = pintbit;
856 static void bfin_gpio_mask_irq(unsigned int irq)
858 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
860 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
863 static void bfin_gpio_unmask_irq(unsigned int irq)
865 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
866 u32 pintbit = PINT_BIT(pint_val);
867 u32 bank = PINT_2_BANK(pint_val);
869 pint[bank]->request = pintbit;
870 pint[bank]->mask_set = pintbit;
873 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
875 u32 gpionr = irq_to_gpio(irq);
876 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
878 if (pint_val == IRQ_NOT_AVAIL) {
880 "GPIO IRQ %d :Not in PINT Assign table "
881 "Reconfigure Interrupt to Port Assignemt\n", irq);
885 if (__test_and_set_bit(gpionr, gpio_enabled))
886 bfin_gpio_irq_prepare(gpionr);
888 bfin_gpio_unmask_irq(irq);
893 static void bfin_gpio_irq_shutdown(unsigned int irq)
895 u32 gpionr = irq_to_gpio(irq);
897 bfin_gpio_mask_irq(irq);
898 __clear_bit(gpionr, gpio_enabled);
899 bfin_gpio_irq_free(gpionr);
902 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
906 u32 gpionr = irq_to_gpio(irq);
907 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
908 u32 pintbit = PINT_BIT(pint_val);
909 u32 bank = PINT_2_BANK(pint_val);
911 if (pint_val == IRQ_NOT_AVAIL)
914 if (type == IRQ_TYPE_PROBE) {
915 /* only probe unenabled GPIO interrupt lines */
916 if (test_bit(gpionr, gpio_enabled))
918 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
921 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
922 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
924 snprintf(buf, 16, "gpio-irq%d", irq);
925 ret = bfin_gpio_irq_request(gpionr, buf);
929 if (__test_and_set_bit(gpionr, gpio_enabled))
930 bfin_gpio_irq_prepare(gpionr);
933 __clear_bit(gpionr, gpio_enabled);
937 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
938 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
940 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
942 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
943 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
944 if (gpio_get_value(gpionr))
945 pint[bank]->invert_set = pintbit;
947 pint[bank]->invert_clear = pintbit;
950 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
951 pint[bank]->edge_set = pintbit;
952 bfin_set_irq_handler(irq, handle_edge_irq);
954 pint[bank]->edge_clear = pintbit;
955 bfin_set_irq_handler(irq, handle_level_irq);
962 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
963 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
965 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
968 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
969 u32 bank = PINT_2_BANK(pint_val);
970 u32 pintbit = PINT_BIT(pint_val);
974 pint_irq = IRQ_PINT0;
977 pint_irq = IRQ_PINT2;
980 pint_irq = IRQ_PINT3;
983 pint_irq = IRQ_PINT1;
989 bfin_internal_set_wake(pint_irq, state);
992 pint_wakeup_masks[bank] |= pintbit;
994 pint_wakeup_masks[bank] &= ~pintbit;
999 u32 bfin_pm_setup(void)
1003 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1004 val = pint[i]->mask_clear;
1005 pint_saved_masks[i] = val;
1006 if (val ^ pint_wakeup_masks[i]) {
1007 pint[i]->mask_clear = val;
1008 pint[i]->mask_set = pint_wakeup_masks[i];
1015 void bfin_pm_restore(void)
1019 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1020 val = pint_saved_masks[i];
1021 if (val ^ pint_wakeup_masks[i]) {
1022 pint[i]->mask_clear = pint[i]->mask_clear;
1023 pint[i]->mask_set = val;
1029 static void bfin_demux_gpio_irq(unsigned int inta_irq,
1030 struct irq_desc *desc)
1052 pint_val = bank * NR_PINT_BITS;
1054 request = pint[bank]->request;
1058 irq = pint2irq_lut[pint_val] + SYS_IRQS;
1059 bfin_handle_irq(irq);
1068 static struct irq_chip bfin_gpio_irqchip = {
1070 .ack = bfin_gpio_ack_irq,
1071 .mask = bfin_gpio_mask_irq,
1072 .mask_ack = bfin_gpio_mask_ack_irq,
1073 .unmask = bfin_gpio_unmask_irq,
1074 .disable = bfin_gpio_mask_irq,
1075 .enable = bfin_gpio_unmask_irq,
1076 .set_type = bfin_gpio_irq_type,
1077 .startup = bfin_gpio_irq_startup,
1078 .shutdown = bfin_gpio_irq_shutdown,
1080 .set_wake = bfin_gpio_set_wake,
1084 void __cpuinit init_exception_vectors(void)
1086 /* cannot program in software:
1087 * evt0 - emulation (jtag)
1090 bfin_write_EVT2(evt_nmi);
1091 bfin_write_EVT3(trap);
1092 bfin_write_EVT5(evt_ivhw);
1093 bfin_write_EVT6(evt_timer);
1094 bfin_write_EVT7(evt_evt7);
1095 bfin_write_EVT8(evt_evt8);
1096 bfin_write_EVT9(evt_evt9);
1097 bfin_write_EVT10(evt_evt10);
1098 bfin_write_EVT11(evt_evt11);
1099 bfin_write_EVT12(evt_evt12);
1100 bfin_write_EVT13(evt_evt13);
1101 bfin_write_EVT14(evt_evt14);
1102 bfin_write_EVT15(evt_system_call);
1107 * This function should be called during kernel startup to initialize
1108 * the BFin IRQ handling routines.
1111 int __init init_arch_irq(void)
1114 unsigned long ilat = 0;
1115 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
1116 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1117 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1118 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1119 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1120 # ifdef CONFIG_BF54x
1121 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1124 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1125 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1128 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1131 local_irq_disable();
1133 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1134 /* Clear EMAC Interrupt Status bits so we can demux it later */
1135 bfin_write_EMAC_SYSTAT(-1);
1139 # ifdef CONFIG_PINTx_REASSIGN
1140 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1141 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1142 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1143 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1145 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1149 for (irq = 0; irq <= SYS_IRQS; irq++) {
1150 if (irq <= IRQ_CORETMR)
1151 set_irq_chip(irq, &bfin_core_irqchip);
1153 set_irq_chip(irq, &bfin_internal_irqchip);
1156 #if defined(CONFIG_BF53x)
1158 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1161 #elif defined(CONFIG_BF54x)
1166 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1167 case IRQ_PORTF_INTA:
1168 case IRQ_PORTG_INTA:
1169 case IRQ_PORTH_INTA:
1170 #elif defined(CONFIG_BF561)
1171 case IRQ_PROG0_INTA:
1172 case IRQ_PROG1_INTA:
1173 case IRQ_PROG2_INTA:
1174 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1175 case IRQ_PORTF_INTA:
1177 set_irq_chained_handler(irq,
1178 bfin_demux_gpio_irq);
1180 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1181 case IRQ_GENERIC_ERROR:
1182 set_irq_chained_handler(irq, bfin_demux_error_irq);
1185 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1187 set_irq_chained_handler(irq, bfin_demux_mac_status_irq);
1193 set_irq_handler(irq, handle_percpu_irq);
1197 #ifdef CONFIG_TICKSOURCE_CORETMR
1200 set_irq_handler(irq, handle_percpu_irq);
1203 set_irq_handler(irq, handle_simple_irq);
1208 #ifdef CONFIG_TICKSOURCE_GPTMR0
1210 set_irq_handler(irq, handle_simple_irq);
1216 set_irq_handler(irq, handle_level_irq);
1218 #else /* !CONFIG_IPIPE */
1220 set_irq_handler(irq, handle_simple_irq);
1222 #endif /* !CONFIG_IPIPE */
1226 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1227 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1228 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1230 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1231 set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1235 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1236 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1237 set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip,
1240 /* if configured as edge, then will be changed to do_edge_IRQ */
1241 for (irq = GPIO_IRQ_BASE;
1242 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1243 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1246 bfin_write_IMASK(0);
1248 ilat = bfin_read_ILAT();
1250 bfin_write_ILAT(ilat);
1253 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1254 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1255 * local_irq_enable()
1258 /* Therefore it's better to setup IARs before interrupts enabled */
1261 /* Enable interrupts IVG7-15 */
1262 bfin_irq_flags |= IMASK_IVG15 |
1263 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1264 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1266 /* This implicitly covers ANOMALY_05000171
1267 * Boot-ROM code modifies SICA_IWRx wakeup registers
1270 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1272 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1273 * will screw up the bootrom as it relies on MDMA0/1 waking it
1274 * up from IDLE instructions. See this report for more info:
1275 * http://blackfin.uclinux.org/gf/tracker/4323
1277 if (ANOMALY_05000435)
1278 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1280 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1283 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1286 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1292 #ifdef CONFIG_DO_IRQ_L1
1293 __attribute__((l1_text))
1295 void do_irq(int vec, struct pt_regs *fp)
1297 if (vec == EVT_IVTMR_P) {
1300 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1301 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1302 #if defined(SIC_ISR0)
1303 unsigned long sic_status[3];
1305 if (smp_processor_id()) {
1307 /* This will be optimized out in UP mode. */
1308 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1309 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1312 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1313 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1316 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1319 if (ivg >= ivg_stop) {
1320 atomic_inc(&num_spurious);
1323 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1327 unsigned long sic_status;
1329 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1332 if (ivg >= ivg_stop) {
1333 atomic_inc(&num_spurious);
1335 } else if (sic_status & ivg->isrflag)
1341 asm_do_IRQ(vec, fp);
1346 int __ipipe_get_irq_priority(unsigned irq)
1350 if (irq <= IRQ_CORETMR)
1353 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1354 struct ivgx *ivg = ivg_table + ient;
1355 if (ivg->irqno == irq) {
1356 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1357 if (ivg7_13[prio].ifirst <= ivg &&
1358 ivg7_13[prio].istop > ivg)
1367 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1368 #ifdef CONFIG_DO_IRQ_L1
1369 __attribute__((l1_text))
1371 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1373 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1374 struct ipipe_domain *this_domain = __ipipe_current_domain;
1375 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1376 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1379 if (likely(vec == EVT_IVTMR_P))
1382 #if defined(SIC_ISR0)
1383 unsigned long sic_status[3];
1385 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1386 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1388 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1391 if (ivg >= ivg_stop) {
1392 atomic_inc(&num_spurious);
1395 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1399 unsigned long sic_status;
1401 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1404 if (ivg >= ivg_stop) {
1405 atomic_inc(&num_spurious);
1407 } else if (sic_status & ivg->isrflag)
1414 if (irq == IRQ_SYSTMR) {
1415 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1416 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1418 /* This is basically what we need from the register frame. */
1419 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1420 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1421 if (this_domain != ipipe_root_domain)
1422 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1424 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1427 if (this_domain == ipipe_root_domain) {
1428 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1432 ipipe_trace_irq_entry(irq);
1433 __ipipe_handle_irq(irq, regs);
1434 ipipe_trace_irq_exit(irq);
1436 if (this_domain == ipipe_root_domain) {
1437 set_thread_flag(TIF_IRQ_SYNC);
1439 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1440 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1447 #endif /* CONFIG_IPIPE */