arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * Set up the interrupt priorities
   3  *
   4  * Copyright  2004-2009 Analog Devices Inc.
   5  *                 2003 Bas Vermeulen <bas@buyways.nl>
   6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
   7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
   8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *                 1996 Roman Zippel
  10  *
  11  * Licensed under the GPL-2
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/irq.h>
  18 #ifdef CONFIG_IPIPE
  19 #include <linux/ipipe.h>
  20 #endif
  21 #ifdef CONFIG_KGDB
  22 #include <linux/kgdb.h>
  23 #endif
  24 #include <asm/traps.h>
  25 #include <asm/blackfin.h>
  26 #include <asm/gpio.h>
  27 #include <asm/irq_handler.h>
  28 #include <asm/dpmc.h>
  29 #include <asm/bfin5xx_spi.h>
  30 #include <asm/bfin_sport.h>
  31 #include <asm/bfin_can.h>
  32
  33 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
  34
  35 #ifdef BF537_FAMILY
  36 # define BF537_GENERIC_ERROR_INT_DEMUX
  37 # define SPI_ERR_MASK   (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
  38 # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)     /* SPORT_STAT */
  39 # define PPI_ERR_MASK   (0xFFFF & ~FLD) /* PPI_STATUS */
  40 # define EMAC_ERR_MASK  (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
  41 # define UART_ERR_MASK  (0x6)   /* UART_IIR */
  42 # define CAN_ERR_MASK   (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)      /* CAN_GIF */
  43 #else
  44 # undef BF537_GENERIC_ERROR_INT_DEMUX
  45 #endif
  46
  47 /*
  48  * NOTES:
  49  * - we have separated the physical Hardware interrupt from the
  50  * levels that the LINUX kernel sees (see the description in irq.h)
  51  * -
  52  */
  53
  54 #ifndef CONFIG_SMP
  55 /* Initialize this to an actual value to force it into the .data
  56  * section so that we know it is properly initialized at entry into
  57  * the kernel but before bss is initialized to zero (which is where
  58  * it would live otherwise).  The 0x1f magic represents the IRQs we
  59  * cannot actually mask out in hardware.
  60  */
  61 unsigned long bfin_irq_flags = 0x1f;
  62 EXPORT_SYMBOL(bfin_irq_flags);
  63 #endif
  64
  65 /* The number of spurious interrupts */
  66 atomic_t num_spurious;
  67
  68 #ifdef CONFIG_PM
  69 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  70 unsigned vr_wakeup;
  71 #endif
  72
  73 struct ivgx {
  74         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  75         unsigned int irqno;
  76         /* corresponding bit in the SIC_ISR register */
  77         unsigned int isrflag;
  78 } ivg_table[NR_PERI_INTS];
  79
  80 struct ivg_slice {
  81         /* position of first irq in ivg_table for given ivg */
  82         struct ivgx *ifirst;
  83         struct ivgx *istop;
  84 } ivg7_13[IVG13 - IVG7 + 1];
  85
  86
  87 /*
  88  * Search SIC_IAR and fill tables with the irqvalues
  89  * and their positions in the SIC_ISR register.
  90  */
  91 static void __init search_IAR(void)
  92 {
  93         unsigned ivg, irq_pos = 0;
  94         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  95                 int irqn;
  96
  97                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  98
  99                 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
 100                         int iar_shift = (irqn & 7) * 4;
 101                                 if (ivg == (0xf &
 102 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
 103         || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
 104                              bfin_read32((unsigned long *)SIC_IAR0 +
 105                                          ((irqn % 32) >> 3) + ((irqn / 32) *
 106                                          ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
 107 #else
 108                              bfin_read32((unsigned long *)SIC_IAR0 +
 109                                          (irqn >> 3)) >> iar_shift)) {
 110 #endif
 111                                 ivg_table[irq_pos].irqno = IVG7 + irqn;
 112                                 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 113                                 ivg7_13[ivg].istop++;
 114                                 irq_pos++;
 115                         }
 116                 }
 117         }
 118 }
 119
 120 /*
 121  * This is for core internal IRQs
 122  */
 123
 124 static void bfin_ack_noop(unsigned int irq)
 125 {
 126         /* Dummy function.  */
 127 }
 128
 129 static void bfin_core_mask_irq(unsigned int irq)
 130 {
 131         bfin_irq_flags &= ~(1 << irq);
 132         if (!irqs_disabled_hw())
 133                 local_irq_enable_hw();
 134 }
 135
 136 static void bfin_core_unmask_irq(unsigned int irq)
 137 {
 138         bfin_irq_flags |= 1 << irq;
 139         /*
 140          * If interrupts are enabled, IMASK must contain the same value
 141          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 142          * are currently disabled we need not do anything; one of the
 143          * callers will take care of setting IMASK to the proper value
 144          * when reenabling interrupts.
 145          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 146          * what we need.
 147          */
 148         if (!irqs_disabled_hw())
 149                 local_irq_enable_hw();
 150         return;
 151 }
 152
 153 static void bfin_internal_mask_irq(unsigned int irq)
 154 {
 155         unsigned long flags;
 156
 157 #ifdef CONFIG_BF53x
 158         local_irq_save_hw(flags);
 159         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 160                              ~(1 << SIC_SYSIRQ(irq)));
 161 #else
 162         unsigned mask_bank, mask_bit;
 163         local_irq_save_hw(flags);
 164         mask_bank = SIC_SYSIRQ(irq) / 32;
 165         mask_bit = SIC_SYSIRQ(irq) % 32;
 166         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 167                              ~(1 << mask_bit));
 168 #ifdef CONFIG_SMP
 169         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 170                              ~(1 << mask_bit));
 171 #endif
 172 #endif
 173         local_irq_restore_hw(flags);
 174 }
 175
 176 #ifdef CONFIG_SMP
 177 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
 178                 const struct cpumask *affinity)
 179 #else
 180 static void bfin_internal_unmask_irq(unsigned int irq)
 181 #endif
 182 {
 183         unsigned long flags;
 184
 185 #ifdef CONFIG_BF53x
 186         local_irq_save_hw(flags);
 187         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 188                              (1 << SIC_SYSIRQ(irq)));
 189 #else
 190         unsigned mask_bank, mask_bit;
 191         local_irq_save_hw(flags);
 192         mask_bank = SIC_SYSIRQ(irq) / 32;
 193         mask_bit = SIC_SYSIRQ(irq) % 32;
 194 #ifdef CONFIG_SMP
 195         if (cpumask_test_cpu(0, affinity))
 196 #endif
 197                 bfin_write_SIC_IMASK(mask_bank,
 198                         bfin_read_SIC_IMASK(mask_bank) |
 199                         (1 << mask_bit));
 200 #ifdef CONFIG_SMP
 201         if (cpumask_test_cpu(1, affinity))
 202                 bfin_write_SICB_IMASK(mask_bank,
 203                         bfin_read_SICB_IMASK(mask_bank) |
 204                         (1 << mask_bit));
 205 #endif
 206 #endif
 207         local_irq_restore_hw(flags);
 208 }
 209
 210 #ifdef CONFIG_SMP
 211 static void bfin_internal_unmask_irq(unsigned int irq)
 212 {
 213         struct irq_desc *desc = irq_to_desc(irq);
 214         bfin_internal_unmask_irq_affinity(irq, desc->affinity);
 215 }
 216
 217 static int bfin_internal_set_affinity(unsigned int irq, const struct cpumask *mask)
 218 {
 219         bfin_internal_mask_irq(irq);
 220         bfin_internal_unmask_irq_affinity(irq, mask);
 221
 222         return 0;
 223 }
 224 #endif
 225
 226 #ifdef CONFIG_PM
 227 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 228 {
 229         u32 bank, bit, wakeup = 0;
 230         unsigned long flags;
 231         bank = SIC_SYSIRQ(irq) / 32;
 232         bit = SIC_SYSIRQ(irq) % 32;
 233
 234         switch (irq) {
 235 #ifdef IRQ_RTC
 236         case IRQ_RTC:
 237         wakeup |= WAKE;
 238         break;
 239 #endif
 240 #ifdef IRQ_CAN0_RX
 241         case IRQ_CAN0_RX:
 242         wakeup |= CANWE;
 243         break;
 244 #endif
 245 #ifdef IRQ_CAN1_RX
 246         case IRQ_CAN1_RX:
 247         wakeup |= CANWE;
 248         break;
 249 #endif
 250 #ifdef IRQ_USB_INT0
 251         case IRQ_USB_INT0:
 252         wakeup |= USBWE;
 253         break;
 254 #endif
 255 #ifdef IRQ_KEY
 256         case IRQ_KEY:
 257         wakeup |= KPADWE;
 258         break;
 259 #endif
 260 #ifdef CONFIG_BF54x
 261         case IRQ_CNT:
 262         wakeup |= ROTWE;
 263         break;
 264 #endif
 265         default:
 266         break;
 267         }
 268
 269         local_irq_save_hw(flags);
 270
 271         if (state) {
 272                 bfin_sic_iwr[bank] |= (1 << bit);
 273                 vr_wakeup  |= wakeup;
 274
 275         } else {
 276                 bfin_sic_iwr[bank] &= ~(1 << bit);
 277                 vr_wakeup  &= ~wakeup;
 278         }
 279
 280         local_irq_restore_hw(flags);
 281
 282         return 0;
 283 }
 284 #endif
 285
 286 static struct irq_chip bfin_core_irqchip = {
 287         .name = "CORE",
 288         .ack = bfin_ack_noop,
 289         .mask = bfin_core_mask_irq,
 290         .unmask = bfin_core_unmask_irq,
 291 };
 292
 293 static struct irq_chip bfin_internal_irqchip = {
 294         .name = "INTN",
 295         .ack = bfin_ack_noop,
 296         .mask = bfin_internal_mask_irq,
 297         .unmask = bfin_internal_unmask_irq,
 298         .mask_ack = bfin_internal_mask_irq,
 299         .disable = bfin_internal_mask_irq,
 300         .enable = bfin_internal_unmask_irq,
 301 #ifdef CONFIG_SMP
 302         .set_affinity = bfin_internal_set_affinity,
 303 #endif
 304 #ifdef CONFIG_PM
 305         .set_wake = bfin_internal_set_wake,
 306 #endif
 307 };
 308
 309 static void bfin_handle_irq(unsigned irq)
 310 {
 311 #ifdef CONFIG_IPIPE
 312         struct pt_regs regs;    /* Contents not used. */
 313         ipipe_trace_irq_entry(irq);
 314         __ipipe_handle_irq(irq, &regs);
 315         ipipe_trace_irq_exit(irq);
 316 #else /* !CONFIG_IPIPE */
 317         struct irq_desc *desc = irq_desc + irq;
 318         desc->handle_irq(irq, desc);
 319 #endif  /* !CONFIG_IPIPE */
 320 }
 321
 322 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 323 static int error_int_mask;
 324
 325 static void bfin_generic_error_mask_irq(unsigned int irq)
 326 {
 327         error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
 328
 329         if (!error_int_mask)
 330                 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
 331 }
 332
 333 static void bfin_generic_error_unmask_irq(unsigned int irq)
 334 {
 335         bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
 336         error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
 337 }
 338
 339 static struct irq_chip bfin_generic_error_irqchip = {
 340         .name = "ERROR",
 341         .ack = bfin_ack_noop,
 342         .mask_ack = bfin_generic_error_mask_irq,
 343         .mask = bfin_generic_error_mask_irq,
 344         .unmask = bfin_generic_error_unmask_irq,
 345 };
 346
 347 static void bfin_demux_error_irq(unsigned int int_err_irq,
 348                                  struct irq_desc *inta_desc)
 349 {
 350         int irq = 0;
 351
 352 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 353         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
 354                 irq = IRQ_MAC_ERROR;
 355         else
 356 #endif
 357         if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
 358                 irq = IRQ_SPORT0_ERROR;
 359         else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
 360                 irq = IRQ_SPORT1_ERROR;
 361         else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
 362                 irq = IRQ_PPI_ERROR;
 363         else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
 364                 irq = IRQ_CAN_ERROR;
 365         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
 366                 irq = IRQ_SPI_ERROR;
 367         else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 368                 irq = IRQ_UART0_ERROR;
 369         else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 370                 irq = IRQ_UART1_ERROR;
 371
 372         if (irq) {
 373                 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
 374                         bfin_handle_irq(irq);
 375                 else {
 376
 377                         switch (irq) {
 378                         case IRQ_PPI_ERROR:
 379                                 bfin_write_PPI_STATUS(PPI_ERR_MASK);
 380                                 break;
 381 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 382                         case IRQ_MAC_ERROR:
 383                                 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
 384                                 break;
 385 #endif
 386                         case IRQ_SPORT0_ERROR:
 387                                 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
 388                                 break;
 389
 390                         case IRQ_SPORT1_ERROR:
 391                                 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
 392                                 break;
 393
 394                         case IRQ_CAN_ERROR:
 395                                 bfin_write_CAN_GIS(CAN_ERR_MASK);
 396                                 break;
 397
 398                         case IRQ_SPI_ERROR:
 399                                 bfin_write_SPI_STAT(SPI_ERR_MASK);
 400                                 break;
 401
 402                         default:
 403                                 break;
 404                         }
 405
 406                         pr_debug("IRQ %d:"
 407                                  " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
 408                                  irq);
 409                 }
 410         } else
 411                 printk(KERN_ERR
 412                        "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
 413                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
 414                        __func__, __FILE__, __LINE__);
 415
 416 }
 417 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
 418
 419 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 420 {
 421 #ifdef CONFIG_IPIPE
 422         _set_irq_handler(irq, handle_level_irq);
 423 #else
 424         struct irq_desc *desc = irq_desc + irq;
 425         /* May not call generic set_irq_handler() due to spinlock
 426            recursion. */
 427         desc->handle_irq = handle;
 428 #endif
 429 }
 430
 431 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 432 extern void bfin_gpio_irq_prepare(unsigned gpio);
 433
 434 #if !defined(CONFIG_BF54x)
 435
 436 static void bfin_gpio_ack_irq(unsigned int irq)
 437 {
 438         /* AFAIK ack_irq in case mask_ack is provided
 439          * get's only called for edge sense irqs
 440          */
 441         set_gpio_data(irq_to_gpio(irq), 0);
 442 }
 443
 444 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 445 {
 446         struct irq_desc *desc = irq_desc + irq;
 447         u32 gpionr = irq_to_gpio(irq);
 448
 449         if (desc->handle_irq == handle_edge_irq)
 450                 set_gpio_data(gpionr, 0);
 451
 452         set_gpio_maska(gpionr, 0);
 453 }
 454
 455 static void bfin_gpio_mask_irq(unsigned int irq)
 456 {
 457         set_gpio_maska(irq_to_gpio(irq), 0);
 458 }
 459
 460 static void bfin_gpio_unmask_irq(unsigned int irq)
 461 {
 462         set_gpio_maska(irq_to_gpio(irq), 1);
 463 }
 464
 465 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 466 {
 467         u32 gpionr = irq_to_gpio(irq);
 468
 469         if (__test_and_set_bit(gpionr, gpio_enabled))
 470                 bfin_gpio_irq_prepare(gpionr);
 471
 472         bfin_gpio_unmask_irq(irq);
 473
 474         return 0;
 475 }
 476
 477 static void bfin_gpio_irq_shutdown(unsigned int irq)
 478 {
 479         u32 gpionr = irq_to_gpio(irq);
 480
 481         bfin_gpio_mask_irq(irq);
 482         __clear_bit(gpionr, gpio_enabled);
 483         bfin_gpio_irq_free(gpionr);
 484 }
 485
 486 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 487 {
 488         int ret;
 489         char buf[16];
 490         u32 gpionr = irq_to_gpio(irq);
 491
 492         if (type == IRQ_TYPE_PROBE) {
 493                 /* only probe unenabled GPIO interrupt lines */
 494                 if (test_bit(gpionr, gpio_enabled))
 495                         return 0;
 496                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 497         }
 498
 499         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 500                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 501
 502                 snprintf(buf, 16, "gpio-irq%d", irq);
 503                 ret = bfin_gpio_irq_request(gpionr, buf);
 504                 if (ret)
 505                         return ret;
 506
 507                 if (__test_and_set_bit(gpionr, gpio_enabled))
 508                         bfin_gpio_irq_prepare(gpionr);
 509
 510         } else {
 511                 __clear_bit(gpionr, gpio_enabled);
 512                 return 0;
 513         }
 514
 515         set_gpio_inen(gpionr, 0);
 516         set_gpio_dir(gpionr, 0);
 517
 518         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 519             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 520                 set_gpio_both(gpionr, 1);
 521         else
 522                 set_gpio_both(gpionr, 0);
 523
 524         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 525                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 526         else
 527                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 528
 529         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 530                 set_gpio_edge(gpionr, 1);
 531                 set_gpio_inen(gpionr, 1);
 532                 set_gpio_data(gpionr, 0);
 533
 534         } else {
 535                 set_gpio_edge(gpionr, 0);
 536                 set_gpio_inen(gpionr, 1);
 537         }
 538
 539         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 540                 bfin_set_irq_handler(irq, handle_edge_irq);
 541         else
 542                 bfin_set_irq_handler(irq, handle_level_irq);
 543
 544         return 0;
 545 }
 546
 547 #ifdef CONFIG_PM
 548 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 549 {
 550         unsigned gpio = irq_to_gpio(irq);
 551
 552         if (state)
 553                 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
 554         else
 555                 gpio_pm_wakeup_free(gpio);
 556
 557         return 0;
 558 }
 559 #endif
 560
 561 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 562                                 struct irq_desc *desc)
 563 {
 564         unsigned int i, gpio, mask, irq, search = 0;
 565
 566         switch (inta_irq) {
 567 #if defined(CONFIG_BF53x)
 568         case IRQ_PROG_INTA:
 569                 irq = IRQ_PF0;
 570                 search = 1;
 571                 break;
 572 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
 573         case IRQ_MAC_RX:
 574                 irq = IRQ_PH0;
 575                 break;
 576 # endif
 577 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
 578         case IRQ_PORTF_INTA:
 579                 irq = IRQ_PF0;
 580                 break;
 581 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 582         case IRQ_PORTF_INTA:
 583                 irq = IRQ_PF0;
 584                 break;
 585         case IRQ_PORTG_INTA:
 586                 irq = IRQ_PG0;
 587                 break;
 588         case IRQ_PORTH_INTA:
 589                 irq = IRQ_PH0;
 590                 break;
 591 #elif defined(CONFIG_BF561)
 592         case IRQ_PROG0_INTA:
 593                 irq = IRQ_PF0;
 594                 break;
 595         case IRQ_PROG1_INTA:
 596                 irq = IRQ_PF16;
 597                 break;
 598         case IRQ_PROG2_INTA:
 599                 irq = IRQ_PF32;
 600                 break;
 601 #endif
 602         default:
 603                 BUG();
 604                 return;
 605         }
 606
 607         if (search) {
 608                 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
 609                         irq += i;
 610
 611                         mask = get_gpiop_data(i) & get_gpiop_maska(i);
 612
 613                         while (mask) {
 614                                 if (mask & 1)
 615                                         bfin_handle_irq(irq);
 616                                 irq++;
 617                                 mask >>= 1;
 618                         }
 619                 }
 620         } else {
 621                         gpio = irq_to_gpio(irq);
 622                         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 623
 624                         do {
 625                                 if (mask & 1)
 626                                         bfin_handle_irq(irq);
 627                                 irq++;
 628                                 mask >>= 1;
 629                         } while (mask);
 630         }
 631
 632 }
 633
 634 #else                           /* CONFIG_BF54x */
 635
 636 #define NR_PINT_SYS_IRQS        4
 637 #define NR_PINT_BITS            32
 638 #define NR_PINTS                160
 639 #define IRQ_NOT_AVAIL           0xFF
 640
 641 #define PINT_2_BANK(x)          ((x) >> 5)
 642 #define PINT_2_BIT(x)           ((x) & 0x1F)
 643 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 644
 645 static unsigned char irq2pint_lut[NR_PINTS];
 646 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 647
 648 struct pin_int_t {
 649         unsigned int mask_set;
 650         unsigned int mask_clear;
 651         unsigned int request;
 652         unsigned int assign;
 653         unsigned int edge_set;
 654         unsigned int edge_clear;
 655         unsigned int invert_set;
 656         unsigned int invert_clear;
 657         unsigned int pinstate;
 658         unsigned int latch;
 659 };
 660
 661 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
 662         (struct pin_int_t *)PINT0_MASK_SET,
 663         (struct pin_int_t *)PINT1_MASK_SET,
 664         (struct pin_int_t *)PINT2_MASK_SET,
 665         (struct pin_int_t *)PINT3_MASK_SET,
 666 };
 667
 668 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 669 {
 670         unsigned int irq_base;
 671
 672         if (bank < 2) {         /*PA-PB */
 673                 irq_base = IRQ_PA0 + bmap * 16;
 674         } else {                /*PC-PJ */
 675                 irq_base = IRQ_PC0 + bmap * 16;
 676         }
 677
 678         return irq_base;
 679 }
 680
 681         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 682 void init_pint_lut(void)
 683 {
 684         u16 bank, bit, irq_base, bit_pos;
 685         u32 pint_assign;
 686         u8 bmap;
 687
 688         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 689
 690         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 691
 692                 pint_assign = pint[bank]->assign;
 693
 694                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 695
 696                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 697
 698                         irq_base = get_irq_base(bank, bmap);
 699
 700                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 701                         bit_pos = bit + bank * NR_PINT_BITS;
 702
 703                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 704                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 705                 }
 706         }
 707 }
 708
 709 static void bfin_gpio_ack_irq(unsigned int irq)
 710 {
 711         struct irq_desc *desc = irq_desc + irq;
 712         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 713         u32 pintbit = PINT_BIT(pint_val);
 714         u32 bank = PINT_2_BANK(pint_val);
 715
 716         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 717                 if (pint[bank]->invert_set & pintbit)
 718                         pint[bank]->invert_clear = pintbit;
 719                 else
 720                         pint[bank]->invert_set = pintbit;
 721         }
 722         pint[bank]->request = pintbit;
 723
 724 }
 725
 726 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 727 {
 728         struct irq_desc *desc = irq_desc + irq;
 729         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 730         u32 pintbit = PINT_BIT(pint_val);
 731         u32 bank = PINT_2_BANK(pint_val);
 732
 733         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 734                 if (pint[bank]->invert_set & pintbit)
 735                         pint[bank]->invert_clear = pintbit;
 736                 else
 737                         pint[bank]->invert_set = pintbit;
 738         }
 739
 740         pint[bank]->request = pintbit;
 741         pint[bank]->mask_clear = pintbit;
 742 }
 743
 744 static void bfin_gpio_mask_irq(unsigned int irq)
 745 {
 746         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 747
 748         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 749 }
 750
 751 static void bfin_gpio_unmask_irq(unsigned int irq)
 752 {
 753         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 754         u32 pintbit = PINT_BIT(pint_val);
 755         u32 bank = PINT_2_BANK(pint_val);
 756
 757         pint[bank]->request = pintbit;
 758         pint[bank]->mask_set = pintbit;
 759 }
 760
 761 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 762 {
 763         u32 gpionr = irq_to_gpio(irq);
 764         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 765
 766         if (pint_val == IRQ_NOT_AVAIL) {
 767                 printk(KERN_ERR
 768                 "GPIO IRQ %d :Not in PINT Assign table "
 769                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 770                 return -ENODEV;
 771         }
 772
 773         if (__test_and_set_bit(gpionr, gpio_enabled))
 774                 bfin_gpio_irq_prepare(gpionr);
 775
 776         bfin_gpio_unmask_irq(irq);
 777
 778         return 0;
 779 }
 780
 781 static void bfin_gpio_irq_shutdown(unsigned int irq)
 782 {
 783         u32 gpionr = irq_to_gpio(irq);
 784
 785         bfin_gpio_mask_irq(irq);
 786         __clear_bit(gpionr, gpio_enabled);
 787         bfin_gpio_irq_free(gpionr);
 788 }
 789
 790 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 791 {
 792         int ret;
 793         char buf[16];
 794         u32 gpionr = irq_to_gpio(irq);
 795         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 796         u32 pintbit = PINT_BIT(pint_val);
 797         u32 bank = PINT_2_BANK(pint_val);
 798
 799         if (pint_val == IRQ_NOT_AVAIL)
 800                 return -ENODEV;
 801
 802         if (type == IRQ_TYPE_PROBE) {
 803                 /* only probe unenabled GPIO interrupt lines */
 804                 if (test_bit(gpionr, gpio_enabled))
 805                         return 0;
 806                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 807         }
 808
 809         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 810                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 811
 812                 snprintf(buf, 16, "gpio-irq%d", irq);
 813                 ret = bfin_gpio_irq_request(gpionr, buf);
 814                 if (ret)
 815                         return ret;
 816
 817                 if (__test_and_set_bit(gpionr, gpio_enabled))
 818                         bfin_gpio_irq_prepare(gpionr);
 819
 820         } else {
 821                 __clear_bit(gpionr, gpio_enabled);
 822                 return 0;
 823         }
 824
 825         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 826                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
 827         else
 828                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
 829
 830         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 831             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 832                 if (gpio_get_value(gpionr))
 833                         pint[bank]->invert_set = pintbit;
 834                 else
 835                         pint[bank]->invert_clear = pintbit;
 836         }
 837
 838         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 839                 pint[bank]->edge_set = pintbit;
 840                 bfin_set_irq_handler(irq, handle_edge_irq);
 841         } else {
 842                 pint[bank]->edge_clear = pintbit;
 843                 bfin_set_irq_handler(irq, handle_level_irq);
 844         }
 845
 846         return 0;
 847 }
 848
 849 #ifdef CONFIG_PM
 850 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
 851 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
 852
 853 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 854 {
 855         u32 pint_irq;
 856         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 857         u32 bank = PINT_2_BANK(pint_val);
 858         u32 pintbit = PINT_BIT(pint_val);
 859
 860         switch (bank) {
 861         case 0:
 862                 pint_irq = IRQ_PINT0;
 863                 break;
 864         case 2:
 865                 pint_irq = IRQ_PINT2;
 866                 break;
 867         case 3:
 868                 pint_irq = IRQ_PINT3;
 869                 break;
 870         case 1:
 871                 pint_irq = IRQ_PINT1;
 872                 break;
 873         default:
 874                 return -EINVAL;
 875         }
 876
 877         bfin_internal_set_wake(pint_irq, state);
 878
 879         if (state)
 880                 pint_wakeup_masks[bank] |= pintbit;
 881         else
 882                 pint_wakeup_masks[bank] &= ~pintbit;
 883
 884         return 0;
 885 }
 886
 887 u32 bfin_pm_setup(void)
 888 {
 889         u32 val, i;
 890
 891         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
 892                 val = pint[i]->mask_clear;
 893                 pint_saved_masks[i] = val;
 894                 if (val ^ pint_wakeup_masks[i]) {
 895                         pint[i]->mask_clear = val;
 896                         pint[i]->mask_set = pint_wakeup_masks[i];
 897                 }
 898         }
 899
 900         return 0;
 901 }
 902
 903 void bfin_pm_restore(void)
 904 {
 905         u32 i, val;
 906
 907         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
 908                 val = pint_saved_masks[i];
 909                 if (val ^ pint_wakeup_masks[i]) {
 910                         pint[i]->mask_clear = pint[i]->mask_clear;
 911                         pint[i]->mask_set = val;
 912                 }
 913         }
 914 }
 915 #endif
 916
 917 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 918                                 struct irq_desc *desc)
 919 {
 920         u32 bank, pint_val;
 921         u32 request, irq;
 922
 923         switch (inta_irq) {
 924         case IRQ_PINT0:
 925                 bank = 0;
 926                 break;
 927         case IRQ_PINT2:
 928                 bank = 2;
 929                 break;
 930         case IRQ_PINT3:
 931                 bank = 3;
 932                 break;
 933         case IRQ_PINT1:
 934                 bank = 1;
 935                 break;
 936         default:
 937                 return;
 938         }
 939
 940         pint_val = bank * NR_PINT_BITS;
 941
 942         request = pint[bank]->request;
 943
 944         while (request) {
 945                 if (request & 1) {
 946                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
 947                         bfin_handle_irq(irq);
 948                 }
 949                 pint_val++;
 950                 request >>= 1;
 951         }
 952
 953 }
 954 #endif
 955
 956 static struct irq_chip bfin_gpio_irqchip = {
 957         .name = "GPIO",
 958         .ack = bfin_gpio_ack_irq,
 959         .mask = bfin_gpio_mask_irq,
 960         .mask_ack = bfin_gpio_mask_ack_irq,
 961         .unmask = bfin_gpio_unmask_irq,
 962         .disable = bfin_gpio_mask_irq,
 963         .enable = bfin_gpio_unmask_irq,
 964         .set_type = bfin_gpio_irq_type,
 965         .startup = bfin_gpio_irq_startup,
 966         .shutdown = bfin_gpio_irq_shutdown,
 967 #ifdef CONFIG_PM
 968         .set_wake = bfin_gpio_set_wake,
 969 #endif
 970 };
 971
 972 void __cpuinit init_exception_vectors(void)
 973 {
 974         /* cannot program in software:
 975          * evt0 - emulation (jtag)
 976          * evt1 - reset
 977          */
 978         bfin_write_EVT2(evt_nmi);
 979         bfin_write_EVT3(trap);
 980         bfin_write_EVT5(evt_ivhw);
 981         bfin_write_EVT6(evt_timer);
 982         bfin_write_EVT7(evt_evt7);
 983         bfin_write_EVT8(evt_evt8);
 984         bfin_write_EVT9(evt_evt9);
 985         bfin_write_EVT10(evt_evt10);
 986         bfin_write_EVT11(evt_evt11);
 987         bfin_write_EVT12(evt_evt12);
 988         bfin_write_EVT13(evt_evt13);
 989         bfin_write_EVT14(evt_evt14);
 990         bfin_write_EVT15(evt_system_call);
 991         CSYNC();
 992 }
 993
 994 /*
 995  * This function should be called during kernel startup to initialize
 996  * the BFin IRQ handling routines.
 997  */
 998
 999 int __init init_arch_irq(void)
1000 {
1001         int irq;
1002         unsigned long ilat = 0;
1003         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
1004 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1005         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1006         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1007         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1008 # ifdef CONFIG_BF54x
1009         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1010 # endif
1011 # ifdef CONFIG_SMP
1012         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1013         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1014 # endif
1015 #else
1016         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1017 #endif
1018
1019         local_irq_disable();
1020
1021 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1022         /* Clear EMAC Interrupt Status bits so we can demux it later */
1023         bfin_write_EMAC_SYSTAT(-1);
1024 #endif
1025
1026 #ifdef CONFIG_BF54x
1027 # ifdef CONFIG_PINTx_REASSIGN
1028         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1029         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1030         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1031         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1032 # endif
1033         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1034         init_pint_lut();
1035 #endif
1036
1037         for (irq = 0; irq <= SYS_IRQS; irq++) {
1038                 if (irq <= IRQ_CORETMR)
1039                         set_irq_chip(irq, &bfin_core_irqchip);
1040                 else
1041                         set_irq_chip(irq, &bfin_internal_irqchip);
1042
1043                 switch (irq) {
1044 #if defined(CONFIG_BF53x)
1045                 case IRQ_PROG_INTA:
1046 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1047                 case IRQ_MAC_RX:
1048 # endif
1049 #elif defined(CONFIG_BF54x)
1050                 case IRQ_PINT0:
1051                 case IRQ_PINT1:
1052                 case IRQ_PINT2:
1053                 case IRQ_PINT3:
1054 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1055                 case IRQ_PORTF_INTA:
1056                 case IRQ_PORTG_INTA:
1057                 case IRQ_PORTH_INTA:
1058 #elif defined(CONFIG_BF561)
1059                 case IRQ_PROG0_INTA:
1060                 case IRQ_PROG1_INTA:
1061                 case IRQ_PROG2_INTA:
1062 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1063                 case IRQ_PORTF_INTA:
1064 #endif
1065                         set_irq_chained_handler(irq,
1066                                                 bfin_demux_gpio_irq);
1067                         break;
1068 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1069                 case IRQ_GENERIC_ERROR:
1070                         set_irq_chained_handler(irq, bfin_demux_error_irq);
1071                         break;
1072 #endif
1073
1074 #ifdef CONFIG_SMP
1075                 case IRQ_SUPPLE_0:
1076                 case IRQ_SUPPLE_1:
1077                         set_irq_handler(irq, handle_percpu_irq);
1078                         break;
1079 #endif
1080
1081 #ifdef CONFIG_TICKSOURCE_CORETMR
1082                 case IRQ_CORETMR:
1083 # ifdef CONFIG_SMP
1084                         set_irq_handler(irq, handle_percpu_irq);
1085                         break;
1086 # else
1087                         set_irq_handler(irq, handle_simple_irq);
1088                         break;
1089 # endif
1090 #endif
1091
1092 #ifdef CONFIG_TICKSOURCE_GPTMR0
1093                 case IRQ_TIMER0:
1094                         set_irq_handler(irq, handle_simple_irq);
1095                         break;
1096 #endif
1097
1098 #ifdef CONFIG_IPIPE
1099                 default:
1100                         set_irq_handler(irq, handle_level_irq);
1101                         break;
1102 #else /* !CONFIG_IPIPE */
1103                 default:
1104                         set_irq_handler(irq, handle_simple_irq);
1105                         break;
1106 #endif /* !CONFIG_IPIPE */
1107                 }
1108         }
1109
1110 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1111         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1112                 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1113                                          handle_level_irq);
1114 #endif
1115
1116         /* if configured as edge, then will be changed to do_edge_IRQ */
1117         for (irq = GPIO_IRQ_BASE; irq < NR_MACH_IRQS; irq++)
1118                 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1119                                          handle_level_irq);
1120
1121
1122         bfin_write_IMASK(0);
1123         CSYNC();
1124         ilat = bfin_read_ILAT();
1125         CSYNC();
1126         bfin_write_ILAT(ilat);
1127         CSYNC();
1128
1129         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1130         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1131          * local_irq_enable()
1132          */
1133         program_IAR();
1134         /* Therefore it's better to setup IARs before interrupts enabled */
1135         search_IAR();
1136
1137         /* Enable interrupts IVG7-15 */
1138         bfin_irq_flags |= IMASK_IVG15 |
1139             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1140             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1141
1142         /* This implicitly covers ANOMALY_05000171
1143          * Boot-ROM code modifies SICA_IWRx wakeup registers
1144          */
1145 #ifdef SIC_IWR0
1146         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1147 # ifdef SIC_IWR1
1148         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1149          * will screw up the bootrom as it relies on MDMA0/1 waking it
1150          * up from IDLE instructions.  See this report for more info:
1151          * http://blackfin.uclinux.org/gf/tracker/4323
1152          */
1153         if (ANOMALY_05000435)
1154                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1155         else
1156                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1157 # endif
1158 # ifdef SIC_IWR2
1159         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1160 # endif
1161 #else
1162         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1163 #endif
1164
1165         return 0;
1166 }
1167
1168 #ifdef CONFIG_DO_IRQ_L1
1169 __attribute__((l1_text))
1170 #endif
1171 void do_irq(int vec, struct pt_regs *fp)
1172 {
1173         if (vec == EVT_IVTMR_P) {
1174                 vec = IRQ_CORETMR;
1175         } else {
1176                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1177                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1178 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1179                 unsigned long sic_status[3];
1180
1181                 if (smp_processor_id()) {
1182 # ifdef SICB_ISR0
1183                         /* This will be optimized out in UP mode. */
1184                         sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1185                         sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1186 # endif
1187                 } else {
1188                         sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1189                         sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1190                 }
1191 # ifdef SIC_ISR2
1192                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1193 # endif
1194                 for (;; ivg++) {
1195                         if (ivg >= ivg_stop) {
1196                                 atomic_inc(&num_spurious);
1197                                 return;
1198                         }
1199                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1200                                 break;
1201                 }
1202 #else
1203                 unsigned long sic_status;
1204
1205                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1206
1207                 for (;; ivg++) {
1208                         if (ivg >= ivg_stop) {
1209                                 atomic_inc(&num_spurious);
1210                                 return;
1211                         } else if (sic_status & ivg->isrflag)
1212                                 break;
1213                 }
1214 #endif
1215                 vec = ivg->irqno;
1216         }
1217         asm_do_IRQ(vec, fp);
1218 }
1219
1220 #ifdef CONFIG_IPIPE
1221
1222 int __ipipe_get_irq_priority(unsigned irq)
1223 {
1224         int ient, prio;
1225
1226         if (irq <= IRQ_CORETMR)
1227                 return irq;
1228
1229         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1230                 struct ivgx *ivg = ivg_table + ient;
1231                 if (ivg->irqno == irq) {
1232                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1233                                 if (ivg7_13[prio].ifirst <= ivg &&
1234                                     ivg7_13[prio].istop > ivg)
1235                                         return IVG7 + prio;
1236                         }
1237                 }
1238         }
1239
1240         return IVG15;
1241 }
1242
1243 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1244 #ifdef CONFIG_DO_IRQ_L1
1245 __attribute__((l1_text))
1246 #endif
1247 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1248 {
1249         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1250         struct ipipe_domain *this_domain = __ipipe_current_domain;
1251         struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1252         struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1253         int irq, s;
1254
1255         if (likely(vec == EVT_IVTMR_P))
1256                 irq = IRQ_CORETMR;
1257         else {
1258 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1259                 unsigned long sic_status[3];
1260
1261                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1262                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1263 # ifdef SIC_ISR2
1264                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1265 # endif
1266                 for (;; ivg++) {
1267                         if (ivg >= ivg_stop) {
1268                                 atomic_inc(&num_spurious);
1269                                 return 0;
1270                         }
1271                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1272                                 break;
1273                 }
1274 #else
1275                 unsigned long sic_status;
1276
1277                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1278
1279                 for (;; ivg++) {
1280                         if (ivg >= ivg_stop) {
1281                                 atomic_inc(&num_spurious);
1282                                 return 0;
1283                         } else if (sic_status & ivg->isrflag)
1284                                 break;
1285                 }
1286 #endif
1287                 irq = ivg->irqno;
1288         }
1289
1290         if (irq == IRQ_SYSTMR) {
1291 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1292                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1293 #endif
1294                 /* This is basically what we need from the register frame. */
1295                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1296                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1297                 if (this_domain != ipipe_root_domain)
1298                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1299                 else
1300                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1301         }
1302
1303         if (this_domain == ipipe_root_domain) {
1304                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1305                 barrier();
1306         }
1307
1308         ipipe_trace_irq_entry(irq);
1309         __ipipe_handle_irq(irq, regs);
1310         ipipe_trace_irq_exit(irq);
1311
1312         if (this_domain == ipipe_root_domain) {
1313                 set_thread_flag(TIF_IRQ_SYNC);
1314                 if (!s) {
1315                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1316                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1317                 }
1318         }
1319
1320         return 0;
1321 }
1322
1323 #endif /* CONFIG_IPIPE */