arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * Set up the interrupt priorities
   3  *
   4  * Copyright  2004-2009 Analog Devices Inc.
   5  *                 2003 Bas Vermeulen <bas@buyways.nl>
   6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
   7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
   8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *                 1996 Roman Zippel
  10  *
  11  * Licensed under the GPL-2
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/irq.h>
  18 #include <linux/sched.h>
  19 #include <linux/syscore_ops.h>
  20 #include <asm/delay.h>
  21 #ifdef CONFIG_IPIPE
  22 #include <linux/ipipe.h>
  23 #endif
  24 #include <asm/traps.h>
  25 #include <asm/blackfin.h>
  26 #include <asm/gpio.h>
  27 #include <asm/irq_handler.h>
  28 #include <asm/dpmc.h>
  29
  30 #ifndef SEC_GCTL
  31 # define SIC_SYSIRQ(irq)        (irq - (IRQ_CORETMR + 1))
  32 #else
  33 # define SIC_SYSIRQ(irq)        ((irq) - IVG15)
  34 #endif
  35
  36 /*
  37  * NOTES:
  38  * - we have separated the physical Hardware interrupt from the
  39  * levels that the LINUX kernel sees (see the description in irq.h)
  40  * -
  41  */
  42
  43 #ifndef CONFIG_SMP
  44 /* Initialize this to an actual value to force it into the .data
  45  * section so that we know it is properly initialized at entry into
  46  * the kernel but before bss is initialized to zero (which is where
  47  * it would live otherwise).  The 0x1f magic represents the IRQs we
  48  * cannot actually mask out in hardware.
  49  */
  50 unsigned long bfin_irq_flags = 0x1f;
  51 EXPORT_SYMBOL(bfin_irq_flags);
  52 #endif
  53
  54 #ifdef CONFIG_PM
  55 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  56 unsigned vr_wakeup;
  57 #endif
  58
  59 #ifndef SEC_GCTL
  60 static struct ivgx {
  61         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  62         unsigned int irqno;
  63         /* corresponding bit in the SIC_ISR register */
  64         unsigned int isrflag;
  65 } ivg_table[NR_PERI_INTS];
  66
  67 static struct ivg_slice {
  68         /* position of first irq in ivg_table for given ivg */
  69         struct ivgx *ifirst;
  70         struct ivgx *istop;
  71 } ivg7_13[IVG13 - IVG7 + 1];
  72
  73
  74 /*
  75  * Search SIC_IAR and fill tables with the irqvalues
  76  * and their positions in the SIC_ISR register.
  77  */
  78 static void __init search_IAR(void)
  79 {
  80         unsigned ivg, irq_pos = 0;
  81         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  82                 int irqN;
  83
  84                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  85
  86                 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
  87                         int irqn;
  88                         u32 iar =
  89                                 bfin_read32((unsigned long *)SIC_IAR0 +
  90 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
  91         defined(CONFIG_BF538) || defined(CONFIG_BF539)
  92                                 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
  93 #else
  94                                 (irqN >> 3)
  95 #endif
  96                                 );
  97                         for (irqn = irqN; irqn < irqN + 4; ++irqn) {
  98                                 int iar_shift = (irqn & 7) * 4;
  99                                 if (ivg == (0xf & (iar >> iar_shift))) {
 100                                         ivg_table[irq_pos].irqno = IVG7 + irqn;
 101                                         ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 102                                         ivg7_13[ivg].istop++;
 103                                         irq_pos++;
 104                                 }
 105                         }
 106                 }
 107         }
 108 }
 109 #endif
 110
 111 /*
 112  * This is for core internal IRQs
 113  */
 114 void bfin_ack_noop(struct irq_data *d)
 115 {
 116         /* Dummy function.  */
 117 }
 118
 119 static void bfin_core_mask_irq(struct irq_data *d)
 120 {
 121         bfin_irq_flags &= ~(1 << d->irq);
 122         if (!hard_irqs_disabled())
 123                 hard_local_irq_enable();
 124 }
 125
 126 static void bfin_core_unmask_irq(struct irq_data *d)
 127 {
 128         bfin_irq_flags |= 1 << d->irq;
 129         /*
 130          * If interrupts are enabled, IMASK must contain the same value
 131          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 132          * are currently disabled we need not do anything; one of the
 133          * callers will take care of setting IMASK to the proper value
 134          * when reenabling interrupts.
 135          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 136          * what we need.
 137          */
 138         if (!hard_irqs_disabled())
 139                 hard_local_irq_enable();
 140         return;
 141 }
 142
 143 void bfin_internal_mask_irq(unsigned int irq)
 144 {
 145         unsigned long flags = hard_local_irq_save();
 146 #ifndef SEC_GCTL
 147 #ifdef SIC_IMASK0
 148         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
 149         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
 150         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 151                         ~(1 << mask_bit));
 152 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
 153         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 154                         ~(1 << mask_bit));
 155 # endif
 156 #else
 157         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 158                         ~(1 << SIC_SYSIRQ(irq)));
 159 #endif /* end of SIC_IMASK0 */
 160 #endif
 161         hard_local_irq_restore(flags);
 162 }
 163
 164 static void bfin_internal_mask_irq_chip(struct irq_data *d)
 165 {
 166         bfin_internal_mask_irq(d->irq);
 167 }
 168
 169 #ifdef CONFIG_SMP
 170 void bfin_internal_unmask_irq_affinity(unsigned int irq,
 171                 const struct cpumask *affinity)
 172 #else
 173 void bfin_internal_unmask_irq(unsigned int irq)
 174 #endif
 175 {
 176         unsigned long flags = hard_local_irq_save();
 177
 178 #ifndef SEC_GCTL
 179 #ifdef SIC_IMASK0
 180         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
 181         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
 182 # ifdef CONFIG_SMP
 183         if (cpumask_test_cpu(0, affinity))
 184 # endif
 185                 bfin_write_SIC_IMASK(mask_bank,
 186                                 bfin_read_SIC_IMASK(mask_bank) |
 187                                 (1 << mask_bit));
 188 # ifdef CONFIG_SMP
 189         if (cpumask_test_cpu(1, affinity))
 190                 bfin_write_SICB_IMASK(mask_bank,
 191                                 bfin_read_SICB_IMASK(mask_bank) |
 192                                 (1 << mask_bit));
 193 # endif
 194 #else
 195         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 196                         (1 << SIC_SYSIRQ(irq)));
 197 #endif
 198 #endif
 199         hard_local_irq_restore(flags);
 200 }
 201
 202 #ifdef SEC_GCTL
 203 static void bfin_sec_preflow_handler(struct irq_data *d)
 204 {
 205         unsigned long flags = hard_local_irq_save();
 206         unsigned int sid = SIC_SYSIRQ(d->irq);
 207
 208         bfin_write_SEC_SCI(0, SEC_CSID, sid);
 209
 210         hard_local_irq_restore(flags);
 211 }
 212
 213 static void bfin_sec_mask_ack_irq(struct irq_data *d)
 214 {
 215         unsigned long flags = hard_local_irq_save();
 216         unsigned int sid = SIC_SYSIRQ(d->irq);
 217
 218         bfin_write_SEC_SCI(0, SEC_CSID, sid);
 219
 220         hard_local_irq_restore(flags);
 221 }
 222
 223 static void bfin_sec_unmask_irq(struct irq_data *d)
 224 {
 225         unsigned long flags = hard_local_irq_save();
 226         unsigned int sid = SIC_SYSIRQ(d->irq);
 227
 228         bfin_write32(SEC_END, sid);
 229
 230         hard_local_irq_restore(flags);
 231 }
 232
 233 static void bfin_sec_enable_ssi(unsigned int sid)
 234 {
 235         unsigned long flags = hard_local_irq_save();
 236         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 237
 238         reg_sctl |= SEC_SCTL_SRC_EN;
 239         bfin_write_SEC_SCTL(sid, reg_sctl);
 240
 241         hard_local_irq_restore(flags);
 242 }
 243
 244 static void bfin_sec_disable_ssi(unsigned int sid)
 245 {
 246         unsigned long flags = hard_local_irq_save();
 247         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 248
 249         reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
 250         bfin_write_SEC_SCTL(sid, reg_sctl);
 251
 252         hard_local_irq_restore(flags);
 253 }
 254
 255 static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
 256 {
 257         unsigned long flags = hard_local_irq_save();
 258         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 259
 260         reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
 261         bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
 262
 263         hard_local_irq_restore(flags);
 264 }
 265
 266 static void bfin_sec_enable_sci(unsigned int sid)
 267 {
 268         unsigned long flags = hard_local_irq_save();
 269         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 270
 271         if (sid == SIC_SYSIRQ(IRQ_WATCH0))
 272                 reg_sctl |= SEC_SCTL_FAULT_EN;
 273         else
 274                 reg_sctl |= SEC_SCTL_INT_EN;
 275         bfin_write_SEC_SCTL(sid, reg_sctl);
 276
 277         hard_local_irq_restore(flags);
 278 }
 279
 280 static void bfin_sec_disable_sci(unsigned int sid)
 281 {
 282         unsigned long flags = hard_local_irq_save();
 283         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 284
 285         reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
 286         bfin_write_SEC_SCTL(sid, reg_sctl);
 287
 288         hard_local_irq_restore(flags);
 289 }
 290
 291 static void bfin_sec_enable(struct irq_data *d)
 292 {
 293         unsigned long flags = hard_local_irq_save();
 294         unsigned int sid = SIC_SYSIRQ(d->irq);
 295
 296         bfin_sec_enable_sci(sid);
 297         bfin_sec_enable_ssi(sid);
 298
 299         hard_local_irq_restore(flags);
 300 }
 301
 302 static void bfin_sec_disable(struct irq_data *d)
 303 {
 304         unsigned long flags = hard_local_irq_save();
 305         unsigned int sid = SIC_SYSIRQ(d->irq);
 306
 307         bfin_sec_disable_sci(sid);
 308         bfin_sec_disable_ssi(sid);
 309
 310         hard_local_irq_restore(flags);
 311 }
 312
 313 static void bfin_sec_raise_irq(unsigned int sid)
 314 {
 315         unsigned long flags = hard_local_irq_save();
 316
 317         bfin_write32(SEC_RAISE, sid);
 318
 319         hard_local_irq_restore(flags);
 320 }
 321
 322 static void init_software_driven_irq(void)
 323 {
 324         bfin_sec_set_ssi_coreid(34, 0);
 325         bfin_sec_set_ssi_coreid(35, 1);
 326         bfin_sec_set_ssi_coreid(36, 0);
 327         bfin_sec_set_ssi_coreid(37, 1);
 328 }
 329
 330 void bfin_sec_resume(void)
 331 {
 332         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
 333         udelay(100);
 334         bfin_write_SEC_GCTL(SEC_GCTL_EN);
 335         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
 336 }
 337
 338 void handle_sec_sfi_fault(uint32_t gstat)
 339 {
 340
 341 }
 342
 343 void handle_sec_sci_fault(uint32_t gstat)
 344 {
 345         uint32_t core_id;
 346         uint32_t cstat;
 347
 348         core_id = gstat & SEC_GSTAT_SCI;
 349         cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
 350         if (cstat & SEC_CSTAT_ERR) {
 351                 switch (cstat & SEC_CSTAT_ERRC) {
 352                 case SEC_CSTAT_ACKERR:
 353                         printk(KERN_DEBUG "sec ack err\n");
 354                         break;
 355                 default:
 356                         printk(KERN_DEBUG "sec sci unknow err\n");
 357                 }
 358         }
 359
 360 }
 361
 362 void handle_sec_ssi_fault(uint32_t gstat)
 363 {
 364         uint32_t sid;
 365         uint32_t sstat;
 366
 367         sid = gstat & SEC_GSTAT_SID;
 368         sstat = bfin_read_SEC_SSTAT(sid);
 369
 370 }
 371
 372 void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
 373 {
 374         uint32_t sec_gstat;
 375
 376         raw_spin_lock(&desc->lock);
 377
 378         sec_gstat = bfin_read32(SEC_GSTAT);
 379         if (sec_gstat & SEC_GSTAT_ERR) {
 380
 381                 switch (sec_gstat & SEC_GSTAT_ERRC) {
 382                 case 0:
 383                         handle_sec_sfi_fault(sec_gstat);
 384                         break;
 385                 case SEC_GSTAT_SCIERR:
 386                         handle_sec_sci_fault(sec_gstat);
 387                         break;
 388                 case SEC_GSTAT_SSIERR:
 389                         handle_sec_ssi_fault(sec_gstat);
 390                         break;
 391                 }
 392
 393
 394         }
 395
 396         raw_spin_unlock(&desc->lock);
 397 }
 398
 399 #endif
 400
 401 #ifdef CONFIG_SMP
 402 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 403 {
 404         bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
 405 }
 406
 407 static int bfin_internal_set_affinity(struct irq_data *d,
 408                                       const struct cpumask *mask, bool force)
 409 {
 410         bfin_internal_mask_irq(d->irq);
 411         bfin_internal_unmask_irq_affinity(d->irq, mask);
 412
 413         return 0;
 414 }
 415 #else
 416 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 417 {
 418         bfin_internal_unmask_irq(d->irq);
 419 }
 420 #endif
 421
 422 #if defined(CONFIG_PM) && !defined(SEC_GCTL)
 423 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 424 {
 425         u32 bank, bit, wakeup = 0;
 426         unsigned long flags;
 427         bank = SIC_SYSIRQ(irq) / 32;
 428         bit = SIC_SYSIRQ(irq) % 32;
 429
 430         switch (irq) {
 431 #ifdef IRQ_RTC
 432         case IRQ_RTC:
 433         wakeup |= WAKE;
 434         break;
 435 #endif
 436 #ifdef IRQ_CAN0_RX
 437         case IRQ_CAN0_RX:
 438         wakeup |= CANWE;
 439         break;
 440 #endif
 441 #ifdef IRQ_CAN1_RX
 442         case IRQ_CAN1_RX:
 443         wakeup |= CANWE;
 444         break;
 445 #endif
 446 #ifdef IRQ_USB_INT0
 447         case IRQ_USB_INT0:
 448         wakeup |= USBWE;
 449         break;
 450 #endif
 451 #ifdef CONFIG_BF54x
 452         case IRQ_CNT:
 453         wakeup |= ROTWE;
 454         break;
 455 #endif
 456         default:
 457         break;
 458         }
 459
 460         flags = hard_local_irq_save();
 461
 462         if (state) {
 463                 bfin_sic_iwr[bank] |= (1 << bit);
 464                 vr_wakeup  |= wakeup;
 465
 466         } else {
 467                 bfin_sic_iwr[bank] &= ~(1 << bit);
 468                 vr_wakeup  &= ~wakeup;
 469         }
 470
 471         hard_local_irq_restore(flags);
 472
 473         return 0;
 474 }
 475
 476 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
 477 {
 478         return bfin_internal_set_wake(d->irq, state);
 479 }
 480 #else
 481 inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 482 {
 483         return 0;
 484 }
 485 # define bfin_internal_set_wake_chip NULL
 486 #endif
 487
 488 static struct irq_chip bfin_core_irqchip = {
 489         .name = "CORE",
 490         .irq_mask = bfin_core_mask_irq,
 491         .irq_unmask = bfin_core_unmask_irq,
 492 };
 493
 494 static struct irq_chip bfin_internal_irqchip = {
 495         .name = "INTN",
 496         .irq_mask = bfin_internal_mask_irq_chip,
 497         .irq_unmask = bfin_internal_unmask_irq_chip,
 498         .irq_disable = bfin_internal_mask_irq_chip,
 499         .irq_enable = bfin_internal_unmask_irq_chip,
 500 #ifdef CONFIG_SMP
 501         .irq_set_affinity = bfin_internal_set_affinity,
 502 #endif
 503         .irq_set_wake = bfin_internal_set_wake_chip,
 504 };
 505
 506 #ifdef SEC_GCTL
 507 static struct irq_chip bfin_sec_irqchip = {
 508         .name = "SEC",
 509         .irq_mask_ack = bfin_sec_mask_ack_irq,
 510         .irq_mask = bfin_sec_mask_ack_irq,
 511         .irq_unmask = bfin_sec_unmask_irq,
 512         .irq_eoi = bfin_sec_unmask_irq,
 513         .irq_disable = bfin_sec_disable,
 514         .irq_enable = bfin_sec_enable,
 515 };
 516 #endif
 517
 518 void bfin_handle_irq(unsigned irq)
 519 {
 520 #ifdef CONFIG_IPIPE
 521         struct pt_regs regs;    /* Contents not used. */
 522         ipipe_trace_irq_entry(irq);
 523         __ipipe_handle_irq(irq, &regs);
 524         ipipe_trace_irq_exit(irq);
 525 #else /* !CONFIG_IPIPE */
 526         generic_handle_irq(irq);
 527 #endif  /* !CONFIG_IPIPE */
 528 }
 529
 530 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 531 static int mac_stat_int_mask;
 532
 533 static void bfin_mac_status_ack_irq(unsigned int irq)
 534 {
 535         switch (irq) {
 536         case IRQ_MAC_MMCINT:
 537                 bfin_write_EMAC_MMC_TIRQS(
 538                         bfin_read_EMAC_MMC_TIRQE() &
 539                         bfin_read_EMAC_MMC_TIRQS());
 540                 bfin_write_EMAC_MMC_RIRQS(
 541                         bfin_read_EMAC_MMC_RIRQE() &
 542                         bfin_read_EMAC_MMC_RIRQS());
 543                 break;
 544         case IRQ_MAC_RXFSINT:
 545                 bfin_write_EMAC_RX_STKY(
 546                         bfin_read_EMAC_RX_IRQE() &
 547                         bfin_read_EMAC_RX_STKY());
 548                 break;
 549         case IRQ_MAC_TXFSINT:
 550                 bfin_write_EMAC_TX_STKY(
 551                         bfin_read_EMAC_TX_IRQE() &
 552                         bfin_read_EMAC_TX_STKY());
 553                 break;
 554         case IRQ_MAC_WAKEDET:
 555                  bfin_write_EMAC_WKUP_CTL(
 556                         bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
 557                 break;
 558         default:
 559                 /* These bits are W1C */
 560                 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
 561                 break;
 562         }
 563 }
 564
 565 static void bfin_mac_status_mask_irq(struct irq_data *d)
 566 {
 567         unsigned int irq = d->irq;
 568
 569         mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
 570 #ifdef BF537_FAMILY
 571         switch (irq) {
 572         case IRQ_MAC_PHYINT:
 573                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
 574                 break;
 575         default:
 576                 break;
 577         }
 578 #else
 579         if (!mac_stat_int_mask)
 580                 bfin_internal_mask_irq(IRQ_MAC_ERROR);
 581 #endif
 582         bfin_mac_status_ack_irq(irq);
 583 }
 584
 585 static void bfin_mac_status_unmask_irq(struct irq_data *d)
 586 {
 587         unsigned int irq = d->irq;
 588
 589 #ifdef BF537_FAMILY
 590         switch (irq) {
 591         case IRQ_MAC_PHYINT:
 592                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
 593                 break;
 594         default:
 595                 break;
 596         }
 597 #else
 598         if (!mac_stat_int_mask)
 599                 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
 600 #endif
 601         mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
 602 }
 603
 604 #ifdef CONFIG_PM
 605 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
 606 {
 607 #ifdef BF537_FAMILY
 608         return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
 609 #else
 610         return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
 611 #endif
 612 }
 613 #else
 614 # define bfin_mac_status_set_wake NULL
 615 #endif
 616
 617 static struct irq_chip bfin_mac_status_irqchip = {
 618         .name = "MACST",
 619         .irq_mask = bfin_mac_status_mask_irq,
 620         .irq_unmask = bfin_mac_status_unmask_irq,
 621         .irq_set_wake = bfin_mac_status_set_wake,
 622 };
 623
 624 void bfin_demux_mac_status_irq(unsigned int int_err_irq,
 625                                struct irq_desc *inta_desc)
 626 {
 627         int i, irq = 0;
 628         u32 status = bfin_read_EMAC_SYSTAT();
 629
 630         for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
 631                 if (status & (1L << i)) {
 632                         irq = IRQ_MAC_PHYINT + i;
 633                         break;
 634                 }
 635
 636         if (irq) {
 637                 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
 638                         bfin_handle_irq(irq);
 639                 } else {
 640                         bfin_mac_status_ack_irq(irq);
 641                         pr_debug("IRQ %d:"
 642                                         " MASKED MAC ERROR INTERRUPT ASSERTED\n",
 643                                         irq);
 644                 }
 645         } else
 646                 printk(KERN_ERR
 647                                 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
 648                                 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
 649                                 "(EMAC_SYSTAT=0x%X)\n",
 650                                 __func__, __FILE__, __LINE__, status);
 651 }
 652 #endif
 653
 654 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 655 {
 656 #ifdef CONFIG_IPIPE
 657         handle = handle_level_irq;
 658 #endif
 659         __irq_set_handler_locked(irq, handle);
 660 }
 661
 662 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 663 extern void bfin_gpio_irq_prepare(unsigned gpio);
 664
 665 #if !BFIN_GPIO_PINT
 666
 667 static void bfin_gpio_ack_irq(struct irq_data *d)
 668 {
 669         /* AFAIK ack_irq in case mask_ack is provided
 670          * get's only called for edge sense irqs
 671          */
 672         set_gpio_data(irq_to_gpio(d->irq), 0);
 673 }
 674
 675 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
 676 {
 677         unsigned int irq = d->irq;
 678         u32 gpionr = irq_to_gpio(irq);
 679
 680         if (!irqd_is_level_type(d))
 681                 set_gpio_data(gpionr, 0);
 682
 683         set_gpio_maska(gpionr, 0);
 684 }
 685
 686 static void bfin_gpio_mask_irq(struct irq_data *d)
 687 {
 688         set_gpio_maska(irq_to_gpio(d->irq), 0);
 689 }
 690
 691 static void bfin_gpio_unmask_irq(struct irq_data *d)
 692 {
 693         set_gpio_maska(irq_to_gpio(d->irq), 1);
 694 }
 695
 696 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
 697 {
 698         u32 gpionr = irq_to_gpio(d->irq);
 699
 700         if (__test_and_set_bit(gpionr, gpio_enabled))
 701                 bfin_gpio_irq_prepare(gpionr);
 702
 703         bfin_gpio_unmask_irq(d);
 704
 705         return 0;
 706 }
 707
 708 static void bfin_gpio_irq_shutdown(struct irq_data *d)
 709 {
 710         u32 gpionr = irq_to_gpio(d->irq);
 711
 712         bfin_gpio_mask_irq(d);
 713         __clear_bit(gpionr, gpio_enabled);
 714         bfin_gpio_irq_free(gpionr);
 715 }
 716
 717 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
 718 {
 719         unsigned int irq = d->irq;
 720         int ret;
 721         char buf[16];
 722         u32 gpionr = irq_to_gpio(irq);
 723
 724         if (type == IRQ_TYPE_PROBE) {
 725                 /* only probe unenabled GPIO interrupt lines */
 726                 if (test_bit(gpionr, gpio_enabled))
 727                         return 0;
 728                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 729         }
 730
 731         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 732                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 733
 734                 snprintf(buf, 16, "gpio-irq%d", irq);
 735                 ret = bfin_gpio_irq_request(gpionr, buf);
 736                 if (ret)
 737                         return ret;
 738
 739                 if (__test_and_set_bit(gpionr, gpio_enabled))
 740                         bfin_gpio_irq_prepare(gpionr);
 741
 742         } else {
 743                 __clear_bit(gpionr, gpio_enabled);
 744                 return 0;
 745         }
 746
 747         set_gpio_inen(gpionr, 0);
 748         set_gpio_dir(gpionr, 0);
 749
 750         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 751             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 752                 set_gpio_both(gpionr, 1);
 753         else
 754                 set_gpio_both(gpionr, 0);
 755
 756         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 757                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 758         else
 759                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 760
 761         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 762                 set_gpio_edge(gpionr, 1);
 763                 set_gpio_inen(gpionr, 1);
 764                 set_gpio_data(gpionr, 0);
 765
 766         } else {
 767                 set_gpio_edge(gpionr, 0);
 768                 set_gpio_inen(gpionr, 1);
 769         }
 770
 771         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 772                 bfin_set_irq_handler(irq, handle_edge_irq);
 773         else
 774                 bfin_set_irq_handler(irq, handle_level_irq);
 775
 776         return 0;
 777 }
 778
 779 #ifdef CONFIG_PM
 780 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 781 {
 782         return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
 783 }
 784 #else
 785 # define bfin_gpio_set_wake NULL
 786 #endif
 787
 788 static void bfin_demux_gpio_block(unsigned int irq)
 789 {
 790         unsigned int gpio, mask;
 791
 792         gpio = irq_to_gpio(irq);
 793         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 794
 795         while (mask) {
 796                 if (mask & 1)
 797                         bfin_handle_irq(irq);
 798                 irq++;
 799                 mask >>= 1;
 800         }
 801 }
 802
 803 void bfin_demux_gpio_irq(unsigned int inta_irq,
 804                         struct irq_desc *desc)
 805 {
 806         unsigned int irq;
 807
 808         switch (inta_irq) {
 809 #if defined(BF537_FAMILY)
 810         case IRQ_PF_INTA_PG_INTA:
 811                 bfin_demux_gpio_block(IRQ_PF0);
 812                 irq = IRQ_PG0;
 813                 break;
 814         case IRQ_PH_INTA_MAC_RX:
 815                 irq = IRQ_PH0;
 816                 break;
 817 #elif defined(BF533_FAMILY)
 818         case IRQ_PROG_INTA:
 819                 irq = IRQ_PF0;
 820                 break;
 821 #elif defined(BF538_FAMILY)
 822         case IRQ_PORTF_INTA:
 823                 irq = IRQ_PF0;
 824                 break;
 825 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 826         case IRQ_PORTF_INTA:
 827                 irq = IRQ_PF0;
 828                 break;
 829         case IRQ_PORTG_INTA:
 830                 irq = IRQ_PG0;
 831                 break;
 832         case IRQ_PORTH_INTA:
 833                 irq = IRQ_PH0;
 834                 break;
 835 #elif defined(CONFIG_BF561)
 836         case IRQ_PROG0_INTA:
 837                 irq = IRQ_PF0;
 838                 break;
 839         case IRQ_PROG1_INTA:
 840                 irq = IRQ_PF16;
 841                 break;
 842         case IRQ_PROG2_INTA:
 843                 irq = IRQ_PF32;
 844                 break;
 845 #endif
 846         default:
 847                 BUG();
 848                 return;
 849         }
 850
 851         bfin_demux_gpio_block(irq);
 852 }
 853
 854 #else
 855
 856 #define NR_PINT_BITS            32
 857 #define IRQ_NOT_AVAIL           0xFF
 858
 859 #define PINT_2_BANK(x)          ((x) >> 5)
 860 #define PINT_2_BIT(x)           ((x) & 0x1F)
 861 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 862
 863 static unsigned char irq2pint_lut[NR_PINTS];
 864 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 865
 866 static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
 867         (struct bfin_pint_regs *)PINT0_MASK_SET,
 868         (struct bfin_pint_regs *)PINT1_MASK_SET,
 869         (struct bfin_pint_regs *)PINT2_MASK_SET,
 870         (struct bfin_pint_regs *)PINT3_MASK_SET,
 871 #ifdef CONFIG_BF60x
 872         (struct bfin_pint_regs *)PINT4_MASK_SET,
 873         (struct bfin_pint_regs *)PINT5_MASK_SET,
 874 #endif
 875 };
 876
 877 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 878 {
 879         unsigned int irq_base;
 880
 881 #ifndef CONFIG_BF60x
 882         if (bank < 2) {         /*PA-PB */
 883                 irq_base = IRQ_PA0 + bmap * 16;
 884         } else {                /*PC-PJ */
 885                 irq_base = IRQ_PC0 + bmap * 16;
 886         }
 887 #else
 888         irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
 889 #endif
 890         return irq_base;
 891 }
 892
 893         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 894 void init_pint_lut(void)
 895 {
 896         u16 bank, bit, irq_base, bit_pos;
 897         u32 pint_assign;
 898         u8 bmap;
 899
 900         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 901
 902         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 903
 904                 pint_assign = pint[bank]->assign;
 905
 906                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 907
 908                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 909
 910                         irq_base = get_irq_base(bank, bmap);
 911
 912                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 913                         bit_pos = bit + bank * NR_PINT_BITS;
 914
 915                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 916                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 917                 }
 918         }
 919 }
 920
 921 static void bfin_gpio_ack_irq(struct irq_data *d)
 922 {
 923         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 924         u32 pintbit = PINT_BIT(pint_val);
 925         u32 bank = PINT_2_BANK(pint_val);
 926
 927         if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
 928                 if (pint[bank]->invert_set & pintbit)
 929                         pint[bank]->invert_clear = pintbit;
 930                 else
 931                         pint[bank]->invert_set = pintbit;
 932         }
 933         pint[bank]->request = pintbit;
 934
 935 }
 936
 937 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
 938 {
 939         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 940         u32 pintbit = PINT_BIT(pint_val);
 941         u32 bank = PINT_2_BANK(pint_val);
 942
 943         if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
 944                 if (pint[bank]->invert_set & pintbit)
 945                         pint[bank]->invert_clear = pintbit;
 946                 else
 947                         pint[bank]->invert_set = pintbit;
 948         }
 949
 950         pint[bank]->request = pintbit;
 951         pint[bank]->mask_clear = pintbit;
 952 }
 953
 954 static void bfin_gpio_mask_irq(struct irq_data *d)
 955 {
 956         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 957
 958         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 959 }
 960
 961 static void bfin_gpio_unmask_irq(struct irq_data *d)
 962 {
 963         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 964         u32 pintbit = PINT_BIT(pint_val);
 965         u32 bank = PINT_2_BANK(pint_val);
 966
 967         pint[bank]->mask_set = pintbit;
 968 }
 969
 970 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
 971 {
 972         unsigned int irq = d->irq;
 973         u32 gpionr = irq_to_gpio(irq);
 974         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 975
 976         if (pint_val == IRQ_NOT_AVAIL) {
 977                 printk(KERN_ERR
 978                 "GPIO IRQ %d :Not in PINT Assign table "
 979                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 980                 return -ENODEV;
 981         }
 982
 983         if (__test_and_set_bit(gpionr, gpio_enabled))
 984                 bfin_gpio_irq_prepare(gpionr);
 985
 986         bfin_gpio_unmask_irq(d);
 987
 988         return 0;
 989 }
 990
 991 static void bfin_gpio_irq_shutdown(struct irq_data *d)
 992 {
 993         u32 gpionr = irq_to_gpio(d->irq);
 994
 995         bfin_gpio_mask_irq(d);
 996         __clear_bit(gpionr, gpio_enabled);
 997         bfin_gpio_irq_free(gpionr);
 998 }
 999
1000 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
1001 {
1002         unsigned int irq = d->irq;
1003         int ret;
1004         char buf[16];
1005         u32 gpionr = irq_to_gpio(irq);
1006         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1007         u32 pintbit = PINT_BIT(pint_val);
1008         u32 bank = PINT_2_BANK(pint_val);
1009
1010         if (pint_val == IRQ_NOT_AVAIL)
1011                 return -ENODEV;
1012
1013         if (type == IRQ_TYPE_PROBE) {
1014                 /* only probe unenabled GPIO interrupt lines */
1015                 if (test_bit(gpionr, gpio_enabled))
1016                         return 0;
1017                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1018         }
1019
1020         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
1021                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1022
1023                 snprintf(buf, 16, "gpio-irq%d", irq);
1024                 ret = bfin_gpio_irq_request(gpionr, buf);
1025                 if (ret)
1026                         return ret;
1027
1028                 if (__test_and_set_bit(gpionr, gpio_enabled))
1029                         bfin_gpio_irq_prepare(gpionr);
1030
1031         } else {
1032                 __clear_bit(gpionr, gpio_enabled);
1033                 return 0;
1034         }
1035
1036         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
1037                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
1038         else
1039                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
1040
1041         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
1042             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1043                 if (gpio_get_value(gpionr))
1044                         pint[bank]->invert_set = pintbit;
1045                 else
1046                         pint[bank]->invert_clear = pintbit;
1047         }
1048
1049         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1050                 pint[bank]->edge_set = pintbit;
1051                 bfin_set_irq_handler(irq, handle_edge_irq);
1052         } else {
1053                 pint[bank]->edge_clear = pintbit;
1054                 bfin_set_irq_handler(irq, handle_level_irq);
1055         }
1056
1057         return 0;
1058 }
1059
1060 #ifdef CONFIG_PM
1061 static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS];
1062 static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
1063
1064 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
1065 {
1066         u32 pint_irq;
1067         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1068         u32 bank = PINT_2_BANK(pint_val);
1069
1070         switch (bank) {
1071         case 0:
1072                 pint_irq = IRQ_PINT0;
1073                 break;
1074         case 2:
1075                 pint_irq = IRQ_PINT2;
1076                 break;
1077         case 3:
1078                 pint_irq = IRQ_PINT3;
1079                 break;
1080         case 1:
1081                 pint_irq = IRQ_PINT1;
1082                 break;
1083 #ifdef CONFIG_BF60x
1084         case 4:
1085                 pint_irq = IRQ_PINT4;
1086                 break;
1087         case 5:
1088                 pint_irq = IRQ_PINT5;
1089                 break;
1090 #endif
1091         default:
1092                 return -EINVAL;
1093         }
1094
1095         bfin_internal_set_wake(pint_irq, state);
1096
1097         return 0;
1098 }
1099
1100 void bfin_pint_suspend(void)
1101 {
1102         u32 bank;
1103
1104         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
1105                 save_pint_reg[bank].mask_set = pint[bank]->mask_set;
1106                 save_pint_reg[bank].assign = pint[bank]->assign;
1107                 save_pint_reg[bank].edge_set = pint[bank]->edge_set;
1108                 save_pint_reg[bank].invert_set = pint[bank]->invert_set;
1109         }
1110 }
1111
1112 void bfin_pint_resume(void)
1113 {
1114         u32 bank;
1115
1116         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
1117                 pint[bank]->mask_set = save_pint_reg[bank].mask_set;
1118                 pint[bank]->assign = save_pint_reg[bank].assign;
1119                 pint[bank]->edge_set = save_pint_reg[bank].edge_set;
1120                 pint[bank]->invert_set = save_pint_reg[bank].invert_set;
1121         }
1122 }
1123
1124 #ifdef SEC_GCTL
1125 static int sec_suspend(void)
1126 {
1127         u32 bank;
1128
1129         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
1130                 save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0));
1131         return 0;
1132 }
1133
1134 static void sec_resume(void)
1135 {
1136         u32 bank;
1137
1138         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1139         udelay(100);
1140         bfin_write_SEC_GCTL(SEC_GCTL_EN);
1141         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1142
1143         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
1144                 bfin_write_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
1145 }
1146
1147 static struct syscore_ops sec_pm_syscore_ops = {
1148         .suspend = sec_suspend,
1149         .resume = sec_resume,
1150 };
1151 #endif
1152 #else
1153 # define bfin_gpio_set_wake NULL
1154 #endif
1155
1156 void bfin_demux_gpio_irq(unsigned int inta_irq,
1157                         struct irq_desc *desc)
1158 {
1159         u32 bank, pint_val;
1160         u32 request, irq;
1161         u32 level_mask;
1162         int umask = 0;
1163         struct irq_chip *chip = irq_desc_get_chip(desc);
1164
1165         if (chip->irq_mask_ack) {
1166                 chip->irq_mask_ack(&desc->irq_data);
1167         } else {
1168                 chip->irq_mask(&desc->irq_data);
1169                 if (chip->irq_ack)
1170                         chip->irq_ack(&desc->irq_data);
1171         }
1172
1173         switch (inta_irq) {
1174         case IRQ_PINT0:
1175                 bank = 0;
1176                 break;
1177         case IRQ_PINT2:
1178                 bank = 2;
1179                 break;
1180         case IRQ_PINT3:
1181                 bank = 3;
1182                 break;
1183         case IRQ_PINT1:
1184                 bank = 1;
1185                 break;
1186 #ifdef CONFIG_BF60x
1187         case IRQ_PINT4:
1188                 bank = 4;
1189                 break;
1190         case IRQ_PINT5:
1191                 bank = 5;
1192                 break;
1193 #endif
1194         default:
1195                 return;
1196         }
1197
1198         pint_val = bank * NR_PINT_BITS;
1199
1200         request = pint[bank]->request;
1201
1202         level_mask = pint[bank]->edge_set & request;
1203
1204         while (request) {
1205                 if (request & 1) {
1206                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
1207                         if (level_mask & PINT_BIT(pint_val)) {
1208                                 umask = 1;
1209                                 chip->irq_unmask(&desc->irq_data);
1210                         }
1211                         bfin_handle_irq(irq);
1212                 }
1213                 pint_val++;
1214                 request >>= 1;
1215         }
1216
1217         if (!umask)
1218                 chip->irq_unmask(&desc->irq_data);
1219 }
1220 #endif
1221
1222 static struct irq_chip bfin_gpio_irqchip = {
1223         .name = "GPIO",
1224         .irq_ack = bfin_gpio_ack_irq,
1225         .irq_mask = bfin_gpio_mask_irq,
1226         .irq_mask_ack = bfin_gpio_mask_ack_irq,
1227         .irq_unmask = bfin_gpio_unmask_irq,
1228         .irq_disable = bfin_gpio_mask_irq,
1229         .irq_enable = bfin_gpio_unmask_irq,
1230         .irq_set_type = bfin_gpio_irq_type,
1231         .irq_startup = bfin_gpio_irq_startup,
1232         .irq_shutdown = bfin_gpio_irq_shutdown,
1233         .irq_set_wake = bfin_gpio_set_wake,
1234 };
1235
1236 void __cpuinit init_exception_vectors(void)
1237 {
1238         /* cannot program in software:
1239          * evt0 - emulation (jtag)
1240          * evt1 - reset
1241          */
1242         bfin_write_EVT2(evt_nmi);
1243         bfin_write_EVT3(trap);
1244         bfin_write_EVT5(evt_ivhw);
1245         bfin_write_EVT6(evt_timer);
1246         bfin_write_EVT7(evt_evt7);
1247         bfin_write_EVT8(evt_evt8);
1248         bfin_write_EVT9(evt_evt9);
1249         bfin_write_EVT10(evt_evt10);
1250         bfin_write_EVT11(evt_evt11);
1251         bfin_write_EVT12(evt_evt12);
1252         bfin_write_EVT13(evt_evt13);
1253         bfin_write_EVT14(evt_evt14);
1254         bfin_write_EVT15(evt_system_call);
1255         CSYNC();
1256 }
1257
1258 #ifndef SEC_GCTL
1259 /*
1260  * This function should be called during kernel startup to initialize
1261  * the BFin IRQ handling routines.
1262  */
1263
1264 int __init init_arch_irq(void)
1265 {
1266         int irq;
1267         unsigned long ilat = 0;
1268
1269         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
1270 #ifdef SIC_IMASK0
1271         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1272         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1273 # ifdef SIC_IMASK2
1274         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1275 # endif
1276 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1277         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1278         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1279 # endif
1280 #else
1281         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1282 #endif
1283
1284         local_irq_disable();
1285
1286 #if BFIN_GPIO_PINT
1287 # ifdef CONFIG_PINTx_REASSIGN
1288         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1289         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1290         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1291         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1292 # endif
1293         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1294         init_pint_lut();
1295 #endif
1296
1297         for (irq = 0; irq <= SYS_IRQS; irq++) {
1298                 if (irq <= IRQ_CORETMR)
1299                         irq_set_chip(irq, &bfin_core_irqchip);
1300                 else
1301                         irq_set_chip(irq, &bfin_internal_irqchip);
1302
1303                 switch (irq) {
1304 #if BFIN_GPIO_PINT
1305                 case IRQ_PINT0:
1306                 case IRQ_PINT1:
1307                 case IRQ_PINT2:
1308                 case IRQ_PINT3:
1309 #elif defined(BF537_FAMILY)
1310                 case IRQ_PH_INTA_MAC_RX:
1311                 case IRQ_PF_INTA_PG_INTA:
1312 #elif defined(BF533_FAMILY)
1313                 case IRQ_PROG_INTA:
1314 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1315                 case IRQ_PORTF_INTA:
1316                 case IRQ_PORTG_INTA:
1317                 case IRQ_PORTH_INTA:
1318 #elif defined(CONFIG_BF561)
1319                 case IRQ_PROG0_INTA:
1320                 case IRQ_PROG1_INTA:
1321                 case IRQ_PROG2_INTA:
1322 #elif defined(BF538_FAMILY)
1323                 case IRQ_PORTF_INTA:
1324 #endif
1325                         irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1326                         break;
1327 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1328                 case IRQ_MAC_ERROR:
1329                         irq_set_chained_handler(irq,
1330                                                 bfin_demux_mac_status_irq);
1331                         break;
1332 #endif
1333 #if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1334                 case IRQ_SUPPLE_0:
1335                 case IRQ_SUPPLE_1:
1336                         irq_set_handler(irq, handle_percpu_irq);
1337                         break;
1338 #endif
1339
1340 #ifdef CONFIG_TICKSOURCE_CORETMR
1341                 case IRQ_CORETMR:
1342 # ifdef CONFIG_SMP
1343                         irq_set_handler(irq, handle_percpu_irq);
1344 # else
1345                         irq_set_handler(irq, handle_simple_irq);
1346 # endif
1347                         break;
1348 #endif
1349
1350 #ifdef CONFIG_TICKSOURCE_GPTMR0
1351                 case IRQ_TIMER0:
1352                         irq_set_handler(irq, handle_simple_irq);
1353                         break;
1354 #endif
1355
1356                 default:
1357 #ifdef CONFIG_IPIPE
1358                         irq_set_handler(irq, handle_level_irq);
1359 #else
1360                         irq_set_handler(irq, handle_simple_irq);
1361 #endif
1362                         break;
1363                 }
1364         }
1365
1366         init_mach_irq();
1367
1368 #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1369         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1370                 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1371                                          handle_level_irq);
1372 #endif
1373         /* if configured as edge, then will be changed to do_edge_IRQ */
1374         for (irq = GPIO_IRQ_BASE;
1375                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1376                 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1377                                          handle_level_irq);
1378         bfin_write_IMASK(0);
1379         CSYNC();
1380         ilat = bfin_read_ILAT();
1381         CSYNC();
1382         bfin_write_ILAT(ilat);
1383         CSYNC();
1384
1385         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1386         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1387          * local_irq_enable()
1388          */
1389         program_IAR();
1390         /* Therefore it's better to setup IARs before interrupts enabled */
1391         search_IAR();
1392
1393         /* Enable interrupts IVG7-15 */
1394         bfin_irq_flags |= IMASK_IVG15 |
1395                 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1396                 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1397
1398         bfin_sti(bfin_irq_flags);
1399
1400         /* This implicitly covers ANOMALY_05000171
1401          * Boot-ROM code modifies SICA_IWRx wakeup registers
1402          */
1403 #ifdef SIC_IWR0
1404         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1405 # ifdef SIC_IWR1
1406         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1407          * will screw up the bootrom as it relies on MDMA0/1 waking it
1408          * up from IDLE instructions.  See this report for more info:
1409          * http://blackfin.uclinux.org/gf/tracker/4323
1410          */
1411         if (ANOMALY_05000435)
1412                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1413         else
1414                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1415 # endif
1416 # ifdef SIC_IWR2
1417         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1418 # endif
1419 #else
1420         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1421 #endif
1422         return 0;
1423 }
1424
1425 #ifdef CONFIG_DO_IRQ_L1
1426 __attribute__((l1_text))
1427 #endif
1428 static int vec_to_irq(int vec)
1429 {
1430         struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1431         struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1432         unsigned long sic_status[3];
1433         if (likely(vec == EVT_IVTMR_P))
1434                 return IRQ_CORETMR;
1435 #ifdef SIC_ISR
1436         sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1437 #else
1438         if (smp_processor_id()) {
1439 # ifdef SICB_ISR0
1440                 /* This will be optimized out in UP mode. */
1441                 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1442                 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1443 # endif
1444         } else {
1445                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1446                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1447         }
1448 #endif
1449 #ifdef SIC_ISR2
1450         sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1451 #endif
1452
1453         for (;; ivg++) {
1454                 if (ivg >= ivg_stop)
1455                         return -1;
1456 #ifdef SIC_ISR
1457                 if (sic_status[0] & ivg->isrflag)
1458 #else
1459                 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1460 #endif
1461                         return ivg->irqno;
1462         }
1463 }
1464
1465 #else /* SEC_GCTL */
1466
1467 /*
1468  * This function should be called during kernel startup to initialize
1469  * the BFin IRQ handling routines.
1470  */
1471
1472 int __init init_arch_irq(void)
1473 {
1474         int irq;
1475         unsigned long ilat = 0;
1476
1477         bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1478
1479         local_irq_disable();
1480
1481 #if BFIN_GPIO_PINT
1482 # ifdef CONFIG_PINTx_REASSIGN
1483         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1484         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1485         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1486         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1487         pint[4]->assign = CONFIG_PINT4_ASSIGN;
1488         pint[5]->assign = CONFIG_PINT5_ASSIGN;
1489 # endif
1490         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1491         init_pint_lut();
1492 #endif
1493
1494         for (irq = 0; irq <= SYS_IRQS; irq++) {
1495                 if (irq <= IRQ_CORETMR) {
1496                         irq_set_chip(irq, &bfin_core_irqchip);
1497 #ifdef CONFIG_TICKSOURCE_CORETMR
1498                         if (irq == IRQ_CORETMR)
1499 # ifdef CONFIG_SMP
1500                                 irq_set_handler(irq, handle_percpu_irq);
1501 # else
1502                                 irq_set_handler(irq, handle_simple_irq);
1503 # endif
1504 #endif
1505                 } else if (irq < BFIN_IRQ(0)) {
1506                         irq_set_chip_and_handler(irq, &bfin_internal_irqchip,
1507                                         handle_simple_irq);
1508                 } else if (irq < CORE_IRQS && irq != IRQ_CGU_EVT) {
1509                         irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1510                                         handle_sec_fault);
1511                 } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
1512                         irq_set_chip(irq, &bfin_sec_irqchip);
1513                         irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1514                 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
1515                         irq_set_chip(irq, &bfin_sec_irqchip);
1516                         irq_set_handler(irq, handle_percpu_irq);
1517                 } else {
1518                         irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1519                                         handle_fasteoi_irq);
1520                         __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1521                 }
1522         }
1523         for (irq = GPIO_IRQ_BASE;
1524                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1525                 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1526                                         handle_level_irq);
1527
1528         bfin_write_IMASK(0);
1529         CSYNC();
1530         ilat = bfin_read_ILAT();
1531         CSYNC();
1532         bfin_write_ILAT(ilat);
1533         CSYNC();
1534
1535         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1536
1537         /* Enable interrupts IVG7-15 */
1538         bfin_irq_flags |= IMASK_IVG15 |
1539             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1540             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1541
1542
1543         bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
1544         bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
1545         bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
1546         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1547         udelay(100);
1548         bfin_write_SEC_GCTL(SEC_GCTL_EN);
1549         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1550         bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1551
1552         init_software_driven_irq();
1553         register_syscore_ops(&sec_pm_syscore_ops);
1554
1555         return 0;
1556 }
1557
1558 #ifdef CONFIG_DO_IRQ_L1
1559 __attribute__((l1_text))
1560 #endif
1561 static int vec_to_irq(int vec)
1562 {
1563         if (likely(vec == EVT_IVTMR_P))
1564                 return IRQ_CORETMR;
1565
1566         return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1567 }
1568 #endif  /* SEC_GCTL */
1569
1570 #ifdef CONFIG_DO_IRQ_L1
1571 __attribute__((l1_text))
1572 #endif
1573 void do_irq(int vec, struct pt_regs *fp)
1574 {
1575         int irq = vec_to_irq(vec);
1576         if (irq == -1)
1577                 return;
1578         asm_do_IRQ(irq, fp);
1579 }
1580
1581 #ifdef CONFIG_IPIPE
1582
1583 int __ipipe_get_irq_priority(unsigned irq)
1584 {
1585         int ient, prio;
1586
1587         if (irq <= IRQ_CORETMR)
1588                 return irq;
1589
1590 #ifdef SEC_GCTL
1591         if (irq >= BFIN_IRQ(0))
1592                 return IVG11;
1593 #else
1594         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1595                 struct ivgx *ivg = ivg_table + ient;
1596                 if (ivg->irqno == irq) {
1597                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1598                                 if (ivg7_13[prio].ifirst <= ivg &&
1599                                     ivg7_13[prio].istop > ivg)
1600                                         return IVG7 + prio;
1601                         }
1602                 }
1603         }
1604 #endif
1605
1606         return IVG15;
1607 }
1608
1609 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1610 #ifdef CONFIG_DO_IRQ_L1
1611 __attribute__((l1_text))
1612 #endif
1613 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1614 {
1615         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1616         struct ipipe_domain *this_domain = __ipipe_current_domain;
1617         int irq, s = 0;
1618
1619         irq = vec_to_irq(vec);
1620         if (irq == -1)
1621                 return 0;
1622
1623         if (irq == IRQ_SYSTMR) {
1624 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1625                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1626 #endif
1627                 /* This is basically what we need from the register frame. */
1628                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1629                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1630                 if (this_domain != ipipe_root_domain)
1631                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1632                 else
1633                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1634         }
1635
1636         /*
1637          * We don't want Linux interrupt handlers to run at the
1638          * current core priority level (i.e. < EVT15), since this
1639          * might delay other interrupts handled by a high priority
1640          * domain. Here is what we do instead:
1641          *
1642          * - we raise the SYNCDEFER bit to prevent
1643          * __ipipe_handle_irq() to sync the pipeline for the root
1644          * stage for the incoming interrupt. Upon return, that IRQ is
1645          * pending in the interrupt log.
1646          *
1647          * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1648          * that _schedule_and_signal_from_int will eventually sync the
1649          * pipeline from EVT15.
1650          */
1651         if (this_domain == ipipe_root_domain) {
1652                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1653                 barrier();
1654         }
1655
1656         ipipe_trace_irq_entry(irq);
1657         __ipipe_handle_irq(irq, regs);
1658         ipipe_trace_irq_exit(irq);
1659
1660         if (user_mode(regs) &&
1661             !ipipe_test_foreign_stack() &&
1662             (current->ipipe_flags & PF_EVTRET) != 0) {
1663                 /*
1664                  * Testing for user_regs() does NOT fully eliminate
1665                  * foreign stack contexts, because of the forged
1666                  * interrupt returns we do through
1667                  * __ipipe_call_irqtail. In that case, we might have
1668                  * preempted a foreign stack context in a high
1669                  * priority domain, with a single interrupt level now
1670                  * pending after the irqtail unwinding is done. In
1671                  * which case user_mode() is now true, and the event
1672                  * gets dispatched spuriously.
1673                  */
1674                 current->ipipe_flags &= ~PF_EVTRET;
1675                 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1676         }
1677
1678         if (this_domain == ipipe_root_domain) {
1679                 set_thread_flag(TIF_IRQ_SYNC);
1680                 if (!s) {
1681                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1682                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1683                 }
1684         }
1685
1686         return 0;
1687 }
1688
1689 #endif /* CONFIG_IPIPE */