arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * Set up the interrupt priorities
   3  *
   4  * Copyright  2004-2009 Analog Devices Inc.
   5  *                 2003 Bas Vermeulen <bas@buyways.nl>
   6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
   7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
   8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *                 1996 Roman Zippel
  10  *
  11  * Licensed under the GPL-2
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/irq.h>
  18 #include <linux/sched.h>
  19 #include <linux/syscore_ops.h>
  20 #include <asm/delay.h>
  21 #ifdef CONFIG_IPIPE
  22 #include <linux/ipipe.h>
  23 #endif
  24 #include <asm/traps.h>
  25 #include <asm/blackfin.h>
  26 #include <asm/gpio.h>
  27 #include <asm/irq_handler.h>
  28 #include <asm/dpmc.h>
  29
  30 #ifndef CONFIG_BF60x
  31 # define SIC_SYSIRQ(irq)        (irq - (IRQ_CORETMR + 1))
  32 #else
  33 # define SIC_SYSIRQ(irq)        ((irq) - IVG15)
  34 #endif
  35
  36 /*
  37  * NOTES:
  38  * - we have separated the physical Hardware interrupt from the
  39  * levels that the LINUX kernel sees (see the description in irq.h)
  40  * -
  41  */
  42
  43 #ifndef CONFIG_SMP
  44 /* Initialize this to an actual value to force it into the .data
  45  * section so that we know it is properly initialized at entry into
  46  * the kernel but before bss is initialized to zero (which is where
  47  * it would live otherwise).  The 0x1f magic represents the IRQs we
  48  * cannot actually mask out in hardware.
  49  */
  50 unsigned long bfin_irq_flags = 0x1f;
  51 EXPORT_SYMBOL(bfin_irq_flags);
  52 #endif
  53
  54 #ifdef CONFIG_PM
  55 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  56 unsigned vr_wakeup;
  57 #endif
  58
  59 #ifndef CONFIG_BF60x
  60 static struct ivgx {
  61         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  62         unsigned int irqno;
  63         /* corresponding bit in the SIC_ISR register */
  64         unsigned int isrflag;
  65 } ivg_table[NR_PERI_INTS];
  66
  67 static struct ivg_slice {
  68         /* position of first irq in ivg_table for given ivg */
  69         struct ivgx *ifirst;
  70         struct ivgx *istop;
  71 } ivg7_13[IVG13 - IVG7 + 1];
  72
  73
  74 /*
  75  * Search SIC_IAR and fill tables with the irqvalues
  76  * and their positions in the SIC_ISR register.
  77  */
  78 static void __init search_IAR(void)
  79 {
  80         unsigned ivg, irq_pos = 0;
  81         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  82                 int irqN;
  83
  84                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  85
  86                 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
  87                         int irqn;
  88                         u32 iar =
  89                                 bfin_read32((unsigned long *)SIC_IAR0 +
  90 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
  91         defined(CONFIG_BF538) || defined(CONFIG_BF539)
  92                                 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
  93 #else
  94                                 (irqN >> 3)
  95 #endif
  96                                 );
  97                         for (irqn = irqN; irqn < irqN + 4; ++irqn) {
  98                                 int iar_shift = (irqn & 7) * 4;
  99                                 if (ivg == (0xf & (iar >> iar_shift))) {
 100                                         ivg_table[irq_pos].irqno = IVG7 + irqn;
 101                                         ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 102                                         ivg7_13[ivg].istop++;
 103                                         irq_pos++;
 104                                 }
 105                         }
 106                 }
 107         }
 108 }
 109 #endif
 110
 111 /*
 112  * This is for core internal IRQs
 113  */
 114 void bfin_ack_noop(struct irq_data *d)
 115 {
 116         /* Dummy function.  */
 117 }
 118
 119 static void bfin_core_mask_irq(struct irq_data *d)
 120 {
 121         bfin_irq_flags &= ~(1 << d->irq);
 122         if (!hard_irqs_disabled())
 123                 hard_local_irq_enable();
 124 }
 125
 126 static void bfin_core_unmask_irq(struct irq_data *d)
 127 {
 128         bfin_irq_flags |= 1 << d->irq;
 129         /*
 130          * If interrupts are enabled, IMASK must contain the same value
 131          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 132          * are currently disabled we need not do anything; one of the
 133          * callers will take care of setting IMASK to the proper value
 134          * when reenabling interrupts.
 135          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 136          * what we need.
 137          */
 138         if (!hard_irqs_disabled())
 139                 hard_local_irq_enable();
 140         return;
 141 }
 142
 143 void bfin_internal_mask_irq(unsigned int irq)
 144 {
 145         unsigned long flags = hard_local_irq_save();
 146 #ifndef CONFIG_BF60x
 147 #ifdef SIC_IMASK0
 148         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
 149         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
 150         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 151                         ~(1 << mask_bit));
 152 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
 153         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 154                         ~(1 << mask_bit));
 155 # endif
 156 #else
 157         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 158                         ~(1 << SIC_SYSIRQ(irq)));
 159 #endif /* end of SIC_IMASK0 */
 160 #endif
 161         hard_local_irq_restore(flags);
 162 }
 163
 164 static void bfin_internal_mask_irq_chip(struct irq_data *d)
 165 {
 166         bfin_internal_mask_irq(d->irq);
 167 }
 168
 169 #ifdef CONFIG_SMP
 170 void bfin_internal_unmask_irq_affinity(unsigned int irq,
 171                 const struct cpumask *affinity)
 172 #else
 173 void bfin_internal_unmask_irq(unsigned int irq)
 174 #endif
 175 {
 176         unsigned long flags = hard_local_irq_save();
 177
 178 #ifndef CONFIG_BF60x
 179 #ifdef SIC_IMASK0
 180         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
 181         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
 182 # ifdef CONFIG_SMP
 183         if (cpumask_test_cpu(0, affinity))
 184 # endif
 185                 bfin_write_SIC_IMASK(mask_bank,
 186                                 bfin_read_SIC_IMASK(mask_bank) |
 187                                 (1 << mask_bit));
 188 # ifdef CONFIG_SMP
 189         if (cpumask_test_cpu(1, affinity))
 190                 bfin_write_SICB_IMASK(mask_bank,
 191                                 bfin_read_SICB_IMASK(mask_bank) |
 192                                 (1 << mask_bit));
 193 # endif
 194 #else
 195         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 196                         (1 << SIC_SYSIRQ(irq)));
 197 #endif
 198 #endif
 199         hard_local_irq_restore(flags);
 200 }
 201
 202 #ifdef CONFIG_BF60x
 203 static void bfin_sec_preflow_handler(struct irq_data *d)
 204 {
 205         unsigned long flags = hard_local_irq_save();
 206         unsigned int sid = SIC_SYSIRQ(d->irq);
 207
 208         bfin_write_SEC_SCI(0, SEC_CSID, sid);
 209
 210         hard_local_irq_restore(flags);
 211 }
 212
 213 static void bfin_sec_mask_ack_irq(struct irq_data *d)
 214 {
 215         unsigned long flags = hard_local_irq_save();
 216         unsigned int sid = SIC_SYSIRQ(d->irq);
 217
 218         bfin_write_SEC_SCI(0, SEC_CSID, sid);
 219
 220         hard_local_irq_restore(flags);
 221 }
 222
 223 static void bfin_sec_unmask_irq(struct irq_data *d)
 224 {
 225         unsigned long flags = hard_local_irq_save();
 226         unsigned int sid = SIC_SYSIRQ(d->irq);
 227
 228         bfin_write32(SEC_END, sid);
 229
 230         hard_local_irq_restore(flags);
 231 }
 232
 233 static void bfin_sec_enable_ssi(unsigned int sid)
 234 {
 235         unsigned long flags = hard_local_irq_save();
 236         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 237
 238         reg_sctl |= SEC_SCTL_SRC_EN;
 239         bfin_write_SEC_SCTL(sid, reg_sctl);
 240
 241         hard_local_irq_restore(flags);
 242 }
 243
 244 static void bfin_sec_disable_ssi(unsigned int sid)
 245 {
 246         unsigned long flags = hard_local_irq_save();
 247         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 248
 249         reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
 250         bfin_write_SEC_SCTL(sid, reg_sctl);
 251
 252         hard_local_irq_restore(flags);
 253 }
 254
 255 static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
 256 {
 257         unsigned long flags = hard_local_irq_save();
 258         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 259
 260         reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
 261         bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
 262
 263         hard_local_irq_restore(flags);
 264 }
 265
 266 static void bfin_sec_enable_sci(unsigned int sid)
 267 {
 268         unsigned long flags = hard_local_irq_save();
 269         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 270
 271         if (sid == SIC_SYSIRQ(IRQ_WATCH0))
 272                 reg_sctl |= SEC_SCTL_FAULT_EN;
 273         else
 274                 reg_sctl |= SEC_SCTL_INT_EN;
 275         bfin_write_SEC_SCTL(sid, reg_sctl);
 276
 277         hard_local_irq_restore(flags);
 278 }
 279
 280 static void bfin_sec_disable_sci(unsigned int sid)
 281 {
 282         unsigned long flags = hard_local_irq_save();
 283         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 284
 285         reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
 286         bfin_write_SEC_SCTL(sid, reg_sctl);
 287
 288         hard_local_irq_restore(flags);
 289 }
 290
 291 static void bfin_sec_enable(struct irq_data *d)
 292 {
 293         unsigned long flags = hard_local_irq_save();
 294         unsigned int sid = SIC_SYSIRQ(d->irq);
 295
 296         bfin_sec_enable_sci(sid);
 297         bfin_sec_enable_ssi(sid);
 298
 299         hard_local_irq_restore(flags);
 300 }
 301
 302 static void bfin_sec_disable(struct irq_data *d)
 303 {
 304         unsigned long flags = hard_local_irq_save();
 305         unsigned int sid = SIC_SYSIRQ(d->irq);
 306
 307         bfin_sec_disable_sci(sid);
 308         bfin_sec_disable_ssi(sid);
 309
 310         hard_local_irq_restore(flags);
 311 }
 312
 313 static void bfin_sec_raise_irq(unsigned int sid)
 314 {
 315         unsigned long flags = hard_local_irq_save();
 316
 317         bfin_write32(SEC_RAISE, sid);
 318
 319         hard_local_irq_restore(flags);
 320 }
 321
 322 static void init_software_driven_irq(void)
 323 {
 324         bfin_sec_set_ssi_coreid(34, 0);
 325         bfin_sec_set_ssi_coreid(35, 1);
 326         bfin_sec_set_ssi_coreid(36, 0);
 327         bfin_sec_set_ssi_coreid(37, 1);
 328 }
 329
 330 void bfin_sec_resume(void)
 331 {
 332         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
 333         udelay(100);
 334         bfin_write_SEC_GCTL(SEC_GCTL_EN);
 335         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
 336 }
 337
 338 void handle_sec_sfi_fault(uint32_t gstat)
 339 {
 340
 341 }
 342
 343 void handle_sec_sci_fault(uint32_t gstat)
 344 {
 345         uint32_t core_id;
 346         uint32_t cstat;
 347
 348         core_id = gstat & SEC_GSTAT_SCI;
 349         cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
 350         if (cstat & SEC_CSTAT_ERR) {
 351                 switch (cstat & SEC_CSTAT_ERRC) {
 352                 case SEC_CSTAT_ACKERR:
 353                         printk(KERN_DEBUG "sec ack err\n");
 354                         break;
 355                 default:
 356                         printk(KERN_DEBUG "sec sci unknow err\n");
 357                 }
 358         }
 359
 360 }
 361
 362 void handle_sec_ssi_fault(uint32_t gstat)
 363 {
 364         uint32_t sid;
 365         uint32_t sstat;
 366
 367         sid = gstat & SEC_GSTAT_SID;
 368         sstat = bfin_read_SEC_SSTAT(sid);
 369
 370 }
 371
 372 void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
 373 {
 374         uint32_t sec_gstat;
 375
 376         raw_spin_lock(&desc->lock);
 377
 378         sec_gstat = bfin_read32(SEC_GSTAT);
 379         if (sec_gstat & SEC_GSTAT_ERR) {
 380
 381                 switch (sec_gstat & SEC_GSTAT_ERRC) {
 382                 case 0:
 383                         handle_sec_sfi_fault(sec_gstat);
 384                         break;
 385                 case SEC_GSTAT_SCIERR:
 386                         handle_sec_sci_fault(sec_gstat);
 387                         break;
 388                 case SEC_GSTAT_SSIERR:
 389                         handle_sec_ssi_fault(sec_gstat);
 390                         break;
 391                 }
 392
 393
 394         }
 395
 396         raw_spin_unlock(&desc->lock);
 397 }
 398
 399 #endif
 400
 401 #ifdef CONFIG_SMP
 402 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 403 {
 404         bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
 405 }
 406
 407 static int bfin_internal_set_affinity(struct irq_data *d,
 408                                       const struct cpumask *mask, bool force)
 409 {
 410         bfin_internal_mask_irq(d->irq);
 411         bfin_internal_unmask_irq_affinity(d->irq, mask);
 412
 413         return 0;
 414 }
 415 #else
 416 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 417 {
 418         bfin_internal_unmask_irq(d->irq);
 419 }
 420 #endif
 421
 422 #if defined(CONFIG_PM) && !defined(CONFIG_BF60x)
 423 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 424 {
 425         u32 bank, bit, wakeup = 0;
 426         unsigned long flags;
 427         bank = SIC_SYSIRQ(irq) / 32;
 428         bit = SIC_SYSIRQ(irq) % 32;
 429
 430         switch (irq) {
 431 #ifdef IRQ_RTC
 432         case IRQ_RTC:
 433         wakeup |= WAKE;
 434         break;
 435 #endif
 436 #ifdef IRQ_CAN0_RX
 437         case IRQ_CAN0_RX:
 438         wakeup |= CANWE;
 439         break;
 440 #endif
 441 #ifdef IRQ_CAN1_RX
 442         case IRQ_CAN1_RX:
 443         wakeup |= CANWE;
 444         break;
 445 #endif
 446 #ifdef IRQ_USB_INT0
 447         case IRQ_USB_INT0:
 448         wakeup |= USBWE;
 449         break;
 450 #endif
 451 #ifdef CONFIG_BF54x
 452         case IRQ_CNT:
 453         wakeup |= ROTWE;
 454         break;
 455 #endif
 456         default:
 457         break;
 458         }
 459
 460         flags = hard_local_irq_save();
 461
 462         if (state) {
 463                 bfin_sic_iwr[bank] |= (1 << bit);
 464                 vr_wakeup  |= wakeup;
 465
 466         } else {
 467                 bfin_sic_iwr[bank] &= ~(1 << bit);
 468                 vr_wakeup  &= ~wakeup;
 469         }
 470
 471         hard_local_irq_restore(flags);
 472
 473         return 0;
 474 }
 475
 476 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
 477 {
 478         return bfin_internal_set_wake(d->irq, state);
 479 }
 480 #else
 481 inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 482 {
 483         return 0;
 484 }
 485 # define bfin_internal_set_wake_chip NULL
 486 #endif
 487
 488 static struct irq_chip bfin_core_irqchip = {
 489         .name = "CORE",
 490         .irq_mask = bfin_core_mask_irq,
 491         .irq_unmask = bfin_core_unmask_irq,
 492 };
 493
 494 static struct irq_chip bfin_internal_irqchip = {
 495         .name = "INTN",
 496         .irq_mask = bfin_internal_mask_irq_chip,
 497         .irq_unmask = bfin_internal_unmask_irq_chip,
 498         .irq_disable = bfin_internal_mask_irq_chip,
 499         .irq_enable = bfin_internal_unmask_irq_chip,
 500 #ifdef CONFIG_SMP
 501         .irq_set_affinity = bfin_internal_set_affinity,
 502 #endif
 503         .irq_set_wake = bfin_internal_set_wake_chip,
 504 };
 505
 506 #ifdef CONFIG_BF60x
 507 static struct irq_chip bfin_sec_irqchip = {
 508         .name = "SEC",
 509         .irq_mask_ack = bfin_sec_mask_ack_irq,
 510         .irq_mask = bfin_sec_mask_ack_irq,
 511         .irq_unmask = bfin_sec_unmask_irq,
 512         .irq_eoi = bfin_sec_unmask_irq,
 513         .irq_disable = bfin_sec_disable,
 514         .irq_enable = bfin_sec_enable,
 515         .irq_set_wake = bfin_internal_set_wake,
 516 };
 517 #endif
 518
 519 void bfin_handle_irq(unsigned irq)
 520 {
 521 #ifdef CONFIG_IPIPE
 522         struct pt_regs regs;    /* Contents not used. */
 523         ipipe_trace_irq_entry(irq);
 524         __ipipe_handle_irq(irq, &regs);
 525         ipipe_trace_irq_exit(irq);
 526 #else /* !CONFIG_IPIPE */
 527         generic_handle_irq(irq);
 528 #endif  /* !CONFIG_IPIPE */
 529 }
 530
 531 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 532 static int mac_stat_int_mask;
 533
 534 static void bfin_mac_status_ack_irq(unsigned int irq)
 535 {
 536         switch (irq) {
 537         case IRQ_MAC_MMCINT:
 538                 bfin_write_EMAC_MMC_TIRQS(
 539                         bfin_read_EMAC_MMC_TIRQE() &
 540                         bfin_read_EMAC_MMC_TIRQS());
 541                 bfin_write_EMAC_MMC_RIRQS(
 542                         bfin_read_EMAC_MMC_RIRQE() &
 543                         bfin_read_EMAC_MMC_RIRQS());
 544                 break;
 545         case IRQ_MAC_RXFSINT:
 546                 bfin_write_EMAC_RX_STKY(
 547                         bfin_read_EMAC_RX_IRQE() &
 548                         bfin_read_EMAC_RX_STKY());
 549                 break;
 550         case IRQ_MAC_TXFSINT:
 551                 bfin_write_EMAC_TX_STKY(
 552                         bfin_read_EMAC_TX_IRQE() &
 553                         bfin_read_EMAC_TX_STKY());
 554                 break;
 555         case IRQ_MAC_WAKEDET:
 556                  bfin_write_EMAC_WKUP_CTL(
 557                         bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
 558                 break;
 559         default:
 560                 /* These bits are W1C */
 561                 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
 562                 break;
 563         }
 564 }
 565
 566 static void bfin_mac_status_mask_irq(struct irq_data *d)
 567 {
 568         unsigned int irq = d->irq;
 569
 570         mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
 571 #ifdef BF537_FAMILY
 572         switch (irq) {
 573         case IRQ_MAC_PHYINT:
 574                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
 575                 break;
 576         default:
 577                 break;
 578         }
 579 #else
 580         if (!mac_stat_int_mask)
 581                 bfin_internal_mask_irq(IRQ_MAC_ERROR);
 582 #endif
 583         bfin_mac_status_ack_irq(irq);
 584 }
 585
 586 static void bfin_mac_status_unmask_irq(struct irq_data *d)
 587 {
 588         unsigned int irq = d->irq;
 589
 590 #ifdef BF537_FAMILY
 591         switch (irq) {
 592         case IRQ_MAC_PHYINT:
 593                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
 594                 break;
 595         default:
 596                 break;
 597         }
 598 #else
 599         if (!mac_stat_int_mask)
 600                 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
 601 #endif
 602         mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
 603 }
 604
 605 #ifdef CONFIG_PM
 606 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
 607 {
 608 #ifdef BF537_FAMILY
 609         return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
 610 #else
 611         return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
 612 #endif
 613 }
 614 #else
 615 # define bfin_mac_status_set_wake NULL
 616 #endif
 617
 618 static struct irq_chip bfin_mac_status_irqchip = {
 619         .name = "MACST",
 620         .irq_mask = bfin_mac_status_mask_irq,
 621         .irq_unmask = bfin_mac_status_unmask_irq,
 622         .irq_set_wake = bfin_mac_status_set_wake,
 623 };
 624
 625 void bfin_demux_mac_status_irq(unsigned int int_err_irq,
 626                                struct irq_desc *inta_desc)
 627 {
 628         int i, irq = 0;
 629         u32 status = bfin_read_EMAC_SYSTAT();
 630
 631         for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
 632                 if (status & (1L << i)) {
 633                         irq = IRQ_MAC_PHYINT + i;
 634                         break;
 635                 }
 636
 637         if (irq) {
 638                 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
 639                         bfin_handle_irq(irq);
 640                 } else {
 641                         bfin_mac_status_ack_irq(irq);
 642                         pr_debug("IRQ %d:"
 643                                         " MASKED MAC ERROR INTERRUPT ASSERTED\n",
 644                                         irq);
 645                 }
 646         } else
 647                 printk(KERN_ERR
 648                                 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
 649                                 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
 650                                 "(EMAC_SYSTAT=0x%X)\n",
 651                                 __func__, __FILE__, __LINE__, status);
 652 }
 653 #endif
 654
 655 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 656 {
 657 #ifdef CONFIG_IPIPE
 658         handle = handle_level_irq;
 659 #endif
 660         __irq_set_handler_locked(irq, handle);
 661 }
 662
 663 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 664 extern void bfin_gpio_irq_prepare(unsigned gpio);
 665
 666 #if !BFIN_GPIO_PINT
 667
 668 static void bfin_gpio_ack_irq(struct irq_data *d)
 669 {
 670         /* AFAIK ack_irq in case mask_ack is provided
 671          * get's only called for edge sense irqs
 672          */
 673         set_gpio_data(irq_to_gpio(d->irq), 0);
 674 }
 675
 676 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
 677 {
 678         unsigned int irq = d->irq;
 679         u32 gpionr = irq_to_gpio(irq);
 680
 681         if (!irqd_is_level_type(d))
 682                 set_gpio_data(gpionr, 0);
 683
 684         set_gpio_maska(gpionr, 0);
 685 }
 686
 687 static void bfin_gpio_mask_irq(struct irq_data *d)
 688 {
 689         set_gpio_maska(irq_to_gpio(d->irq), 0);
 690 }
 691
 692 static void bfin_gpio_unmask_irq(struct irq_data *d)
 693 {
 694         set_gpio_maska(irq_to_gpio(d->irq), 1);
 695 }
 696
 697 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
 698 {
 699         u32 gpionr = irq_to_gpio(d->irq);
 700
 701         if (__test_and_set_bit(gpionr, gpio_enabled))
 702                 bfin_gpio_irq_prepare(gpionr);
 703
 704         bfin_gpio_unmask_irq(d);
 705
 706         return 0;
 707 }
 708
 709 static void bfin_gpio_irq_shutdown(struct irq_data *d)
 710 {
 711         u32 gpionr = irq_to_gpio(d->irq);
 712
 713         bfin_gpio_mask_irq(d);
 714         __clear_bit(gpionr, gpio_enabled);
 715         bfin_gpio_irq_free(gpionr);
 716 }
 717
 718 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
 719 {
 720         unsigned int irq = d->irq;
 721         int ret;
 722         char buf[16];
 723         u32 gpionr = irq_to_gpio(irq);
 724
 725         if (type == IRQ_TYPE_PROBE) {
 726                 /* only probe unenabled GPIO interrupt lines */
 727                 if (test_bit(gpionr, gpio_enabled))
 728                         return 0;
 729                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 730         }
 731
 732         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 733                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 734
 735                 snprintf(buf, 16, "gpio-irq%d", irq);
 736                 ret = bfin_gpio_irq_request(gpionr, buf);
 737                 if (ret)
 738                         return ret;
 739
 740                 if (__test_and_set_bit(gpionr, gpio_enabled))
 741                         bfin_gpio_irq_prepare(gpionr);
 742
 743         } else {
 744                 __clear_bit(gpionr, gpio_enabled);
 745                 return 0;
 746         }
 747
 748         set_gpio_inen(gpionr, 0);
 749         set_gpio_dir(gpionr, 0);
 750
 751         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 752             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 753                 set_gpio_both(gpionr, 1);
 754         else
 755                 set_gpio_both(gpionr, 0);
 756
 757         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 758                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 759         else
 760                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 761
 762         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 763                 set_gpio_edge(gpionr, 1);
 764                 set_gpio_inen(gpionr, 1);
 765                 set_gpio_data(gpionr, 0);
 766
 767         } else {
 768                 set_gpio_edge(gpionr, 0);
 769                 set_gpio_inen(gpionr, 1);
 770         }
 771
 772         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 773                 bfin_set_irq_handler(irq, handle_edge_irq);
 774         else
 775                 bfin_set_irq_handler(irq, handle_level_irq);
 776
 777         return 0;
 778 }
 779
 780 #ifdef CONFIG_PM
 781 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 782 {
 783         return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
 784 }
 785 #else
 786 # define bfin_gpio_set_wake NULL
 787 #endif
 788
 789 static void bfin_demux_gpio_block(unsigned int irq)
 790 {
 791         unsigned int gpio, mask;
 792
 793         gpio = irq_to_gpio(irq);
 794         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 795
 796         while (mask) {
 797                 if (mask & 1)
 798                         bfin_handle_irq(irq);
 799                 irq++;
 800                 mask >>= 1;
 801         }
 802 }
 803
 804 void bfin_demux_gpio_irq(unsigned int inta_irq,
 805                         struct irq_desc *desc)
 806 {
 807         unsigned int irq;
 808
 809         switch (inta_irq) {
 810 #if defined(BF537_FAMILY)
 811         case IRQ_PF_INTA_PG_INTA:
 812                 bfin_demux_gpio_block(IRQ_PF0);
 813                 irq = IRQ_PG0;
 814                 break;
 815         case IRQ_PH_INTA_MAC_RX:
 816                 irq = IRQ_PH0;
 817                 break;
 818 #elif defined(BF533_FAMILY)
 819         case IRQ_PROG_INTA:
 820                 irq = IRQ_PF0;
 821                 break;
 822 #elif defined(BF538_FAMILY)
 823         case IRQ_PORTF_INTA:
 824                 irq = IRQ_PF0;
 825                 break;
 826 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 827         case IRQ_PORTF_INTA:
 828                 irq = IRQ_PF0;
 829                 break;
 830         case IRQ_PORTG_INTA:
 831                 irq = IRQ_PG0;
 832                 break;
 833         case IRQ_PORTH_INTA:
 834                 irq = IRQ_PH0;
 835                 break;
 836 #elif defined(CONFIG_BF561)
 837         case IRQ_PROG0_INTA:
 838                 irq = IRQ_PF0;
 839                 break;
 840         case IRQ_PROG1_INTA:
 841                 irq = IRQ_PF16;
 842                 break;
 843         case IRQ_PROG2_INTA:
 844                 irq = IRQ_PF32;
 845                 break;
 846 #endif
 847         default:
 848                 BUG();
 849                 return;
 850         }
 851
 852         bfin_demux_gpio_block(irq);
 853 }
 854
 855 #else
 856
 857 # ifndef CONFIG_BF60x
 858 #define NR_PINT_SYS_IRQS        4
 859 #define NR_PINTS                160
 860 # else
 861 #define NR_PINT_SYS_IRQS        6
 862 #define NR_PINTS                112
 863 #endif
 864
 865 #define NR_PINT_BITS            32
 866 #define IRQ_NOT_AVAIL           0xFF
 867
 868 #define PINT_2_BANK(x)          ((x) >> 5)
 869 #define PINT_2_BIT(x)           ((x) & 0x1F)
 870 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 871
 872 static unsigned char irq2pint_lut[NR_PINTS];
 873 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 874
 875 static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
 876         (struct bfin_pint_regs *)PINT0_MASK_SET,
 877         (struct bfin_pint_regs *)PINT1_MASK_SET,
 878         (struct bfin_pint_regs *)PINT2_MASK_SET,
 879         (struct bfin_pint_regs *)PINT3_MASK_SET,
 880 #ifdef CONFIG_BF60x
 881         (struct bfin_pint_regs *)PINT4_MASK_SET,
 882         (struct bfin_pint_regs *)PINT5_MASK_SET,
 883 #endif
 884 };
 885
 886 #ifndef CONFIG_BF60x
 887 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 888 {
 889         unsigned int irq_base;
 890
 891         if (bank < 2) {         /*PA-PB */
 892                 irq_base = IRQ_PA0 + bmap * 16;
 893         } else {                /*PC-PJ */
 894                 irq_base = IRQ_PC0 + bmap * 16;
 895         }
 896
 897         return irq_base;
 898 }
 899 #else
 900 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 901 {
 902         unsigned int irq_base;
 903
 904         irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
 905
 906         return irq_base;
 907 }
 908 #endif
 909
 910         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 911 void init_pint_lut(void)
 912 {
 913         u16 bank, bit, irq_base, bit_pos;
 914         u32 pint_assign;
 915         u8 bmap;
 916
 917         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 918
 919         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 920
 921                 pint_assign = pint[bank]->assign;
 922
 923                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 924
 925                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 926
 927                         irq_base = get_irq_base(bank, bmap);
 928
 929                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 930                         bit_pos = bit + bank * NR_PINT_BITS;
 931
 932                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 933                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 934                 }
 935         }
 936 }
 937
 938 static void bfin_gpio_ack_irq(struct irq_data *d)
 939 {
 940         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 941         u32 pintbit = PINT_BIT(pint_val);
 942         u32 bank = PINT_2_BANK(pint_val);
 943
 944         if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
 945                 if (pint[bank]->invert_set & pintbit)
 946                         pint[bank]->invert_clear = pintbit;
 947                 else
 948                         pint[bank]->invert_set = pintbit;
 949         }
 950         pint[bank]->request = pintbit;
 951
 952 }
 953
 954 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
 955 {
 956         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 957         u32 pintbit = PINT_BIT(pint_val);
 958         u32 bank = PINT_2_BANK(pint_val);
 959
 960         if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
 961                 if (pint[bank]->invert_set & pintbit)
 962                         pint[bank]->invert_clear = pintbit;
 963                 else
 964                         pint[bank]->invert_set = pintbit;
 965         }
 966
 967         pint[bank]->request = pintbit;
 968         pint[bank]->mask_clear = pintbit;
 969 }
 970
 971 static void bfin_gpio_mask_irq(struct irq_data *d)
 972 {
 973         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 974
 975         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 976 }
 977
 978 static void bfin_gpio_unmask_irq(struct irq_data *d)
 979 {
 980         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 981         u32 pintbit = PINT_BIT(pint_val);
 982         u32 bank = PINT_2_BANK(pint_val);
 983
 984         pint[bank]->mask_set = pintbit;
 985 }
 986
 987 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
 988 {
 989         unsigned int irq = d->irq;
 990         u32 gpionr = irq_to_gpio(irq);
 991         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 992
 993         if (pint_val == IRQ_NOT_AVAIL) {
 994                 printk(KERN_ERR
 995                 "GPIO IRQ %d :Not in PINT Assign table "
 996                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 997                 return -ENODEV;
 998         }
 999
1000         if (__test_and_set_bit(gpionr, gpio_enabled))
1001                 bfin_gpio_irq_prepare(gpionr);
1002
1003         bfin_gpio_unmask_irq(d);
1004
1005         return 0;
1006 }
1007
1008 static void bfin_gpio_irq_shutdown(struct irq_data *d)
1009 {
1010         u32 gpionr = irq_to_gpio(d->irq);
1011
1012         bfin_gpio_mask_irq(d);
1013         __clear_bit(gpionr, gpio_enabled);
1014         bfin_gpio_irq_free(gpionr);
1015 }
1016
1017 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
1018 {
1019         unsigned int irq = d->irq;
1020         int ret;
1021         char buf[16];
1022         u32 gpionr = irq_to_gpio(irq);
1023         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1024         u32 pintbit = PINT_BIT(pint_val);
1025         u32 bank = PINT_2_BANK(pint_val);
1026
1027         if (pint_val == IRQ_NOT_AVAIL)
1028                 return -ENODEV;
1029
1030         if (type == IRQ_TYPE_PROBE) {
1031                 /* only probe unenabled GPIO interrupt lines */
1032                 if (test_bit(gpionr, gpio_enabled))
1033                         return 0;
1034                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1035         }
1036
1037         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
1038                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1039
1040                 snprintf(buf, 16, "gpio-irq%d", irq);
1041                 ret = bfin_gpio_irq_request(gpionr, buf);
1042                 if (ret)
1043                         return ret;
1044
1045                 if (__test_and_set_bit(gpionr, gpio_enabled))
1046                         bfin_gpio_irq_prepare(gpionr);
1047
1048         } else {
1049                 __clear_bit(gpionr, gpio_enabled);
1050                 return 0;
1051         }
1052
1053         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
1054                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
1055         else
1056                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
1057
1058         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
1059             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1060                 if (gpio_get_value(gpionr))
1061                         pint[bank]->invert_set = pintbit;
1062                 else
1063                         pint[bank]->invert_clear = pintbit;
1064         }
1065
1066         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1067                 pint[bank]->edge_set = pintbit;
1068                 bfin_set_irq_handler(irq, handle_edge_irq);
1069         } else {
1070                 pint[bank]->edge_clear = pintbit;
1071                 bfin_set_irq_handler(irq, handle_level_irq);
1072         }
1073
1074         return 0;
1075 }
1076
1077 #ifdef CONFIG_PM
1078 static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS];
1079 static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
1080
1081 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
1082 {
1083         u32 pint_irq;
1084         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1085         u32 bank = PINT_2_BANK(pint_val);
1086
1087         switch (bank) {
1088         case 0:
1089                 pint_irq = IRQ_PINT0;
1090                 break;
1091         case 2:
1092                 pint_irq = IRQ_PINT2;
1093                 break;
1094         case 3:
1095                 pint_irq = IRQ_PINT3;
1096                 break;
1097         case 1:
1098                 pint_irq = IRQ_PINT1;
1099                 break;
1100 #ifdef CONFIG_BF60x
1101         case 4:
1102                 pint_irq = IRQ_PINT4;
1103                 break;
1104         case 5:
1105                 pint_irq = IRQ_PINT5;
1106                 break;
1107 #endif
1108         default:
1109                 return -EINVAL;
1110         }
1111
1112         bfin_internal_set_wake(pint_irq, state);
1113
1114         return 0;
1115 }
1116
1117 void bfin_pint_suspend(void)
1118 {
1119         u32 bank;
1120
1121         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
1122                 save_pint_reg[bank].mask_set = pint[bank]->mask_set;
1123                 save_pint_reg[bank].assign = pint[bank]->assign;
1124                 save_pint_reg[bank].edge_set = pint[bank]->edge_set;
1125                 save_pint_reg[bank].invert_set = pint[bank]->invert_set;
1126         }
1127 }
1128
1129 void bfin_pint_resume(void)
1130 {
1131         u32 bank;
1132
1133         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
1134                 pint[bank]->mask_set = save_pint_reg[bank].mask_set;
1135                 pint[bank]->assign = save_pint_reg[bank].assign;
1136                 pint[bank]->edge_set = save_pint_reg[bank].edge_set;
1137                 pint[bank]->invert_set = save_pint_reg[bank].invert_set;
1138         }
1139 }
1140
1141 #ifdef CONFIG_BF60x
1142 static int sec_suspend(void)
1143 {
1144         u32 bank;
1145
1146         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
1147                 save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0));
1148         return 0;
1149 }
1150
1151 static void sec_resume(void)
1152 {
1153         u32 bank;
1154
1155         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1156         udelay(100);
1157         bfin_write_SEC_GCTL(SEC_GCTL_EN);
1158         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1159
1160         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
1161                 bfin_write_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
1162 }
1163
1164 static struct syscore_ops sec_pm_syscore_ops = {
1165         .suspend = sec_suspend,
1166         .resume = sec_resume,
1167 };
1168 #endif
1169 #else
1170 # define bfin_gpio_set_wake NULL
1171 #endif
1172
1173 void bfin_demux_gpio_irq(unsigned int inta_irq,
1174                         struct irq_desc *desc)
1175 {
1176         u32 bank, pint_val;
1177         u32 request, irq;
1178         u32 level_mask;
1179         int umask = 0;
1180         struct irq_chip *chip = irq_desc_get_chip(desc);
1181
1182         if (chip->irq_mask_ack) {
1183                 chip->irq_mask_ack(&desc->irq_data);
1184         } else {
1185                 chip->irq_mask(&desc->irq_data);
1186                 if (chip->irq_ack)
1187                         chip->irq_ack(&desc->irq_data);
1188         }
1189
1190         switch (inta_irq) {
1191         case IRQ_PINT0:
1192                 bank = 0;
1193                 break;
1194         case IRQ_PINT2:
1195                 bank = 2;
1196                 break;
1197         case IRQ_PINT3:
1198                 bank = 3;
1199                 break;
1200         case IRQ_PINT1:
1201                 bank = 1;
1202                 break;
1203 #ifdef CONFIG_BF60x
1204         case IRQ_PINT4:
1205                 bank = 4;
1206                 break;
1207         case IRQ_PINT5:
1208                 bank = 5;
1209                 break;
1210 #endif
1211         default:
1212                 return;
1213         }
1214
1215         pint_val = bank * NR_PINT_BITS;
1216
1217         request = pint[bank]->request;
1218
1219         level_mask = pint[bank]->edge_set & request;
1220
1221         while (request) {
1222                 if (request & 1) {
1223                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
1224                         if (level_mask & PINT_BIT(pint_val)) {
1225                                 umask = 1;
1226                                 chip->irq_unmask(&desc->irq_data);
1227                         }
1228                         bfin_handle_irq(irq);
1229                 }
1230                 pint_val++;
1231                 request >>= 1;
1232         }
1233
1234         if (!umask)
1235                 chip->irq_unmask(&desc->irq_data);
1236 }
1237 #endif
1238
1239 static struct irq_chip bfin_gpio_irqchip = {
1240         .name = "GPIO",
1241         .irq_ack = bfin_gpio_ack_irq,
1242         .irq_mask = bfin_gpio_mask_irq,
1243         .irq_mask_ack = bfin_gpio_mask_ack_irq,
1244         .irq_unmask = bfin_gpio_unmask_irq,
1245         .irq_disable = bfin_gpio_mask_irq,
1246         .irq_enable = bfin_gpio_unmask_irq,
1247         .irq_set_type = bfin_gpio_irq_type,
1248         .irq_startup = bfin_gpio_irq_startup,
1249         .irq_shutdown = bfin_gpio_irq_shutdown,
1250         .irq_set_wake = bfin_gpio_set_wake,
1251 };
1252
1253 void __cpuinit init_exception_vectors(void)
1254 {
1255         /* cannot program in software:
1256          * evt0 - emulation (jtag)
1257          * evt1 - reset
1258          */
1259         bfin_write_EVT2(evt_nmi);
1260         bfin_write_EVT3(trap);
1261         bfin_write_EVT5(evt_ivhw);
1262         bfin_write_EVT6(evt_timer);
1263         bfin_write_EVT7(evt_evt7);
1264         bfin_write_EVT8(evt_evt8);
1265         bfin_write_EVT9(evt_evt9);
1266         bfin_write_EVT10(evt_evt10);
1267         bfin_write_EVT11(evt_evt11);
1268         bfin_write_EVT12(evt_evt12);
1269         bfin_write_EVT13(evt_evt13);
1270         bfin_write_EVT14(evt_evt14);
1271         bfin_write_EVT15(evt_system_call);
1272         CSYNC();
1273 }
1274
1275 /*
1276  * This function should be called during kernel startup to initialize
1277  * the BFin IRQ handling routines.
1278  */
1279
1280 int __init init_arch_irq(void)
1281 {
1282         int irq;
1283         unsigned long ilat = 0;
1284
1285 #ifndef CONFIG_BF60x
1286         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
1287 #ifdef SIC_IMASK0
1288         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1289         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1290 # ifdef SIC_IMASK2
1291         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1292 # endif
1293 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1294         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1295         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1296 # endif
1297 #else
1298         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1299 #endif
1300 #else /* CONFIG_BF60x */
1301         bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1302 #endif
1303
1304         local_irq_disable();
1305
1306 #if BFIN_GPIO_PINT
1307 # ifdef CONFIG_PINTx_REASSIGN
1308         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1309         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1310         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1311         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1312 # ifdef CONFIG_BF60x
1313         pint[4]->assign = CONFIG_PINT4_ASSIGN;
1314         pint[5]->assign = CONFIG_PINT5_ASSIGN;
1315 # endif
1316 # endif
1317         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1318         init_pint_lut();
1319 #endif
1320
1321         for (irq = 0; irq <= SYS_IRQS; irq++) {
1322                 if (irq <= IRQ_CORETMR)
1323                         irq_set_chip(irq, &bfin_core_irqchip);
1324                 else
1325                         irq_set_chip(irq, &bfin_internal_irqchip);
1326
1327                 switch (irq) {
1328 #ifndef CONFIG_BF60x
1329 #if BFIN_GPIO_PINT
1330                 case IRQ_PINT0:
1331                 case IRQ_PINT1:
1332                 case IRQ_PINT2:
1333                 case IRQ_PINT3:
1334 #elif defined(BF537_FAMILY)
1335                 case IRQ_PH_INTA_MAC_RX:
1336                 case IRQ_PF_INTA_PG_INTA:
1337 #elif defined(BF533_FAMILY)
1338                 case IRQ_PROG_INTA:
1339 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1340                 case IRQ_PORTF_INTA:
1341                 case IRQ_PORTG_INTA:
1342                 case IRQ_PORTH_INTA:
1343 #elif defined(CONFIG_BF561)
1344                 case IRQ_PROG0_INTA:
1345                 case IRQ_PROG1_INTA:
1346                 case IRQ_PROG2_INTA:
1347 #elif defined(BF538_FAMILY)
1348                 case IRQ_PORTF_INTA:
1349 #endif
1350                         irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1351                         break;
1352 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1353                 case IRQ_MAC_ERROR:
1354                         irq_set_chained_handler(irq,
1355                                                 bfin_demux_mac_status_irq);
1356                         break;
1357 #endif
1358 #if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1359                 case IRQ_SUPPLE_0:
1360                 case IRQ_SUPPLE_1:
1361                         irq_set_handler(irq, handle_percpu_irq);
1362                         break;
1363 #endif
1364 #endif
1365
1366 #ifdef CONFIG_TICKSOURCE_CORETMR
1367                 case IRQ_CORETMR:
1368 # ifdef CONFIG_SMP
1369                         irq_set_handler(irq, handle_percpu_irq);
1370 # else
1371                         irq_set_handler(irq, handle_simple_irq);
1372 # endif
1373                         break;
1374 #endif
1375
1376 #ifdef CONFIG_TICKSOURCE_GPTMR0
1377                 case IRQ_TIMER0:
1378                         irq_set_handler(irq, handle_simple_irq);
1379                         break;
1380 #endif
1381
1382                 default:
1383 #ifdef CONFIG_IPIPE
1384                         irq_set_handler(irq, handle_level_irq);
1385 #else
1386                         irq_set_handler(irq, handle_simple_irq);
1387 #endif
1388                         break;
1389                 }
1390         }
1391
1392         init_mach_irq();
1393
1394 #ifndef CONFIG_BF60x
1395 #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) && !defined(CONFIG_BF60x)
1396         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1397                 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1398                                          handle_level_irq);
1399 #endif
1400         /* if configured as edge, then will be changed to do_edge_IRQ */
1401         for (irq = GPIO_IRQ_BASE;
1402                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1403                 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1404                                          handle_level_irq);
1405 #else
1406         for (irq = BFIN_IRQ(0); irq <= SYS_IRQS; irq++) {
1407                 if (irq < CORE_IRQS && irq != IRQ_CGU_EVT) {
1408                         irq_set_chip(irq, &bfin_sec_irqchip);
1409                         __irq_set_handler(irq, handle_sec_fault, 0, NULL);
1410                 } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
1411                         irq_set_chip(irq, &bfin_sec_irqchip);
1412                         irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1413                 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
1414                         irq_set_chip(irq, &bfin_sec_irqchip);
1415                         irq_set_handler(irq, handle_percpu_irq);
1416                 } else {
1417                         irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1418                                         handle_fasteoi_irq);
1419                         __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1420                 }
1421         }
1422         for (irq = GPIO_IRQ_BASE;
1423                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1424                 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1425                                         handle_level_irq);
1426 #endif
1427         bfin_write_IMASK(0);
1428         CSYNC();
1429         ilat = bfin_read_ILAT();
1430         CSYNC();
1431         bfin_write_ILAT(ilat);
1432         CSYNC();
1433
1434         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1435         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1436          * local_irq_enable()
1437          */
1438 #ifndef CONFIG_BF60x
1439         program_IAR();
1440         /* Therefore it's better to setup IARs before interrupts enabled */
1441         search_IAR();
1442
1443         /* Enable interrupts IVG7-15 */
1444         bfin_irq_flags |= IMASK_IVG15 |
1445                 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1446                 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1447
1448         bfin_sti(bfin_irq_flags);
1449
1450         /* This implicitly covers ANOMALY_05000171
1451          * Boot-ROM code modifies SICA_IWRx wakeup registers
1452          */
1453 #ifdef SIC_IWR0
1454         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1455 # ifdef SIC_IWR1
1456         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1457          * will screw up the bootrom as it relies on MDMA0/1 waking it
1458          * up from IDLE instructions.  See this report for more info:
1459          * http://blackfin.uclinux.org/gf/tracker/4323
1460          */
1461         if (ANOMALY_05000435)
1462                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1463         else
1464                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1465 # endif
1466 # ifdef SIC_IWR2
1467         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1468 # endif
1469 #else
1470         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1471 #endif
1472 #else  /* CONFIG_BF60x */
1473         /* Enable interrupts IVG7-15 */
1474         bfin_irq_flags |= IMASK_IVG15 |
1475             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1476             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1477
1478
1479         bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
1480         bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
1481         bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
1482         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1483         udelay(100);
1484         bfin_write_SEC_GCTL(SEC_GCTL_EN);
1485         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1486         init_software_driven_irq();
1487         register_syscore_ops(&sec_pm_syscore_ops);
1488 #endif
1489         return 0;
1490 }
1491
1492 #ifdef CONFIG_DO_IRQ_L1
1493 __attribute__((l1_text))
1494 #endif
1495 static int vec_to_irq(int vec)
1496 {
1497 #ifndef CONFIG_BF60x
1498         struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1499         struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1500         unsigned long sic_status[3];
1501 #endif
1502         if (likely(vec == EVT_IVTMR_P))
1503                 return IRQ_CORETMR;
1504 #ifndef CONFIG_BF60x
1505 #ifdef SIC_ISR
1506         sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1507 #else
1508         if (smp_processor_id()) {
1509 # ifdef SICB_ISR0
1510                 /* This will be optimized out in UP mode. */
1511                 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1512                 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1513 # endif
1514         } else {
1515                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1516                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1517         }
1518 #endif
1519 #ifdef SIC_ISR2
1520         sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1521 #endif
1522
1523         for (;; ivg++) {
1524                 if (ivg >= ivg_stop)
1525                         return -1;
1526 #ifdef SIC_ISR
1527                 if (sic_status[0] & ivg->isrflag)
1528 #else
1529                 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1530 #endif
1531                         return ivg->irqno;
1532         }
1533 #else
1534         /* for bf60x read */
1535         return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1536 #endif  /* end of CONFIG_BF60x */
1537 }
1538
1539 #ifdef CONFIG_DO_IRQ_L1
1540 __attribute__((l1_text))
1541 #endif
1542 void do_irq(int vec, struct pt_regs *fp)
1543 {
1544         int irq = vec_to_irq(vec);
1545         if (irq == -1)
1546                 return;
1547         asm_do_IRQ(irq, fp);
1548 }
1549
1550 #ifdef CONFIG_IPIPE
1551
1552 int __ipipe_get_irq_priority(unsigned irq)
1553 {
1554         int ient, prio;
1555
1556         if (irq <= IRQ_CORETMR)
1557                 return irq;
1558
1559         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1560                 struct ivgx *ivg = ivg_table + ient;
1561                 if (ivg->irqno == irq) {
1562                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1563                                 if (ivg7_13[prio].ifirst <= ivg &&
1564                                     ivg7_13[prio].istop > ivg)
1565                                         return IVG7 + prio;
1566                         }
1567                 }
1568         }
1569
1570         return IVG15;
1571 }
1572
1573 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1574 #ifdef CONFIG_DO_IRQ_L1
1575 __attribute__((l1_text))
1576 #endif
1577 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1578 {
1579         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1580         struct ipipe_domain *this_domain = __ipipe_current_domain;
1581         struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1582         struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1583         int irq, s = 0;
1584
1585         irq = vec_to_irq(vec);
1586         if (irq == -1)
1587                 return 0;
1588
1589         if (irq == IRQ_SYSTMR) {
1590 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1591                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1592 #endif
1593                 /* This is basically what we need from the register frame. */
1594                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1595                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1596                 if (this_domain != ipipe_root_domain)
1597                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1598                 else
1599                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1600         }
1601
1602         /*
1603          * We don't want Linux interrupt handlers to run at the
1604          * current core priority level (i.e. < EVT15), since this
1605          * might delay other interrupts handled by a high priority
1606          * domain. Here is what we do instead:
1607          *
1608          * - we raise the SYNCDEFER bit to prevent
1609          * __ipipe_handle_irq() to sync the pipeline for the root
1610          * stage for the incoming interrupt. Upon return, that IRQ is
1611          * pending in the interrupt log.
1612          *
1613          * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1614          * that _schedule_and_signal_from_int will eventually sync the
1615          * pipeline from EVT15.
1616          */
1617         if (this_domain == ipipe_root_domain) {
1618                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1619                 barrier();
1620         }
1621
1622         ipipe_trace_irq_entry(irq);
1623         __ipipe_handle_irq(irq, regs);
1624         ipipe_trace_irq_exit(irq);
1625
1626         if (user_mode(regs) &&
1627             !ipipe_test_foreign_stack() &&
1628             (current->ipipe_flags & PF_EVTRET) != 0) {
1629                 /*
1630                  * Testing for user_regs() does NOT fully eliminate
1631                  * foreign stack contexts, because of the forged
1632                  * interrupt returns we do through
1633                  * __ipipe_call_irqtail. In that case, we might have
1634                  * preempted a foreign stack context in a high
1635                  * priority domain, with a single interrupt level now
1636                  * pending after the irqtail unwinding is done. In
1637                  * which case user_mode() is now true, and the event
1638                  * gets dispatched spuriously.
1639                  */
1640                 current->ipipe_flags &= ~PF_EVTRET;
1641                 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1642         }
1643
1644         if (this_domain == ipipe_root_domain) {
1645                 set_thread_flag(TIF_IRQ_SYNC);
1646                 if (!s) {
1647                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1648                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1649                 }
1650         }
1651
1652         return 0;
1653 }
1654
1655 #endif /* CONFIG_IPIPE */