2 * Set up the interrupt priorities
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
11 * Licensed under the GPL-2
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
18 #include <linux/sched.h>
19 #include <linux/syscore_ops.h>
20 #include <asm/delay.h>
22 #include <linux/ipipe.h>
24 #include <asm/traps.h>
25 #include <asm/blackfin.h>
27 #include <asm/irq_handler.h>
29 #include <asm/traps.h>
33 * - we have separated the physical Hardware interrupt from the
34 * levels that the LINUX kernel sees (see the description in irq.h)
39 /* Initialize this to an actual value to force it into the .data
40 * section so that we know it is properly initialized at entry into
41 * the kernel but before bss is initialized to zero (which is where
42 * it would live otherwise). The 0x1f magic represents the IRQs we
43 * cannot actually mask out in hardware.
45 unsigned long bfin_irq_flags = 0x1f;
46 EXPORT_SYMBOL(bfin_irq_flags);
50 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
56 /* irq number for request_irq, available in mach-bf5xx/irq.h */
58 /* corresponding bit in the SIC_ISR register */
60 } ivg_table[NR_PERI_INTS];
62 static struct ivg_slice {
63 /* position of first irq in ivg_table for given ivg */
66 } ivg7_13[IVG13 - IVG7 + 1];
70 * Search SIC_IAR and fill tables with the irqvalues
71 * and their positions in the SIC_ISR register.
73 static void __init search_IAR(void)
75 unsigned ivg, irq_pos = 0;
76 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
79 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
81 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
84 bfin_read32((unsigned long *)SIC_IAR0 +
85 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
86 defined(CONFIG_BF538) || defined(CONFIG_BF539)
87 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
92 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
93 int iar_shift = (irqn & 7) * 4;
94 if (ivg == (0xf & (iar >> iar_shift))) {
95 ivg_table[irq_pos].irqno = IVG7 + irqn;
96 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
107 * This is for core internal IRQs
109 void bfin_ack_noop(struct irq_data *d)
111 /* Dummy function. */
114 static void bfin_core_mask_irq(struct irq_data *d)
116 bfin_irq_flags &= ~(1 << d->irq);
117 if (!hard_irqs_disabled())
118 hard_local_irq_enable();
121 static void bfin_core_unmask_irq(struct irq_data *d)
123 bfin_irq_flags |= 1 << d->irq;
125 * If interrupts are enabled, IMASK must contain the same value
126 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
127 * are currently disabled we need not do anything; one of the
128 * callers will take care of setting IMASK to the proper value
129 * when reenabling interrupts.
130 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
133 if (!hard_irqs_disabled())
134 hard_local_irq_enable();
139 void bfin_internal_mask_irq(unsigned int irq)
141 unsigned long flags = hard_local_irq_save();
143 unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
144 unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
145 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
147 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
148 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
152 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
153 ~(1 << BFIN_SYSIRQ(irq)));
154 #endif /* end of SIC_IMASK0 */
155 hard_local_irq_restore(flags);
158 static void bfin_internal_mask_irq_chip(struct irq_data *d)
160 bfin_internal_mask_irq(d->irq);
164 void bfin_internal_unmask_irq_affinity(unsigned int irq,
165 const struct cpumask *affinity)
167 void bfin_internal_unmask_irq(unsigned int irq)
170 unsigned long flags = hard_local_irq_save();
173 unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
174 unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
176 if (cpumask_test_cpu(0, affinity))
178 bfin_write_SIC_IMASK(mask_bank,
179 bfin_read_SIC_IMASK(mask_bank) |
182 if (cpumask_test_cpu(1, affinity))
183 bfin_write_SICB_IMASK(mask_bank,
184 bfin_read_SICB_IMASK(mask_bank) |
188 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
189 (1 << BFIN_SYSIRQ(irq)));
191 hard_local_irq_restore(flags);
195 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
197 bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
200 static int bfin_internal_set_affinity(struct irq_data *d,
201 const struct cpumask *mask, bool force)
203 bfin_internal_mask_irq(d->irq);
204 bfin_internal_unmask_irq_affinity(d->irq, mask);
209 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
211 bfin_internal_unmask_irq(d->irq);
215 #if defined(CONFIG_PM)
216 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
218 u32 bank, bit, wakeup = 0;
220 bank = BFIN_SYSIRQ(irq) / 32;
221 bit = BFIN_SYSIRQ(irq) % 32;
253 flags = hard_local_irq_save();
256 bfin_sic_iwr[bank] |= (1 << bit);
260 bfin_sic_iwr[bank] &= ~(1 << bit);
261 vr_wakeup &= ~wakeup;
264 hard_local_irq_restore(flags);
269 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
271 return bfin_internal_set_wake(d->irq, state);
274 inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
278 # define bfin_internal_set_wake_chip NULL
282 static void bfin_sec_preflow_handler(struct irq_data *d)
284 unsigned long flags = hard_local_irq_save();
285 unsigned int sid = BFIN_SYSIRQ(d->irq);
287 bfin_write_SEC_SCI(0, SEC_CSID, sid);
289 hard_local_irq_restore(flags);
292 static void bfin_sec_mask_ack_irq(struct irq_data *d)
294 unsigned long flags = hard_local_irq_save();
295 unsigned int sid = BFIN_SYSIRQ(d->irq);
297 bfin_write_SEC_SCI(0, SEC_CSID, sid);
299 hard_local_irq_restore(flags);
302 static void bfin_sec_unmask_irq(struct irq_data *d)
304 unsigned long flags = hard_local_irq_save();
305 unsigned int sid = BFIN_SYSIRQ(d->irq);
307 bfin_write32(SEC_END, sid);
309 hard_local_irq_restore(flags);
312 static void bfin_sec_enable_ssi(unsigned int sid)
314 unsigned long flags = hard_local_irq_save();
315 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
317 reg_sctl |= SEC_SCTL_SRC_EN;
318 bfin_write_SEC_SCTL(sid, reg_sctl);
320 hard_local_irq_restore(flags);
323 static void bfin_sec_disable_ssi(unsigned int sid)
325 unsigned long flags = hard_local_irq_save();
326 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
328 reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
329 bfin_write_SEC_SCTL(sid, reg_sctl);
331 hard_local_irq_restore(flags);
334 static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
336 unsigned long flags = hard_local_irq_save();
337 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
339 reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
340 bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
342 hard_local_irq_restore(flags);
345 static void bfin_sec_enable_sci(unsigned int sid)
347 unsigned long flags = hard_local_irq_save();
348 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
350 if (sid == BFIN_SYSIRQ(IRQ_WATCH0))
351 reg_sctl |= SEC_SCTL_FAULT_EN;
353 reg_sctl |= SEC_SCTL_INT_EN;
354 bfin_write_SEC_SCTL(sid, reg_sctl);
356 hard_local_irq_restore(flags);
359 static void bfin_sec_disable_sci(unsigned int sid)
361 unsigned long flags = hard_local_irq_save();
362 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
364 reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
365 bfin_write_SEC_SCTL(sid, reg_sctl);
367 hard_local_irq_restore(flags);
370 static void bfin_sec_enable(struct irq_data *d)
372 unsigned long flags = hard_local_irq_save();
373 unsigned int sid = BFIN_SYSIRQ(d->irq);
375 bfin_sec_enable_sci(sid);
376 bfin_sec_enable_ssi(sid);
378 hard_local_irq_restore(flags);
381 static void bfin_sec_disable(struct irq_data *d)
383 unsigned long flags = hard_local_irq_save();
384 unsigned int sid = BFIN_SYSIRQ(d->irq);
386 bfin_sec_disable_sci(sid);
387 bfin_sec_disable_ssi(sid);
389 hard_local_irq_restore(flags);
392 static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
394 unsigned long flags = hard_local_irq_save();
398 bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
400 for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
401 reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
402 reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
403 bfin_write_SEC_SCTL(i, reg_sctl);
406 hard_local_irq_restore(flags);
409 void bfin_sec_raise_irq(unsigned int irq)
411 unsigned long flags = hard_local_irq_save();
412 unsigned int sid = BFIN_SYSIRQ(irq);
414 bfin_write32(SEC_RAISE, sid);
416 hard_local_irq_restore(flags);
419 static void init_software_driven_irq(void)
421 bfin_sec_set_ssi_coreid(34, 0);
422 bfin_sec_set_ssi_coreid(35, 1);
424 bfin_sec_enable_sci(35);
425 bfin_sec_enable_ssi(35);
426 bfin_sec_set_ssi_coreid(36, 0);
427 bfin_sec_set_ssi_coreid(37, 1);
428 bfin_sec_enable_sci(37);
429 bfin_sec_enable_ssi(37);
432 void bfin_sec_resume(void)
434 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
436 bfin_write_SEC_GCTL(SEC_GCTL_EN);
437 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
440 void handle_sec_sfi_fault(uint32_t gstat)
445 void handle_sec_sci_fault(uint32_t gstat)
450 core_id = gstat & SEC_GSTAT_SCI;
451 cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
452 if (cstat & SEC_CSTAT_ERR) {
453 switch (cstat & SEC_CSTAT_ERRC) {
454 case SEC_CSTAT_ACKERR:
455 printk(KERN_DEBUG "sec ack err\n");
458 printk(KERN_DEBUG "sec sci unknow err\n");
464 void handle_sec_ssi_fault(uint32_t gstat)
469 sid = gstat & SEC_GSTAT_SID;
470 sstat = bfin_read_SEC_SSTAT(sid);
474 void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
478 raw_spin_lock(&desc->lock);
480 sec_gstat = bfin_read32(SEC_GSTAT);
481 if (sec_gstat & SEC_GSTAT_ERR) {
483 switch (sec_gstat & SEC_GSTAT_ERRC) {
485 handle_sec_sfi_fault(sec_gstat);
487 case SEC_GSTAT_SCIERR:
488 handle_sec_sci_fault(sec_gstat);
490 case SEC_GSTAT_SSIERR:
491 handle_sec_ssi_fault(sec_gstat);
498 raw_spin_unlock(&desc->lock);
500 handle_fasteoi_irq(irq, desc);
503 void handle_core_fault(unsigned int irq, struct irq_desc *desc)
505 struct pt_regs *fp = get_irq_regs();
507 raw_spin_lock(&desc->lock);
510 case IRQ_C0_DBL_FAULT:
514 dump_bfin_process(fp);
517 printk(KERN_NOTICE "Kernel Stack\n");
518 show_stack(current, NULL);
520 panic("Core 0 hardware error");
522 case IRQ_C0_NMI_L1_PARITY_ERR:
523 panic("Core 0 NMI L1 parity error");
526 panic("Core 1 fault %d occurs unexpectedly", irq);
529 raw_spin_unlock(&desc->lock);
531 #endif /* SEC_GCTL */
533 static struct irq_chip bfin_core_irqchip = {
535 .irq_mask = bfin_core_mask_irq,
536 .irq_unmask = bfin_core_unmask_irq,
540 static struct irq_chip bfin_internal_irqchip = {
542 .irq_mask = bfin_internal_mask_irq_chip,
543 .irq_unmask = bfin_internal_unmask_irq_chip,
544 .irq_disable = bfin_internal_mask_irq_chip,
545 .irq_enable = bfin_internal_unmask_irq_chip,
547 .irq_set_affinity = bfin_internal_set_affinity,
549 .irq_set_wake = bfin_internal_set_wake_chip,
552 static struct irq_chip bfin_sec_irqchip = {
554 .irq_mask_ack = bfin_sec_mask_ack_irq,
555 .irq_mask = bfin_sec_mask_ack_irq,
556 .irq_unmask = bfin_sec_unmask_irq,
557 .irq_eoi = bfin_sec_unmask_irq,
558 .irq_disable = bfin_sec_disable,
559 .irq_enable = bfin_sec_enable,
563 void bfin_handle_irq(unsigned irq)
566 struct pt_regs regs; /* Contents not used. */
567 ipipe_trace_irq_entry(irq);
568 __ipipe_handle_irq(irq, ®s);
569 ipipe_trace_irq_exit(irq);
570 #else /* !CONFIG_IPIPE */
571 generic_handle_irq(irq);
572 #endif /* !CONFIG_IPIPE */
575 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
576 static int mac_stat_int_mask;
578 static void bfin_mac_status_ack_irq(unsigned int irq)
582 bfin_write_EMAC_MMC_TIRQS(
583 bfin_read_EMAC_MMC_TIRQE() &
584 bfin_read_EMAC_MMC_TIRQS());
585 bfin_write_EMAC_MMC_RIRQS(
586 bfin_read_EMAC_MMC_RIRQE() &
587 bfin_read_EMAC_MMC_RIRQS());
589 case IRQ_MAC_RXFSINT:
590 bfin_write_EMAC_RX_STKY(
591 bfin_read_EMAC_RX_IRQE() &
592 bfin_read_EMAC_RX_STKY());
594 case IRQ_MAC_TXFSINT:
595 bfin_write_EMAC_TX_STKY(
596 bfin_read_EMAC_TX_IRQE() &
597 bfin_read_EMAC_TX_STKY());
599 case IRQ_MAC_WAKEDET:
600 bfin_write_EMAC_WKUP_CTL(
601 bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
604 /* These bits are W1C */
605 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
610 static void bfin_mac_status_mask_irq(struct irq_data *d)
612 unsigned int irq = d->irq;
614 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
618 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
624 if (!mac_stat_int_mask)
625 bfin_internal_mask_irq(IRQ_MAC_ERROR);
627 bfin_mac_status_ack_irq(irq);
630 static void bfin_mac_status_unmask_irq(struct irq_data *d)
632 unsigned int irq = d->irq;
637 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
643 if (!mac_stat_int_mask)
644 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
646 mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
650 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
653 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
655 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
659 # define bfin_mac_status_set_wake NULL
662 static struct irq_chip bfin_mac_status_irqchip = {
664 .irq_mask = bfin_mac_status_mask_irq,
665 .irq_unmask = bfin_mac_status_unmask_irq,
666 .irq_set_wake = bfin_mac_status_set_wake,
669 void bfin_demux_mac_status_irq(unsigned int int_err_irq,
670 struct irq_desc *inta_desc)
673 u32 status = bfin_read_EMAC_SYSTAT();
675 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
676 if (status & (1L << i)) {
677 irq = IRQ_MAC_PHYINT + i;
682 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
683 bfin_handle_irq(irq);
685 bfin_mac_status_ack_irq(irq);
687 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
692 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
693 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
694 "(EMAC_SYSTAT=0x%X)\n",
695 __func__, __FILE__, __LINE__, status);
699 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
702 handle = handle_level_irq;
704 __irq_set_handler_locked(irq, handle);
707 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
708 extern void bfin_gpio_irq_prepare(unsigned gpio);
712 static void bfin_gpio_ack_irq(struct irq_data *d)
714 /* AFAIK ack_irq in case mask_ack is provided
715 * get's only called for edge sense irqs
717 set_gpio_data(irq_to_gpio(d->irq), 0);
720 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
722 unsigned int irq = d->irq;
723 u32 gpionr = irq_to_gpio(irq);
725 if (!irqd_is_level_type(d))
726 set_gpio_data(gpionr, 0);
728 set_gpio_maska(gpionr, 0);
731 static void bfin_gpio_mask_irq(struct irq_data *d)
733 set_gpio_maska(irq_to_gpio(d->irq), 0);
736 static void bfin_gpio_unmask_irq(struct irq_data *d)
738 set_gpio_maska(irq_to_gpio(d->irq), 1);
741 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
743 u32 gpionr = irq_to_gpio(d->irq);
745 if (__test_and_set_bit(gpionr, gpio_enabled))
746 bfin_gpio_irq_prepare(gpionr);
748 bfin_gpio_unmask_irq(d);
753 static void bfin_gpio_irq_shutdown(struct irq_data *d)
755 u32 gpionr = irq_to_gpio(d->irq);
757 bfin_gpio_mask_irq(d);
758 __clear_bit(gpionr, gpio_enabled);
759 bfin_gpio_irq_free(gpionr);
762 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
764 unsigned int irq = d->irq;
767 u32 gpionr = irq_to_gpio(irq);
769 if (type == IRQ_TYPE_PROBE) {
770 /* only probe unenabled GPIO interrupt lines */
771 if (test_bit(gpionr, gpio_enabled))
773 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
776 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
777 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
779 snprintf(buf, 16, "gpio-irq%d", irq);
780 ret = bfin_gpio_irq_request(gpionr, buf);
784 if (__test_and_set_bit(gpionr, gpio_enabled))
785 bfin_gpio_irq_prepare(gpionr);
788 __clear_bit(gpionr, gpio_enabled);
792 set_gpio_inen(gpionr, 0);
793 set_gpio_dir(gpionr, 0);
795 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
796 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
797 set_gpio_both(gpionr, 1);
799 set_gpio_both(gpionr, 0);
801 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
802 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
804 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
806 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
807 set_gpio_edge(gpionr, 1);
808 set_gpio_inen(gpionr, 1);
809 set_gpio_data(gpionr, 0);
812 set_gpio_edge(gpionr, 0);
813 set_gpio_inen(gpionr, 1);
816 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
817 bfin_set_irq_handler(irq, handle_edge_irq);
819 bfin_set_irq_handler(irq, handle_level_irq);
825 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
827 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
830 # define bfin_gpio_set_wake NULL
833 static void bfin_demux_gpio_block(unsigned int irq)
835 unsigned int gpio, mask;
837 gpio = irq_to_gpio(irq);
838 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
842 bfin_handle_irq(irq);
848 void bfin_demux_gpio_irq(unsigned int inta_irq,
849 struct irq_desc *desc)
854 #if defined(BF537_FAMILY)
855 case IRQ_PF_INTA_PG_INTA:
856 bfin_demux_gpio_block(IRQ_PF0);
859 case IRQ_PH_INTA_MAC_RX:
862 #elif defined(BF533_FAMILY)
866 #elif defined(BF538_FAMILY)
870 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
880 #elif defined(CONFIG_BF561)
896 bfin_demux_gpio_block(irq);
901 #define NR_PINT_BITS 32
902 #define IRQ_NOT_AVAIL 0xFF
904 #define PINT_2_BANK(x) ((x) >> 5)
905 #define PINT_2_BIT(x) ((x) & 0x1F)
906 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
908 static unsigned char irq2pint_lut[NR_PINTS];
909 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
911 static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
912 (struct bfin_pint_regs *)PINT0_MASK_SET,
913 (struct bfin_pint_regs *)PINT1_MASK_SET,
914 (struct bfin_pint_regs *)PINT2_MASK_SET,
915 (struct bfin_pint_regs *)PINT3_MASK_SET,
917 (struct bfin_pint_regs *)PINT4_MASK_SET,
918 (struct bfin_pint_regs *)PINT5_MASK_SET,
922 inline unsigned int get_irq_base(u32 bank, u8 bmap)
924 unsigned int irq_base;
927 if (bank < 2) { /*PA-PB */
928 irq_base = IRQ_PA0 + bmap * 16;
930 irq_base = IRQ_PC0 + bmap * 16;
933 irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
938 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
939 void init_pint_lut(void)
941 u16 bank, bit, irq_base, bit_pos;
945 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
947 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
949 pint_assign = pint[bank]->assign;
951 for (bit = 0; bit < NR_PINT_BITS; bit++) {
953 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
955 irq_base = get_irq_base(bank, bmap);
957 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
958 bit_pos = bit + bank * NR_PINT_BITS;
960 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
961 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
966 static void bfin_gpio_ack_irq(struct irq_data *d)
968 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
969 u32 pintbit = PINT_BIT(pint_val);
970 u32 bank = PINT_2_BANK(pint_val);
972 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
973 if (pint[bank]->invert_set & pintbit)
974 pint[bank]->invert_clear = pintbit;
976 pint[bank]->invert_set = pintbit;
978 pint[bank]->request = pintbit;
982 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
984 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
985 u32 pintbit = PINT_BIT(pint_val);
986 u32 bank = PINT_2_BANK(pint_val);
988 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
989 if (pint[bank]->invert_set & pintbit)
990 pint[bank]->invert_clear = pintbit;
992 pint[bank]->invert_set = pintbit;
995 pint[bank]->request = pintbit;
996 pint[bank]->mask_clear = pintbit;
999 static void bfin_gpio_mask_irq(struct irq_data *d)
1001 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1003 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
1006 static void bfin_gpio_unmask_irq(struct irq_data *d)
1008 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1009 u32 pintbit = PINT_BIT(pint_val);
1010 u32 bank = PINT_2_BANK(pint_val);
1012 pint[bank]->mask_set = pintbit;
1015 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
1017 unsigned int irq = d->irq;
1018 u32 gpionr = irq_to_gpio(irq);
1019 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1021 if (pint_val == IRQ_NOT_AVAIL) {
1023 "GPIO IRQ %d :Not in PINT Assign table "
1024 "Reconfigure Interrupt to Port Assignemt\n", irq);
1028 if (__test_and_set_bit(gpionr, gpio_enabled))
1029 bfin_gpio_irq_prepare(gpionr);
1031 bfin_gpio_unmask_irq(d);
1036 static void bfin_gpio_irq_shutdown(struct irq_data *d)
1038 u32 gpionr = irq_to_gpio(d->irq);
1040 bfin_gpio_mask_irq(d);
1041 __clear_bit(gpionr, gpio_enabled);
1042 bfin_gpio_irq_free(gpionr);
1045 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
1047 unsigned int irq = d->irq;
1050 u32 gpionr = irq_to_gpio(irq);
1051 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1052 u32 pintbit = PINT_BIT(pint_val);
1053 u32 bank = PINT_2_BANK(pint_val);
1055 if (pint_val == IRQ_NOT_AVAIL)
1058 if (type == IRQ_TYPE_PROBE) {
1059 /* only probe unenabled GPIO interrupt lines */
1060 if (test_bit(gpionr, gpio_enabled))
1062 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1065 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
1066 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1068 snprintf(buf, 16, "gpio-irq%d", irq);
1069 ret = bfin_gpio_irq_request(gpionr, buf);
1073 if (__test_and_set_bit(gpionr, gpio_enabled))
1074 bfin_gpio_irq_prepare(gpionr);
1077 __clear_bit(gpionr, gpio_enabled);
1081 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
1082 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
1084 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
1086 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
1087 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1088 if (gpio_get_value(gpionr))
1089 pint[bank]->invert_set = pintbit;
1091 pint[bank]->invert_clear = pintbit;
1094 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1095 pint[bank]->edge_set = pintbit;
1096 bfin_set_irq_handler(irq, handle_edge_irq);
1098 pint[bank]->edge_clear = pintbit;
1099 bfin_set_irq_handler(irq, handle_level_irq);
1106 static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS];
1107 static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
1109 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
1112 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1113 u32 bank = PINT_2_BANK(pint_val);
1117 pint_irq = IRQ_PINT0;
1120 pint_irq = IRQ_PINT2;
1123 pint_irq = IRQ_PINT3;
1126 pint_irq = IRQ_PINT1;
1130 pint_irq = IRQ_PINT4;
1133 pint_irq = IRQ_PINT5;
1141 bfin_internal_set_wake(pint_irq, state);
1147 void bfin_pint_suspend(void)
1151 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
1152 save_pint_reg[bank].mask_set = pint[bank]->mask_set;
1153 save_pint_reg[bank].assign = pint[bank]->assign;
1154 save_pint_reg[bank].edge_set = pint[bank]->edge_set;
1155 save_pint_reg[bank].invert_set = pint[bank]->invert_set;
1159 void bfin_pint_resume(void)
1163 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
1164 pint[bank]->mask_set = save_pint_reg[bank].mask_set;
1165 pint[bank]->assign = save_pint_reg[bank].assign;
1166 pint[bank]->edge_set = save_pint_reg[bank].edge_set;
1167 pint[bank]->invert_set = save_pint_reg[bank].invert_set;
1172 static int sec_suspend(void)
1176 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
1177 save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0));
1181 static void sec_resume(void)
1185 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1187 bfin_write_SEC_GCTL(SEC_GCTL_EN);
1188 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1190 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
1191 bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
1194 static struct syscore_ops sec_pm_syscore_ops = {
1195 .suspend = sec_suspend,
1196 .resume = sec_resume,
1201 # define bfin_gpio_set_wake NULL
1204 void bfin_demux_gpio_irq(unsigned int inta_irq,
1205 struct irq_desc *desc)
1211 struct irq_chip *chip = irq_desc_get_chip(desc);
1213 if (chip->irq_mask_ack) {
1214 chip->irq_mask_ack(&desc->irq_data);
1216 chip->irq_mask(&desc->irq_data);
1218 chip->irq_ack(&desc->irq_data);
1246 pint_val = bank * NR_PINT_BITS;
1248 request = pint[bank]->request;
1250 level_mask = pint[bank]->edge_set & request;
1254 irq = pint2irq_lut[pint_val] + SYS_IRQS;
1255 if (level_mask & PINT_BIT(pint_val)) {
1257 chip->irq_unmask(&desc->irq_data);
1259 bfin_handle_irq(irq);
1266 chip->irq_unmask(&desc->irq_data);
1270 static struct irq_chip bfin_gpio_irqchip = {
1272 .irq_ack = bfin_gpio_ack_irq,
1273 .irq_mask = bfin_gpio_mask_irq,
1274 .irq_mask_ack = bfin_gpio_mask_ack_irq,
1275 .irq_unmask = bfin_gpio_unmask_irq,
1276 .irq_disable = bfin_gpio_mask_irq,
1277 .irq_enable = bfin_gpio_unmask_irq,
1278 .irq_set_type = bfin_gpio_irq_type,
1279 .irq_startup = bfin_gpio_irq_startup,
1280 .irq_shutdown = bfin_gpio_irq_shutdown,
1281 .irq_set_wake = bfin_gpio_set_wake,
1284 void __cpuinit init_exception_vectors(void)
1286 /* cannot program in software:
1287 * evt0 - emulation (jtag)
1290 bfin_write_EVT2(evt_nmi);
1291 bfin_write_EVT3(trap);
1292 bfin_write_EVT5(evt_ivhw);
1293 bfin_write_EVT6(evt_timer);
1294 bfin_write_EVT7(evt_evt7);
1295 bfin_write_EVT8(evt_evt8);
1296 bfin_write_EVT9(evt_evt9);
1297 bfin_write_EVT10(evt_evt10);
1298 bfin_write_EVT11(evt_evt11);
1299 bfin_write_EVT12(evt_evt12);
1300 bfin_write_EVT13(evt_evt13);
1301 bfin_write_EVT14(evt_evt14);
1302 bfin_write_EVT15(evt_system_call);
1308 * This function should be called during kernel startup to initialize
1309 * the BFin IRQ handling routines.
1312 int __init init_arch_irq(void)
1315 unsigned long ilat = 0;
1317 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
1319 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1320 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1322 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1324 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1325 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1326 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1329 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1332 local_irq_disable();
1335 # ifdef CONFIG_PINTx_REASSIGN
1336 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1337 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1338 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1339 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1341 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1345 for (irq = 0; irq <= SYS_IRQS; irq++) {
1346 if (irq <= IRQ_CORETMR)
1347 irq_set_chip(irq, &bfin_core_irqchip);
1349 irq_set_chip(irq, &bfin_internal_irqchip);
1357 #elif defined(BF537_FAMILY)
1358 case IRQ_PH_INTA_MAC_RX:
1359 case IRQ_PF_INTA_PG_INTA:
1360 #elif defined(BF533_FAMILY)
1362 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1363 case IRQ_PORTF_INTA:
1364 case IRQ_PORTG_INTA:
1365 case IRQ_PORTH_INTA:
1366 #elif defined(CONFIG_BF561)
1367 case IRQ_PROG0_INTA:
1368 case IRQ_PROG1_INTA:
1369 case IRQ_PROG2_INTA:
1370 #elif defined(BF538_FAMILY)
1371 case IRQ_PORTF_INTA:
1373 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1375 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1377 irq_set_chained_handler(irq,
1378 bfin_demux_mac_status_irq);
1381 #if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1384 irq_set_handler(irq, handle_percpu_irq);
1388 #ifdef CONFIG_TICKSOURCE_CORETMR
1391 irq_set_handler(irq, handle_percpu_irq);
1393 irq_set_handler(irq, handle_simple_irq);
1398 #ifdef CONFIG_TICKSOURCE_GPTMR0
1400 irq_set_handler(irq, handle_simple_irq);
1406 irq_set_handler(irq, handle_level_irq);
1408 irq_set_handler(irq, handle_simple_irq);
1416 #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1417 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1418 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1421 /* if configured as edge, then will be changed to do_edge_IRQ */
1422 for (irq = GPIO_IRQ_BASE;
1423 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1424 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1426 bfin_write_IMASK(0);
1428 ilat = bfin_read_ILAT();
1430 bfin_write_ILAT(ilat);
1433 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1434 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1435 * local_irq_enable()
1438 /* Therefore it's better to setup IARs before interrupts enabled */
1441 /* Enable interrupts IVG7-15 */
1442 bfin_irq_flags |= IMASK_IVG15 |
1443 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1444 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1447 /* This implicitly covers ANOMALY_05000171
1448 * Boot-ROM code modifies SICA_IWRx wakeup registers
1451 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1453 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1454 * will screw up the bootrom as it relies on MDMA0/1 waking it
1455 * up from IDLE instructions. See this report for more info:
1456 * http://blackfin.uclinux.org/gf/tracker/4323
1458 if (ANOMALY_05000435)
1459 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1461 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1464 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1467 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1472 #ifdef CONFIG_DO_IRQ_L1
1473 __attribute__((l1_text))
1475 static int vec_to_irq(int vec)
1477 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1478 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1479 unsigned long sic_status[3];
1480 if (likely(vec == EVT_IVTMR_P))
1483 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1485 if (smp_processor_id()) {
1487 /* This will be optimized out in UP mode. */
1488 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1489 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1492 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1493 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1497 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1501 if (ivg >= ivg_stop)
1504 if (sic_status[0] & ivg->isrflag)
1506 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1512 #else /* SEC_GCTL */
1515 * This function should be called during kernel startup to initialize
1516 * the BFin IRQ handling routines.
1519 int __init init_arch_irq(void)
1522 unsigned long ilat = 0;
1524 bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1526 local_irq_disable();
1529 # ifdef CONFIG_PINTx_REASSIGN
1530 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1531 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1532 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1533 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1534 pint[4]->assign = CONFIG_PINT4_ASSIGN;
1535 pint[5]->assign = CONFIG_PINT5_ASSIGN;
1537 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1541 for (irq = 0; irq <= SYS_IRQS; irq++) {
1542 if (irq <= IRQ_CORETMR) {
1543 irq_set_chip_and_handler(irq, &bfin_core_irqchip,
1545 #if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP)
1546 if (irq == IRQ_CORETMR)
1547 irq_set_handler(irq, handle_percpu_irq);
1549 } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
1550 irq_set_chip(irq, &bfin_sec_irqchip);
1551 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1552 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
1553 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1556 irq_set_chip(irq, &bfin_sec_irqchip);
1557 if (irq == IRQ_SEC_ERR)
1558 irq_set_handler(irq, handle_sec_fault);
1559 else if (irq >= IRQ_C0_DBL_FAULT && irq < CORE_IRQS)
1560 irq_set_handler(irq, handle_core_fault);
1562 irq_set_handler(irq, handle_fasteoi_irq);
1563 __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1566 for (irq = GPIO_IRQ_BASE;
1567 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1568 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1571 bfin_write_IMASK(0);
1573 ilat = bfin_read_ILAT();
1575 bfin_write_ILAT(ilat);
1578 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1580 bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1582 bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1584 /* Enable interrupts IVG7-15 */
1585 bfin_irq_flags |= IMASK_IVG15 |
1586 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1587 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1590 bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
1591 bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0));
1592 bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0));
1593 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1595 bfin_write_SEC_GCTL(SEC_GCTL_EN);
1596 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1597 bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1599 init_software_driven_irq();
1602 register_syscore_ops(&sec_pm_syscore_ops);
1608 #ifdef CONFIG_DO_IRQ_L1
1609 __attribute__((l1_text))
1611 static int vec_to_irq(int vec)
1613 if (likely(vec == EVT_IVTMR_P))
1616 return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1618 #endif /* SEC_GCTL */
1620 #ifdef CONFIG_DO_IRQ_L1
1621 __attribute__((l1_text))
1623 void do_irq(int vec, struct pt_regs *fp)
1625 int irq = vec_to_irq(vec);
1628 asm_do_IRQ(irq, fp);
1633 int __ipipe_get_irq_priority(unsigned irq)
1637 if (irq <= IRQ_CORETMR)
1641 if (irq >= BFIN_IRQ(0))
1644 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1645 struct ivgx *ivg = ivg_table + ient;
1646 if (ivg->irqno == irq) {
1647 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1648 if (ivg7_13[prio].ifirst <= ivg &&
1649 ivg7_13[prio].istop > ivg)
1659 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1660 #ifdef CONFIG_DO_IRQ_L1
1661 __attribute__((l1_text))
1663 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1665 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1666 struct ipipe_domain *this_domain = __ipipe_current_domain;
1669 irq = vec_to_irq(vec);
1673 if (irq == IRQ_SYSTMR) {
1674 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1675 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1677 /* This is basically what we need from the register frame. */
1678 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1679 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1680 if (this_domain != ipipe_root_domain)
1681 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1683 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1687 * We don't want Linux interrupt handlers to run at the
1688 * current core priority level (i.e. < EVT15), since this
1689 * might delay other interrupts handled by a high priority
1690 * domain. Here is what we do instead:
1692 * - we raise the SYNCDEFER bit to prevent
1693 * __ipipe_handle_irq() to sync the pipeline for the root
1694 * stage for the incoming interrupt. Upon return, that IRQ is
1695 * pending in the interrupt log.
1697 * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1698 * that _schedule_and_signal_from_int will eventually sync the
1699 * pipeline from EVT15.
1701 if (this_domain == ipipe_root_domain) {
1702 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1706 ipipe_trace_irq_entry(irq);
1707 __ipipe_handle_irq(irq, regs);
1708 ipipe_trace_irq_exit(irq);
1710 if (user_mode(regs) &&
1711 !ipipe_test_foreign_stack() &&
1712 (current->ipipe_flags & PF_EVTRET) != 0) {
1714 * Testing for user_regs() does NOT fully eliminate
1715 * foreign stack contexts, because of the forged
1716 * interrupt returns we do through
1717 * __ipipe_call_irqtail. In that case, we might have
1718 * preempted a foreign stack context in a high
1719 * priority domain, with a single interrupt level now
1720 * pending after the irqtail unwinding is done. In
1721 * which case user_mode() is now true, and the event
1722 * gets dispatched spuriously.
1724 current->ipipe_flags &= ~PF_EVTRET;
1725 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1728 if (this_domain == ipipe_root_domain) {
1729 set_thread_flag(TIF_IRQ_SYNC);
1731 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1732 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1739 #endif /* CONFIG_IPIPE */