arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * Set up the interrupt priorities
   3  *
   4  * Copyright  2004-2009 Analog Devices Inc.
   5  *                 2003 Bas Vermeulen <bas@buyways.nl>
   6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
   7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
   8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *                 1996 Roman Zippel
  10  *
  11  * Licensed under the GPL-2
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/irq.h>
  18 #include <linux/sched.h>
  19 #include <linux/syscore_ops.h>
  20 #include <asm/delay.h>
  21 #ifdef CONFIG_IPIPE
  22 #include <linux/ipipe.h>
  23 #endif
  24 #include <asm/traps.h>
  25 #include <asm/blackfin.h>
  26 #include <asm/gpio.h>
  27 #include <asm/irq_handler.h>
  28 #include <asm/dpmc.h>
  29
  30 #ifndef SEC_GCTL
  31 # define SIC_SYSIRQ(irq)        (irq - (IRQ_CORETMR + 1))
  32 #else
  33 # define SIC_SYSIRQ(irq)        ((irq) - IVG15)
  34 #endif
  35
  36 /*
  37  * NOTES:
  38  * - we have separated the physical Hardware interrupt from the
  39  * levels that the LINUX kernel sees (see the description in irq.h)
  40  * -
  41  */
  42
  43 #ifndef CONFIG_SMP
  44 /* Initialize this to an actual value to force it into the .data
  45  * section so that we know it is properly initialized at entry into
  46  * the kernel but before bss is initialized to zero (which is where
  47  * it would live otherwise).  The 0x1f magic represents the IRQs we
  48  * cannot actually mask out in hardware.
  49  */
  50 unsigned long bfin_irq_flags = 0x1f;
  51 EXPORT_SYMBOL(bfin_irq_flags);
  52 #endif
  53
  54 #ifdef CONFIG_PM
  55 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  56 unsigned vr_wakeup;
  57 #endif
  58
  59 #ifndef SEC_GCTL
  60 static struct ivgx {
  61         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  62         unsigned int irqno;
  63         /* corresponding bit in the SIC_ISR register */
  64         unsigned int isrflag;
  65 } ivg_table[NR_PERI_INTS];
  66
  67 static struct ivg_slice {
  68         /* position of first irq in ivg_table for given ivg */
  69         struct ivgx *ifirst;
  70         struct ivgx *istop;
  71 } ivg7_13[IVG13 - IVG7 + 1];
  72
  73
  74 /*
  75  * Search SIC_IAR and fill tables with the irqvalues
  76  * and their positions in the SIC_ISR register.
  77  */
  78 static void __init search_IAR(void)
  79 {
  80         unsigned ivg, irq_pos = 0;
  81         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  82                 int irqN;
  83
  84                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  85
  86                 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
  87                         int irqn;
  88                         u32 iar =
  89                                 bfin_read32((unsigned long *)SIC_IAR0 +
  90 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
  91         defined(CONFIG_BF538) || defined(CONFIG_BF539)
  92                                 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
  93 #else
  94                                 (irqN >> 3)
  95 #endif
  96                                 );
  97                         for (irqn = irqN; irqn < irqN + 4; ++irqn) {
  98                                 int iar_shift = (irqn & 7) * 4;
  99                                 if (ivg == (0xf & (iar >> iar_shift))) {
 100                                         ivg_table[irq_pos].irqno = IVG7 + irqn;
 101                                         ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 102                                         ivg7_13[ivg].istop++;
 103                                         irq_pos++;
 104                                 }
 105                         }
 106                 }
 107         }
 108 }
 109 #endif
 110
 111 /*
 112  * This is for core internal IRQs
 113  */
 114 void bfin_ack_noop(struct irq_data *d)
 115 {
 116         /* Dummy function.  */
 117 }
 118
 119 static void bfin_core_mask_irq(struct irq_data *d)
 120 {
 121         bfin_irq_flags &= ~(1 << d->irq);
 122         if (!hard_irqs_disabled())
 123                 hard_local_irq_enable();
 124 }
 125
 126 static void bfin_core_unmask_irq(struct irq_data *d)
 127 {
 128         bfin_irq_flags |= 1 << d->irq;
 129         /*
 130          * If interrupts are enabled, IMASK must contain the same value
 131          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 132          * are currently disabled we need not do anything; one of the
 133          * callers will take care of setting IMASK to the proper value
 134          * when reenabling interrupts.
 135          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 136          * what we need.
 137          */
 138         if (!hard_irqs_disabled())
 139                 hard_local_irq_enable();
 140         return;
 141 }
 142
 143 void bfin_internal_mask_irq(unsigned int irq)
 144 {
 145         unsigned long flags = hard_local_irq_save();
 146 #ifndef SEC_GCTL
 147 #ifdef SIC_IMASK0
 148         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
 149         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
 150         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 151                         ~(1 << mask_bit));
 152 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
 153         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 154                         ~(1 << mask_bit));
 155 # endif
 156 #else
 157         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 158                         ~(1 << SIC_SYSIRQ(irq)));
 159 #endif /* end of SIC_IMASK0 */
 160 #endif
 161         hard_local_irq_restore(flags);
 162 }
 163
 164 static void bfin_internal_mask_irq_chip(struct irq_data *d)
 165 {
 166         bfin_internal_mask_irq(d->irq);
 167 }
 168
 169 #ifdef CONFIG_SMP
 170 void bfin_internal_unmask_irq_affinity(unsigned int irq,
 171                 const struct cpumask *affinity)
 172 #else
 173 void bfin_internal_unmask_irq(unsigned int irq)
 174 #endif
 175 {
 176         unsigned long flags = hard_local_irq_save();
 177
 178 #ifndef SEC_GCTL
 179 #ifdef SIC_IMASK0
 180         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
 181         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
 182 # ifdef CONFIG_SMP
 183         if (cpumask_test_cpu(0, affinity))
 184 # endif
 185                 bfin_write_SIC_IMASK(mask_bank,
 186                                 bfin_read_SIC_IMASK(mask_bank) |
 187                                 (1 << mask_bit));
 188 # ifdef CONFIG_SMP
 189         if (cpumask_test_cpu(1, affinity))
 190                 bfin_write_SICB_IMASK(mask_bank,
 191                                 bfin_read_SICB_IMASK(mask_bank) |
 192                                 (1 << mask_bit));
 193 # endif
 194 #else
 195         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 196                         (1 << SIC_SYSIRQ(irq)));
 197 #endif
 198 #endif
 199         hard_local_irq_restore(flags);
 200 }
 201
 202 #ifdef SEC_GCTL
 203 static void bfin_sec_preflow_handler(struct irq_data *d)
 204 {
 205         unsigned long flags = hard_local_irq_save();
 206         unsigned int sid = SIC_SYSIRQ(d->irq);
 207
 208         bfin_write_SEC_SCI(0, SEC_CSID, sid);
 209
 210         hard_local_irq_restore(flags);
 211 }
 212
 213 static void bfin_sec_mask_ack_irq(struct irq_data *d)
 214 {
 215         unsigned long flags = hard_local_irq_save();
 216         unsigned int sid = SIC_SYSIRQ(d->irq);
 217
 218         bfin_write_SEC_SCI(0, SEC_CSID, sid);
 219
 220         hard_local_irq_restore(flags);
 221 }
 222
 223 static void bfin_sec_unmask_irq(struct irq_data *d)
 224 {
 225         unsigned long flags = hard_local_irq_save();
 226         unsigned int sid = SIC_SYSIRQ(d->irq);
 227
 228         bfin_write32(SEC_END, sid);
 229
 230         hard_local_irq_restore(flags);
 231 }
 232
 233 static void bfin_sec_enable_ssi(unsigned int sid)
 234 {
 235         unsigned long flags = hard_local_irq_save();
 236         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 237
 238         reg_sctl |= SEC_SCTL_SRC_EN;
 239         bfin_write_SEC_SCTL(sid, reg_sctl);
 240
 241         hard_local_irq_restore(flags);
 242 }
 243
 244 static void bfin_sec_disable_ssi(unsigned int sid)
 245 {
 246         unsigned long flags = hard_local_irq_save();
 247         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 248
 249         reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
 250         bfin_write_SEC_SCTL(sid, reg_sctl);
 251
 252         hard_local_irq_restore(flags);
 253 }
 254
 255 static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
 256 {
 257         unsigned long flags = hard_local_irq_save();
 258         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 259
 260         reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
 261         bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
 262
 263         hard_local_irq_restore(flags);
 264 }
 265
 266 static void bfin_sec_enable_sci(unsigned int sid)
 267 {
 268         unsigned long flags = hard_local_irq_save();
 269         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 270
 271         if (sid == SIC_SYSIRQ(IRQ_WATCH0))
 272                 reg_sctl |= SEC_SCTL_FAULT_EN;
 273         else
 274                 reg_sctl |= SEC_SCTL_INT_EN;
 275         bfin_write_SEC_SCTL(sid, reg_sctl);
 276
 277         hard_local_irq_restore(flags);
 278 }
 279
 280 static void bfin_sec_disable_sci(unsigned int sid)
 281 {
 282         unsigned long flags = hard_local_irq_save();
 283         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 284
 285         reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
 286         bfin_write_SEC_SCTL(sid, reg_sctl);
 287
 288         hard_local_irq_restore(flags);
 289 }
 290
 291 static void bfin_sec_enable(struct irq_data *d)
 292 {
 293         unsigned long flags = hard_local_irq_save();
 294         unsigned int sid = SIC_SYSIRQ(d->irq);
 295
 296         bfin_sec_enable_sci(sid);
 297         bfin_sec_enable_ssi(sid);
 298
 299         hard_local_irq_restore(flags);
 300 }
 301
 302 static void bfin_sec_disable(struct irq_data *d)
 303 {
 304         unsigned long flags = hard_local_irq_save();
 305         unsigned int sid = SIC_SYSIRQ(d->irq);
 306
 307         bfin_sec_disable_sci(sid);
 308         bfin_sec_disable_ssi(sid);
 309
 310         hard_local_irq_restore(flags);
 311 }
 312
 313 static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
 314 {
 315         unsigned long flags = hard_local_irq_save();
 316         uint32_t reg_sctl;
 317         int i;
 318
 319         bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
 320
 321         for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
 322                 reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
 323                 reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
 324                 bfin_write_SEC_SCTL(i, reg_sctl);
 325         }
 326
 327         hard_local_irq_restore(flags);
 328 }
 329
 330 static void bfin_sec_raise_irq(unsigned int sid)
 331 {
 332         unsigned long flags = hard_local_irq_save();
 333
 334         bfin_write32(SEC_RAISE, sid);
 335
 336         hard_local_irq_restore(flags);
 337 }
 338
 339 static void init_software_driven_irq(void)
 340 {
 341         bfin_sec_set_ssi_coreid(34, 0);
 342         bfin_sec_set_ssi_coreid(35, 1);
 343         bfin_sec_set_ssi_coreid(36, 0);
 344         bfin_sec_set_ssi_coreid(37, 1);
 345 }
 346
 347 void bfin_sec_resume(void)
 348 {
 349         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
 350         udelay(100);
 351         bfin_write_SEC_GCTL(SEC_GCTL_EN);
 352         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
 353 }
 354
 355 void handle_sec_sfi_fault(uint32_t gstat)
 356 {
 357
 358 }
 359
 360 void handle_sec_sci_fault(uint32_t gstat)
 361 {
 362         uint32_t core_id;
 363         uint32_t cstat;
 364
 365         core_id = gstat & SEC_GSTAT_SCI;
 366         cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
 367         if (cstat & SEC_CSTAT_ERR) {
 368                 switch (cstat & SEC_CSTAT_ERRC) {
 369                 case SEC_CSTAT_ACKERR:
 370                         printk(KERN_DEBUG "sec ack err\n");
 371                         break;
 372                 default:
 373                         printk(KERN_DEBUG "sec sci unknow err\n");
 374                 }
 375         }
 376
 377 }
 378
 379 void handle_sec_ssi_fault(uint32_t gstat)
 380 {
 381         uint32_t sid;
 382         uint32_t sstat;
 383
 384         sid = gstat & SEC_GSTAT_SID;
 385         sstat = bfin_read_SEC_SSTAT(sid);
 386
 387 }
 388
 389 void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
 390 {
 391         uint32_t sec_gstat;
 392
 393         raw_spin_lock(&desc->lock);
 394
 395         sec_gstat = bfin_read32(SEC_GSTAT);
 396         if (sec_gstat & SEC_GSTAT_ERR) {
 397
 398                 switch (sec_gstat & SEC_GSTAT_ERRC) {
 399                 case 0:
 400                         handle_sec_sfi_fault(sec_gstat);
 401                         break;
 402                 case SEC_GSTAT_SCIERR:
 403                         handle_sec_sci_fault(sec_gstat);
 404                         break;
 405                 case SEC_GSTAT_SSIERR:
 406                         handle_sec_ssi_fault(sec_gstat);
 407                         break;
 408                 }
 409
 410
 411         }
 412
 413         raw_spin_unlock(&desc->lock);
 414 }
 415
 416 #endif
 417
 418 #ifdef CONFIG_SMP
 419 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 420 {
 421         bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
 422 }
 423
 424 static int bfin_internal_set_affinity(struct irq_data *d,
 425                                       const struct cpumask *mask, bool force)
 426 {
 427         bfin_internal_mask_irq(d->irq);
 428         bfin_internal_unmask_irq_affinity(d->irq, mask);
 429
 430         return 0;
 431 }
 432 #else
 433 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 434 {
 435         bfin_internal_unmask_irq(d->irq);
 436 }
 437 #endif
 438
 439 #if defined(CONFIG_PM) && !defined(SEC_GCTL)
 440 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 441 {
 442         u32 bank, bit, wakeup = 0;
 443         unsigned long flags;
 444         bank = SIC_SYSIRQ(irq) / 32;
 445         bit = SIC_SYSIRQ(irq) % 32;
 446
 447         switch (irq) {
 448 #ifdef IRQ_RTC
 449         case IRQ_RTC:
 450         wakeup |= WAKE;
 451         break;
 452 #endif
 453 #ifdef IRQ_CAN0_RX
 454         case IRQ_CAN0_RX:
 455         wakeup |= CANWE;
 456         break;
 457 #endif
 458 #ifdef IRQ_CAN1_RX
 459         case IRQ_CAN1_RX:
 460         wakeup |= CANWE;
 461         break;
 462 #endif
 463 #ifdef IRQ_USB_INT0
 464         case IRQ_USB_INT0:
 465         wakeup |= USBWE;
 466         break;
 467 #endif
 468 #ifdef CONFIG_BF54x
 469         case IRQ_CNT:
 470         wakeup |= ROTWE;
 471         break;
 472 #endif
 473         default:
 474         break;
 475         }
 476
 477         flags = hard_local_irq_save();
 478
 479         if (state) {
 480                 bfin_sic_iwr[bank] |= (1 << bit);
 481                 vr_wakeup  |= wakeup;
 482
 483         } else {
 484                 bfin_sic_iwr[bank] &= ~(1 << bit);
 485                 vr_wakeup  &= ~wakeup;
 486         }
 487
 488         hard_local_irq_restore(flags);
 489
 490         return 0;
 491 }
 492
 493 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
 494 {
 495         return bfin_internal_set_wake(d->irq, state);
 496 }
 497 #else
 498 inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 499 {
 500         return 0;
 501 }
 502 # define bfin_internal_set_wake_chip NULL
 503 #endif
 504
 505 static struct irq_chip bfin_core_irqchip = {
 506         .name = "CORE",
 507         .irq_mask = bfin_core_mask_irq,
 508         .irq_unmask = bfin_core_unmask_irq,
 509 };
 510
 511 static struct irq_chip bfin_internal_irqchip = {
 512         .name = "INTN",
 513         .irq_mask = bfin_internal_mask_irq_chip,
 514         .irq_unmask = bfin_internal_unmask_irq_chip,
 515         .irq_disable = bfin_internal_mask_irq_chip,
 516         .irq_enable = bfin_internal_unmask_irq_chip,
 517 #ifdef CONFIG_SMP
 518         .irq_set_affinity = bfin_internal_set_affinity,
 519 #endif
 520         .irq_set_wake = bfin_internal_set_wake_chip,
 521 };
 522
 523 #ifdef SEC_GCTL
 524 static struct irq_chip bfin_sec_irqchip = {
 525         .name = "SEC",
 526         .irq_mask_ack = bfin_sec_mask_ack_irq,
 527         .irq_mask = bfin_sec_mask_ack_irq,
 528         .irq_unmask = bfin_sec_unmask_irq,
 529         .irq_eoi = bfin_sec_unmask_irq,
 530         .irq_disable = bfin_sec_disable,
 531         .irq_enable = bfin_sec_enable,
 532 };
 533 #endif
 534
 535 void bfin_handle_irq(unsigned irq)
 536 {
 537 #ifdef CONFIG_IPIPE
 538         struct pt_regs regs;    /* Contents not used. */
 539         ipipe_trace_irq_entry(irq);
 540         __ipipe_handle_irq(irq, &regs);
 541         ipipe_trace_irq_exit(irq);
 542 #else /* !CONFIG_IPIPE */
 543         generic_handle_irq(irq);
 544 #endif  /* !CONFIG_IPIPE */
 545 }
 546
 547 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 548 static int mac_stat_int_mask;
 549
 550 static void bfin_mac_status_ack_irq(unsigned int irq)
 551 {
 552         switch (irq) {
 553         case IRQ_MAC_MMCINT:
 554                 bfin_write_EMAC_MMC_TIRQS(
 555                         bfin_read_EMAC_MMC_TIRQE() &
 556                         bfin_read_EMAC_MMC_TIRQS());
 557                 bfin_write_EMAC_MMC_RIRQS(
 558                         bfin_read_EMAC_MMC_RIRQE() &
 559                         bfin_read_EMAC_MMC_RIRQS());
 560                 break;
 561         case IRQ_MAC_RXFSINT:
 562                 bfin_write_EMAC_RX_STKY(
 563                         bfin_read_EMAC_RX_IRQE() &
 564                         bfin_read_EMAC_RX_STKY());
 565                 break;
 566         case IRQ_MAC_TXFSINT:
 567                 bfin_write_EMAC_TX_STKY(
 568                         bfin_read_EMAC_TX_IRQE() &
 569                         bfin_read_EMAC_TX_STKY());
 570                 break;
 571         case IRQ_MAC_WAKEDET:
 572                  bfin_write_EMAC_WKUP_CTL(
 573                         bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
 574                 break;
 575         default:
 576                 /* These bits are W1C */
 577                 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
 578                 break;
 579         }
 580 }
 581
 582 static void bfin_mac_status_mask_irq(struct irq_data *d)
 583 {
 584         unsigned int irq = d->irq;
 585
 586         mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
 587 #ifdef BF537_FAMILY
 588         switch (irq) {
 589         case IRQ_MAC_PHYINT:
 590                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
 591                 break;
 592         default:
 593                 break;
 594         }
 595 #else
 596         if (!mac_stat_int_mask)
 597                 bfin_internal_mask_irq(IRQ_MAC_ERROR);
 598 #endif
 599         bfin_mac_status_ack_irq(irq);
 600 }
 601
 602 static void bfin_mac_status_unmask_irq(struct irq_data *d)
 603 {
 604         unsigned int irq = d->irq;
 605
 606 #ifdef BF537_FAMILY
 607         switch (irq) {
 608         case IRQ_MAC_PHYINT:
 609                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
 610                 break;
 611         default:
 612                 break;
 613         }
 614 #else
 615         if (!mac_stat_int_mask)
 616                 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
 617 #endif
 618         mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
 619 }
 620
 621 #ifdef CONFIG_PM
 622 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
 623 {
 624 #ifdef BF537_FAMILY
 625         return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
 626 #else
 627         return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
 628 #endif
 629 }
 630 #else
 631 # define bfin_mac_status_set_wake NULL
 632 #endif
 633
 634 static struct irq_chip bfin_mac_status_irqchip = {
 635         .name = "MACST",
 636         .irq_mask = bfin_mac_status_mask_irq,
 637         .irq_unmask = bfin_mac_status_unmask_irq,
 638         .irq_set_wake = bfin_mac_status_set_wake,
 639 };
 640
 641 void bfin_demux_mac_status_irq(unsigned int int_err_irq,
 642                                struct irq_desc *inta_desc)
 643 {
 644         int i, irq = 0;
 645         u32 status = bfin_read_EMAC_SYSTAT();
 646
 647         for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
 648                 if (status & (1L << i)) {
 649                         irq = IRQ_MAC_PHYINT + i;
 650                         break;
 651                 }
 652
 653         if (irq) {
 654                 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
 655                         bfin_handle_irq(irq);
 656                 } else {
 657                         bfin_mac_status_ack_irq(irq);
 658                         pr_debug("IRQ %d:"
 659                                         " MASKED MAC ERROR INTERRUPT ASSERTED\n",
 660                                         irq);
 661                 }
 662         } else
 663                 printk(KERN_ERR
 664                                 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
 665                                 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
 666                                 "(EMAC_SYSTAT=0x%X)\n",
 667                                 __func__, __FILE__, __LINE__, status);
 668 }
 669 #endif
 670
 671 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 672 {
 673 #ifdef CONFIG_IPIPE
 674         handle = handle_level_irq;
 675 #endif
 676         __irq_set_handler_locked(irq, handle);
 677 }
 678
 679 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 680 extern void bfin_gpio_irq_prepare(unsigned gpio);
 681
 682 #if !BFIN_GPIO_PINT
 683
 684 static void bfin_gpio_ack_irq(struct irq_data *d)
 685 {
 686         /* AFAIK ack_irq in case mask_ack is provided
 687          * get's only called for edge sense irqs
 688          */
 689         set_gpio_data(irq_to_gpio(d->irq), 0);
 690 }
 691
 692 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
 693 {
 694         unsigned int irq = d->irq;
 695         u32 gpionr = irq_to_gpio(irq);
 696
 697         if (!irqd_is_level_type(d))
 698                 set_gpio_data(gpionr, 0);
 699
 700         set_gpio_maska(gpionr, 0);
 701 }
 702
 703 static void bfin_gpio_mask_irq(struct irq_data *d)
 704 {
 705         set_gpio_maska(irq_to_gpio(d->irq), 0);
 706 }
 707
 708 static void bfin_gpio_unmask_irq(struct irq_data *d)
 709 {
 710         set_gpio_maska(irq_to_gpio(d->irq), 1);
 711 }
 712
 713 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
 714 {
 715         u32 gpionr = irq_to_gpio(d->irq);
 716
 717         if (__test_and_set_bit(gpionr, gpio_enabled))
 718                 bfin_gpio_irq_prepare(gpionr);
 719
 720         bfin_gpio_unmask_irq(d);
 721
 722         return 0;
 723 }
 724
 725 static void bfin_gpio_irq_shutdown(struct irq_data *d)
 726 {
 727         u32 gpionr = irq_to_gpio(d->irq);
 728
 729         bfin_gpio_mask_irq(d);
 730         __clear_bit(gpionr, gpio_enabled);
 731         bfin_gpio_irq_free(gpionr);
 732 }
 733
 734 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
 735 {
 736         unsigned int irq = d->irq;
 737         int ret;
 738         char buf[16];
 739         u32 gpionr = irq_to_gpio(irq);
 740
 741         if (type == IRQ_TYPE_PROBE) {
 742                 /* only probe unenabled GPIO interrupt lines */
 743                 if (test_bit(gpionr, gpio_enabled))
 744                         return 0;
 745                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 746         }
 747
 748         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 749                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 750
 751                 snprintf(buf, 16, "gpio-irq%d", irq);
 752                 ret = bfin_gpio_irq_request(gpionr, buf);
 753                 if (ret)
 754                         return ret;
 755
 756                 if (__test_and_set_bit(gpionr, gpio_enabled))
 757                         bfin_gpio_irq_prepare(gpionr);
 758
 759         } else {
 760                 __clear_bit(gpionr, gpio_enabled);
 761                 return 0;
 762         }
 763
 764         set_gpio_inen(gpionr, 0);
 765         set_gpio_dir(gpionr, 0);
 766
 767         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 768             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 769                 set_gpio_both(gpionr, 1);
 770         else
 771                 set_gpio_both(gpionr, 0);
 772
 773         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 774                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 775         else
 776                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 777
 778         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 779                 set_gpio_edge(gpionr, 1);
 780                 set_gpio_inen(gpionr, 1);
 781                 set_gpio_data(gpionr, 0);
 782
 783         } else {
 784                 set_gpio_edge(gpionr, 0);
 785                 set_gpio_inen(gpionr, 1);
 786         }
 787
 788         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 789                 bfin_set_irq_handler(irq, handle_edge_irq);
 790         else
 791                 bfin_set_irq_handler(irq, handle_level_irq);
 792
 793         return 0;
 794 }
 795
 796 #ifdef CONFIG_PM
 797 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 798 {
 799         return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
 800 }
 801 #else
 802 # define bfin_gpio_set_wake NULL
 803 #endif
 804
 805 static void bfin_demux_gpio_block(unsigned int irq)
 806 {
 807         unsigned int gpio, mask;
 808
 809         gpio = irq_to_gpio(irq);
 810         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 811
 812         while (mask) {
 813                 if (mask & 1)
 814                         bfin_handle_irq(irq);
 815                 irq++;
 816                 mask >>= 1;
 817         }
 818 }
 819
 820 void bfin_demux_gpio_irq(unsigned int inta_irq,
 821                         struct irq_desc *desc)
 822 {
 823         unsigned int irq;
 824
 825         switch (inta_irq) {
 826 #if defined(BF537_FAMILY)
 827         case IRQ_PF_INTA_PG_INTA:
 828                 bfin_demux_gpio_block(IRQ_PF0);
 829                 irq = IRQ_PG0;
 830                 break;
 831         case IRQ_PH_INTA_MAC_RX:
 832                 irq = IRQ_PH0;
 833                 break;
 834 #elif defined(BF533_FAMILY)
 835         case IRQ_PROG_INTA:
 836                 irq = IRQ_PF0;
 837                 break;
 838 #elif defined(BF538_FAMILY)
 839         case IRQ_PORTF_INTA:
 840                 irq = IRQ_PF0;
 841                 break;
 842 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 843         case IRQ_PORTF_INTA:
 844                 irq = IRQ_PF0;
 845                 break;
 846         case IRQ_PORTG_INTA:
 847                 irq = IRQ_PG0;
 848                 break;
 849         case IRQ_PORTH_INTA:
 850                 irq = IRQ_PH0;
 851                 break;
 852 #elif defined(CONFIG_BF561)
 853         case IRQ_PROG0_INTA:
 854                 irq = IRQ_PF0;
 855                 break;
 856         case IRQ_PROG1_INTA:
 857                 irq = IRQ_PF16;
 858                 break;
 859         case IRQ_PROG2_INTA:
 860                 irq = IRQ_PF32;
 861                 break;
 862 #endif
 863         default:
 864                 BUG();
 865                 return;
 866         }
 867
 868         bfin_demux_gpio_block(irq);
 869 }
 870
 871 #else
 872
 873 #define NR_PINT_BITS            32
 874 #define IRQ_NOT_AVAIL           0xFF
 875
 876 #define PINT_2_BANK(x)          ((x) >> 5)
 877 #define PINT_2_BIT(x)           ((x) & 0x1F)
 878 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 879
 880 static unsigned char irq2pint_lut[NR_PINTS];
 881 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 882
 883 static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
 884         (struct bfin_pint_regs *)PINT0_MASK_SET,
 885         (struct bfin_pint_regs *)PINT1_MASK_SET,
 886         (struct bfin_pint_regs *)PINT2_MASK_SET,
 887         (struct bfin_pint_regs *)PINT3_MASK_SET,
 888 #ifdef CONFIG_BF60x
 889         (struct bfin_pint_regs *)PINT4_MASK_SET,
 890         (struct bfin_pint_regs *)PINT5_MASK_SET,
 891 #endif
 892 };
 893
 894 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 895 {
 896         unsigned int irq_base;
 897
 898 #ifndef CONFIG_BF60x
 899         if (bank < 2) {         /*PA-PB */
 900                 irq_base = IRQ_PA0 + bmap * 16;
 901         } else {                /*PC-PJ */
 902                 irq_base = IRQ_PC0 + bmap * 16;
 903         }
 904 #else
 905         irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
 906 #endif
 907         return irq_base;
 908 }
 909
 910         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 911 void init_pint_lut(void)
 912 {
 913         u16 bank, bit, irq_base, bit_pos;
 914         u32 pint_assign;
 915         u8 bmap;
 916
 917         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 918
 919         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 920
 921                 pint_assign = pint[bank]->assign;
 922
 923                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 924
 925                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 926
 927                         irq_base = get_irq_base(bank, bmap);
 928
 929                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 930                         bit_pos = bit + bank * NR_PINT_BITS;
 931
 932                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 933                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 934                 }
 935         }
 936 }
 937
 938 static void bfin_gpio_ack_irq(struct irq_data *d)
 939 {
 940         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 941         u32 pintbit = PINT_BIT(pint_val);
 942         u32 bank = PINT_2_BANK(pint_val);
 943
 944         if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
 945                 if (pint[bank]->invert_set & pintbit)
 946                         pint[bank]->invert_clear = pintbit;
 947                 else
 948                         pint[bank]->invert_set = pintbit;
 949         }
 950         pint[bank]->request = pintbit;
 951
 952 }
 953
 954 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
 955 {
 956         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 957         u32 pintbit = PINT_BIT(pint_val);
 958         u32 bank = PINT_2_BANK(pint_val);
 959
 960         if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
 961                 if (pint[bank]->invert_set & pintbit)
 962                         pint[bank]->invert_clear = pintbit;
 963                 else
 964                         pint[bank]->invert_set = pintbit;
 965         }
 966
 967         pint[bank]->request = pintbit;
 968         pint[bank]->mask_clear = pintbit;
 969 }
 970
 971 static void bfin_gpio_mask_irq(struct irq_data *d)
 972 {
 973         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 974
 975         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 976 }
 977
 978 static void bfin_gpio_unmask_irq(struct irq_data *d)
 979 {
 980         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 981         u32 pintbit = PINT_BIT(pint_val);
 982         u32 bank = PINT_2_BANK(pint_val);
 983
 984         pint[bank]->mask_set = pintbit;
 985 }
 986
 987 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
 988 {
 989         unsigned int irq = d->irq;
 990         u32 gpionr = irq_to_gpio(irq);
 991         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 992
 993         if (pint_val == IRQ_NOT_AVAIL) {
 994                 printk(KERN_ERR
 995                 "GPIO IRQ %d :Not in PINT Assign table "
 996                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 997                 return -ENODEV;
 998         }
 999
1000         if (__test_and_set_bit(gpionr, gpio_enabled))
1001                 bfin_gpio_irq_prepare(gpionr);
1002
1003         bfin_gpio_unmask_irq(d);
1004
1005         return 0;
1006 }
1007
1008 static void bfin_gpio_irq_shutdown(struct irq_data *d)
1009 {
1010         u32 gpionr = irq_to_gpio(d->irq);
1011
1012         bfin_gpio_mask_irq(d);
1013         __clear_bit(gpionr, gpio_enabled);
1014         bfin_gpio_irq_free(gpionr);
1015 }
1016
1017 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
1018 {
1019         unsigned int irq = d->irq;
1020         int ret;
1021         char buf[16];
1022         u32 gpionr = irq_to_gpio(irq);
1023         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1024         u32 pintbit = PINT_BIT(pint_val);
1025         u32 bank = PINT_2_BANK(pint_val);
1026
1027         if (pint_val == IRQ_NOT_AVAIL)
1028                 return -ENODEV;
1029
1030         if (type == IRQ_TYPE_PROBE) {
1031                 /* only probe unenabled GPIO interrupt lines */
1032                 if (test_bit(gpionr, gpio_enabled))
1033                         return 0;
1034                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1035         }
1036
1037         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
1038                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1039
1040                 snprintf(buf, 16, "gpio-irq%d", irq);
1041                 ret = bfin_gpio_irq_request(gpionr, buf);
1042                 if (ret)
1043                         return ret;
1044
1045                 if (__test_and_set_bit(gpionr, gpio_enabled))
1046                         bfin_gpio_irq_prepare(gpionr);
1047
1048         } else {
1049                 __clear_bit(gpionr, gpio_enabled);
1050                 return 0;
1051         }
1052
1053         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
1054                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
1055         else
1056                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
1057
1058         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
1059             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1060                 if (gpio_get_value(gpionr))
1061                         pint[bank]->invert_set = pintbit;
1062                 else
1063                         pint[bank]->invert_clear = pintbit;
1064         }
1065
1066         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1067                 pint[bank]->edge_set = pintbit;
1068                 bfin_set_irq_handler(irq, handle_edge_irq);
1069         } else {
1070                 pint[bank]->edge_clear = pintbit;
1071                 bfin_set_irq_handler(irq, handle_level_irq);
1072         }
1073
1074         return 0;
1075 }
1076
1077 #ifdef CONFIG_PM
1078 static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS];
1079 static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
1080
1081 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
1082 {
1083         u32 pint_irq;
1084         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1085         u32 bank = PINT_2_BANK(pint_val);
1086
1087         switch (bank) {
1088         case 0:
1089                 pint_irq = IRQ_PINT0;
1090                 break;
1091         case 2:
1092                 pint_irq = IRQ_PINT2;
1093                 break;
1094         case 3:
1095                 pint_irq = IRQ_PINT3;
1096                 break;
1097         case 1:
1098                 pint_irq = IRQ_PINT1;
1099                 break;
1100 #ifdef CONFIG_BF60x
1101         case 4:
1102                 pint_irq = IRQ_PINT4;
1103                 break;
1104         case 5:
1105                 pint_irq = IRQ_PINT5;
1106                 break;
1107 #endif
1108         default:
1109                 return -EINVAL;
1110         }
1111
1112         bfin_internal_set_wake(pint_irq, state);
1113
1114         return 0;
1115 }
1116
1117 void bfin_pint_suspend(void)
1118 {
1119         u32 bank;
1120
1121         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
1122                 save_pint_reg[bank].mask_set = pint[bank]->mask_set;
1123                 save_pint_reg[bank].assign = pint[bank]->assign;
1124                 save_pint_reg[bank].edge_set = pint[bank]->edge_set;
1125                 save_pint_reg[bank].invert_set = pint[bank]->invert_set;
1126         }
1127 }
1128
1129 void bfin_pint_resume(void)
1130 {
1131         u32 bank;
1132
1133         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
1134                 pint[bank]->mask_set = save_pint_reg[bank].mask_set;
1135                 pint[bank]->assign = save_pint_reg[bank].assign;
1136                 pint[bank]->edge_set = save_pint_reg[bank].edge_set;
1137                 pint[bank]->invert_set = save_pint_reg[bank].invert_set;
1138         }
1139 }
1140
1141 #ifdef SEC_GCTL
1142 static int sec_suspend(void)
1143 {
1144         u32 bank;
1145
1146         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
1147                 save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0));
1148         return 0;
1149 }
1150
1151 static void sec_resume(void)
1152 {
1153         u32 bank;
1154
1155         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1156         udelay(100);
1157         bfin_write_SEC_GCTL(SEC_GCTL_EN);
1158         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1159
1160         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
1161                 bfin_write_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
1162 }
1163
1164 static struct syscore_ops sec_pm_syscore_ops = {
1165         .suspend = sec_suspend,
1166         .resume = sec_resume,
1167 };
1168 #endif
1169 #else
1170 # define bfin_gpio_set_wake NULL
1171 #endif
1172
1173 void bfin_demux_gpio_irq(unsigned int inta_irq,
1174                         struct irq_desc *desc)
1175 {
1176         u32 bank, pint_val;
1177         u32 request, irq;
1178         u32 level_mask;
1179         int umask = 0;
1180         struct irq_chip *chip = irq_desc_get_chip(desc);
1181
1182         if (chip->irq_mask_ack) {
1183                 chip->irq_mask_ack(&desc->irq_data);
1184         } else {
1185                 chip->irq_mask(&desc->irq_data);
1186                 if (chip->irq_ack)
1187                         chip->irq_ack(&desc->irq_data);
1188         }
1189
1190         switch (inta_irq) {
1191         case IRQ_PINT0:
1192                 bank = 0;
1193                 break;
1194         case IRQ_PINT2:
1195                 bank = 2;
1196                 break;
1197         case IRQ_PINT3:
1198                 bank = 3;
1199                 break;
1200         case IRQ_PINT1:
1201                 bank = 1;
1202                 break;
1203 #ifdef CONFIG_BF60x
1204         case IRQ_PINT4:
1205                 bank = 4;
1206                 break;
1207         case IRQ_PINT5:
1208                 bank = 5;
1209                 break;
1210 #endif
1211         default:
1212                 return;
1213         }
1214
1215         pint_val = bank * NR_PINT_BITS;
1216
1217         request = pint[bank]->request;
1218
1219         level_mask = pint[bank]->edge_set & request;
1220
1221         while (request) {
1222                 if (request & 1) {
1223                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
1224                         if (level_mask & PINT_BIT(pint_val)) {
1225                                 umask = 1;
1226                                 chip->irq_unmask(&desc->irq_data);
1227                         }
1228                         bfin_handle_irq(irq);
1229                 }
1230                 pint_val++;
1231                 request >>= 1;
1232         }
1233
1234         if (!umask)
1235                 chip->irq_unmask(&desc->irq_data);
1236 }
1237 #endif
1238
1239 static struct irq_chip bfin_gpio_irqchip = {
1240         .name = "GPIO",
1241         .irq_ack = bfin_gpio_ack_irq,
1242         .irq_mask = bfin_gpio_mask_irq,
1243         .irq_mask_ack = bfin_gpio_mask_ack_irq,
1244         .irq_unmask = bfin_gpio_unmask_irq,
1245         .irq_disable = bfin_gpio_mask_irq,
1246         .irq_enable = bfin_gpio_unmask_irq,
1247         .irq_set_type = bfin_gpio_irq_type,
1248         .irq_startup = bfin_gpio_irq_startup,
1249         .irq_shutdown = bfin_gpio_irq_shutdown,
1250         .irq_set_wake = bfin_gpio_set_wake,
1251 };
1252
1253 void __cpuinit init_exception_vectors(void)
1254 {
1255         /* cannot program in software:
1256          * evt0 - emulation (jtag)
1257          * evt1 - reset
1258          */
1259         bfin_write_EVT2(evt_nmi);
1260         bfin_write_EVT3(trap);
1261         bfin_write_EVT5(evt_ivhw);
1262         bfin_write_EVT6(evt_timer);
1263         bfin_write_EVT7(evt_evt7);
1264         bfin_write_EVT8(evt_evt8);
1265         bfin_write_EVT9(evt_evt9);
1266         bfin_write_EVT10(evt_evt10);
1267         bfin_write_EVT11(evt_evt11);
1268         bfin_write_EVT12(evt_evt12);
1269         bfin_write_EVT13(evt_evt13);
1270         bfin_write_EVT14(evt_evt14);
1271         bfin_write_EVT15(evt_system_call);
1272         CSYNC();
1273 }
1274
1275 #ifndef SEC_GCTL
1276 /*
1277  * This function should be called during kernel startup to initialize
1278  * the BFin IRQ handling routines.
1279  */
1280
1281 int __init init_arch_irq(void)
1282 {
1283         int irq;
1284         unsigned long ilat = 0;
1285
1286         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
1287 #ifdef SIC_IMASK0
1288         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1289         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1290 # ifdef SIC_IMASK2
1291         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1292 # endif
1293 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1294         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1295         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1296 # endif
1297 #else
1298         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1299 #endif
1300
1301         local_irq_disable();
1302
1303 #if BFIN_GPIO_PINT
1304 # ifdef CONFIG_PINTx_REASSIGN
1305         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1306         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1307         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1308         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1309 # endif
1310         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1311         init_pint_lut();
1312 #endif
1313
1314         for (irq = 0; irq <= SYS_IRQS; irq++) {
1315                 if (irq <= IRQ_CORETMR)
1316                         irq_set_chip(irq, &bfin_core_irqchip);
1317                 else
1318                         irq_set_chip(irq, &bfin_internal_irqchip);
1319
1320                 switch (irq) {
1321 #if BFIN_GPIO_PINT
1322                 case IRQ_PINT0:
1323                 case IRQ_PINT1:
1324                 case IRQ_PINT2:
1325                 case IRQ_PINT3:
1326 #elif defined(BF537_FAMILY)
1327                 case IRQ_PH_INTA_MAC_RX:
1328                 case IRQ_PF_INTA_PG_INTA:
1329 #elif defined(BF533_FAMILY)
1330                 case IRQ_PROG_INTA:
1331 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1332                 case IRQ_PORTF_INTA:
1333                 case IRQ_PORTG_INTA:
1334                 case IRQ_PORTH_INTA:
1335 #elif defined(CONFIG_BF561)
1336                 case IRQ_PROG0_INTA:
1337                 case IRQ_PROG1_INTA:
1338                 case IRQ_PROG2_INTA:
1339 #elif defined(BF538_FAMILY)
1340                 case IRQ_PORTF_INTA:
1341 #endif
1342                         irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1343                         break;
1344 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1345                 case IRQ_MAC_ERROR:
1346                         irq_set_chained_handler(irq,
1347                                                 bfin_demux_mac_status_irq);
1348                         break;
1349 #endif
1350 #if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1351                 case IRQ_SUPPLE_0:
1352                 case IRQ_SUPPLE_1:
1353                         irq_set_handler(irq, handle_percpu_irq);
1354                         break;
1355 #endif
1356
1357 #ifdef CONFIG_TICKSOURCE_CORETMR
1358                 case IRQ_CORETMR:
1359 # ifdef CONFIG_SMP
1360                         irq_set_handler(irq, handle_percpu_irq);
1361 # else
1362                         irq_set_handler(irq, handle_simple_irq);
1363 # endif
1364                         break;
1365 #endif
1366
1367 #ifdef CONFIG_TICKSOURCE_GPTMR0
1368                 case IRQ_TIMER0:
1369                         irq_set_handler(irq, handle_simple_irq);
1370                         break;
1371 #endif
1372
1373                 default:
1374 #ifdef CONFIG_IPIPE
1375                         irq_set_handler(irq, handle_level_irq);
1376 #else
1377                         irq_set_handler(irq, handle_simple_irq);
1378 #endif
1379                         break;
1380                 }
1381         }
1382
1383         init_mach_irq();
1384
1385 #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1386         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1387                 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1388                                          handle_level_irq);
1389 #endif
1390         /* if configured as edge, then will be changed to do_edge_IRQ */
1391         for (irq = GPIO_IRQ_BASE;
1392                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1393                 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1394                                          handle_level_irq);
1395         bfin_write_IMASK(0);
1396         CSYNC();
1397         ilat = bfin_read_ILAT();
1398         CSYNC();
1399         bfin_write_ILAT(ilat);
1400         CSYNC();
1401
1402         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1403         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1404          * local_irq_enable()
1405          */
1406         program_IAR();
1407         /* Therefore it's better to setup IARs before interrupts enabled */
1408         search_IAR();
1409
1410         /* Enable interrupts IVG7-15 */
1411         bfin_irq_flags |= IMASK_IVG15 |
1412                 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1413                 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1414
1415         bfin_sti(bfin_irq_flags);
1416
1417         /* This implicitly covers ANOMALY_05000171
1418          * Boot-ROM code modifies SICA_IWRx wakeup registers
1419          */
1420 #ifdef SIC_IWR0
1421         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1422 # ifdef SIC_IWR1
1423         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1424          * will screw up the bootrom as it relies on MDMA0/1 waking it
1425          * up from IDLE instructions.  See this report for more info:
1426          * http://blackfin.uclinux.org/gf/tracker/4323
1427          */
1428         if (ANOMALY_05000435)
1429                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1430         else
1431                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1432 # endif
1433 # ifdef SIC_IWR2
1434         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1435 # endif
1436 #else
1437         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1438 #endif
1439         return 0;
1440 }
1441
1442 #ifdef CONFIG_DO_IRQ_L1
1443 __attribute__((l1_text))
1444 #endif
1445 static int vec_to_irq(int vec)
1446 {
1447         struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1448         struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1449         unsigned long sic_status[3];
1450         if (likely(vec == EVT_IVTMR_P))
1451                 return IRQ_CORETMR;
1452 #ifdef SIC_ISR
1453         sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1454 #else
1455         if (smp_processor_id()) {
1456 # ifdef SICB_ISR0
1457                 /* This will be optimized out in UP mode. */
1458                 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1459                 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1460 # endif
1461         } else {
1462                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1463                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1464         }
1465 #endif
1466 #ifdef SIC_ISR2
1467         sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1468 #endif
1469
1470         for (;; ivg++) {
1471                 if (ivg >= ivg_stop)
1472                         return -1;
1473 #ifdef SIC_ISR
1474                 if (sic_status[0] & ivg->isrflag)
1475 #else
1476                 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1477 #endif
1478                         return ivg->irqno;
1479         }
1480 }
1481
1482 #else /* SEC_GCTL */
1483
1484 /*
1485  * This function should be called during kernel startup to initialize
1486  * the BFin IRQ handling routines.
1487  */
1488
1489 int __init init_arch_irq(void)
1490 {
1491         int irq;
1492         unsigned long ilat = 0;
1493
1494         bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1495
1496         local_irq_disable();
1497
1498 #if BFIN_GPIO_PINT
1499 # ifdef CONFIG_PINTx_REASSIGN
1500         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1501         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1502         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1503         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1504         pint[4]->assign = CONFIG_PINT4_ASSIGN;
1505         pint[5]->assign = CONFIG_PINT5_ASSIGN;
1506 # endif
1507         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1508         init_pint_lut();
1509 #endif
1510
1511         for (irq = 0; irq <= SYS_IRQS; irq++) {
1512                 if (irq <= IRQ_CORETMR) {
1513                         irq_set_chip(irq, &bfin_core_irqchip);
1514 #ifdef CONFIG_TICKSOURCE_CORETMR
1515                         if (irq == IRQ_CORETMR)
1516 # ifdef CONFIG_SMP
1517                                 irq_set_handler(irq, handle_percpu_irq);
1518 # else
1519                                 irq_set_handler(irq, handle_simple_irq);
1520 # endif
1521 #endif
1522                 } else if (irq < BFIN_IRQ(0)) {
1523                         irq_set_chip_and_handler(irq, &bfin_internal_irqchip,
1524                                         handle_simple_irq);
1525                 } else if (irq < CORE_IRQS && irq != IRQ_CGU_EVT) {
1526                         irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1527                                         handle_sec_fault);
1528                 } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
1529                         irq_set_chip(irq, &bfin_sec_irqchip);
1530                         irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1531                 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
1532                         irq_set_chip(irq, &bfin_sec_irqchip);
1533                         irq_set_handler(irq, handle_percpu_irq);
1534                 } else {
1535                         irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1536                                         handle_fasteoi_irq);
1537                         __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1538                 }
1539         }
1540         for (irq = GPIO_IRQ_BASE;
1541                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1542                 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1543                                         handle_level_irq);
1544
1545         bfin_write_IMASK(0);
1546         CSYNC();
1547         ilat = bfin_read_ILAT();
1548         CSYNC();
1549         bfin_write_ILAT(ilat);
1550         CSYNC();
1551
1552         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1553
1554         bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1555
1556         bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1557
1558         /* Enable interrupts IVG7-15 */
1559         bfin_irq_flags |= IMASK_IVG15 |
1560             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1561             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1562
1563
1564         bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
1565         bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
1566         bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
1567         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1568         udelay(100);
1569         bfin_write_SEC_GCTL(SEC_GCTL_EN);
1570         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1571         bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1572
1573         init_software_driven_irq();
1574         register_syscore_ops(&sec_pm_syscore_ops);
1575
1576         return 0;
1577 }
1578
1579 #ifdef CONFIG_DO_IRQ_L1
1580 __attribute__((l1_text))
1581 #endif
1582 static int vec_to_irq(int vec)
1583 {
1584         if (likely(vec == EVT_IVTMR_P))
1585                 return IRQ_CORETMR;
1586
1587         return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1588 }
1589 #endif  /* SEC_GCTL */
1590
1591 #ifdef CONFIG_DO_IRQ_L1
1592 __attribute__((l1_text))
1593 #endif
1594 void do_irq(int vec, struct pt_regs *fp)
1595 {
1596         int irq = vec_to_irq(vec);
1597         if (irq == -1)
1598                 return;
1599         asm_do_IRQ(irq, fp);
1600 }
1601
1602 #ifdef CONFIG_IPIPE
1603
1604 int __ipipe_get_irq_priority(unsigned irq)
1605 {
1606         int ient, prio;
1607
1608         if (irq <= IRQ_CORETMR)
1609                 return irq;
1610
1611 #ifdef SEC_GCTL
1612         if (irq >= BFIN_IRQ(0))
1613                 return IVG11;
1614 #else
1615         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1616                 struct ivgx *ivg = ivg_table + ient;
1617                 if (ivg->irqno == irq) {
1618                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1619                                 if (ivg7_13[prio].ifirst <= ivg &&
1620                                     ivg7_13[prio].istop > ivg)
1621                                         return IVG7 + prio;
1622                         }
1623                 }
1624         }
1625 #endif
1626
1627         return IVG15;
1628 }
1629
1630 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1631 #ifdef CONFIG_DO_IRQ_L1
1632 __attribute__((l1_text))
1633 #endif
1634 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1635 {
1636         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1637         struct ipipe_domain *this_domain = __ipipe_current_domain;
1638         int irq, s = 0;
1639
1640         irq = vec_to_irq(vec);
1641         if (irq == -1)
1642                 return 0;
1643
1644         if (irq == IRQ_SYSTMR) {
1645 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1646                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1647 #endif
1648                 /* This is basically what we need from the register frame. */
1649                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1650                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1651                 if (this_domain != ipipe_root_domain)
1652                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1653                 else
1654                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1655         }
1656
1657         /*
1658          * We don't want Linux interrupt handlers to run at the
1659          * current core priority level (i.e. < EVT15), since this
1660          * might delay other interrupts handled by a high priority
1661          * domain. Here is what we do instead:
1662          *
1663          * - we raise the SYNCDEFER bit to prevent
1664          * __ipipe_handle_irq() to sync the pipeline for the root
1665          * stage for the incoming interrupt. Upon return, that IRQ is
1666          * pending in the interrupt log.
1667          *
1668          * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1669          * that _schedule_and_signal_from_int will eventually sync the
1670          * pipeline from EVT15.
1671          */
1672         if (this_domain == ipipe_root_domain) {
1673                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1674                 barrier();
1675         }
1676
1677         ipipe_trace_irq_entry(irq);
1678         __ipipe_handle_irq(irq, regs);
1679         ipipe_trace_irq_exit(irq);
1680
1681         if (user_mode(regs) &&
1682             !ipipe_test_foreign_stack() &&
1683             (current->ipipe_flags & PF_EVTRET) != 0) {
1684                 /*
1685                  * Testing for user_regs() does NOT fully eliminate
1686                  * foreign stack contexts, because of the forged
1687                  * interrupt returns we do through
1688                  * __ipipe_call_irqtail. In that case, we might have
1689                  * preempted a foreign stack context in a high
1690                  * priority domain, with a single interrupt level now
1691                  * pending after the irqtail unwinding is done. In
1692                  * which case user_mode() is now true, and the event
1693                  * gets dispatched spuriously.
1694                  */
1695                 current->ipipe_flags &= ~PF_EVTRET;
1696                 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1697         }
1698
1699         if (this_domain == ipipe_root_domain) {
1700                 set_thread_flag(TIF_IRQ_SYNC);
1701                 if (!s) {
1702                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1703                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1704                 }
1705         }
1706
1707         return 0;
1708 }
1709
1710 #endif /* CONFIG_IPIPE */