2 * File: arch/blackfin/mach-common/lock.S
4 * Author: LG Soft India
7 * Description: kernel locks
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/linkage.h>
32 #include <asm/blackfin.h>
36 #ifdef CONFIG_BLKFIN_CACHE_LOCK
38 /* When you come here, it is assumed that
39 * R0 - Which way to be locked
42 ENTRY(_cache_grab_lock)
46 P1.H = HI(IMEM_CONTROL);
47 P1.L = LO(IMEM_CONTROL);
48 P5.H = HI(ICPLB_ADDR0);
49 P5.L = LO(ICPLB_ADDR0);
50 P4.H = HI(ICPLB_DATA0);
51 P4.L = LO(ICPLB_DATA0);
54 /* If the code of interest already resides in the cache
55 * invalidate the entire cache itself.
56 * invalidate_entire_icache;
61 CALL _invalidate_entire_icache;
65 /* Disable the Interrupts*/
73 * Way2 - 0xFFA13BE0 Total Way Size = 4K
77 /* Procedure Ex. -Set the locks for other ways by setting ILOC[3:1]
78 * Only Way0 of the instruction cache can now be
79 * replaced by a new code
92 .LDONE1: R4 = R7 << 3;
95 SSYNC; /* SSYNC required writing to IMEM_CONTROL. */
110 .LDONE2: R4 = R7 << 3;
113 SSYNC; /* SSYNC required writing to IMEM_CONTROL. */
127 .LDONE3: R4 = R7 << 3;
130 SSYNC; /* SSYNC required writing to IMEM_CONTROL. */
145 .LDONE4: R4 = R7 << 3;
148 SSYNC; /* SSYNC required writing to IMEM_CONTROL. */
155 ( R7:0,P5:0 ) = [SP++];
158 ENDPROC(_cache_grab_lock)
160 /* After the execution of critical code, the code is now locked into
161 * the cache way. Now we need to set ILOC.
163 * R0 - Which way to be locked
168 [--SP]=( R7:0,P5:0 );
170 P1.H = HI(IMEM_CONTROL);
171 P1.L = LO(IMEM_CONTROL);
173 /* Disable the Interrupts*/
181 SSYNC; /* SSYNC required writing to IMEM_CONTROL. */
185 /* Renable the Interrupts */
188 ( R7:0,P5:0 ) = [SP++];
192 #endif /* BLKFIN_CACHE_LOCK */
194 /* Return the ILOC bits of IMEM_CONTROL
198 P1.H = HI(IMEM_CONTROL);
199 P1.L = LO(IMEM_CONTROL);