2 * Blackfin power management
4 * Copyright 2006-2009 Analog Devices Inc.
6 * Licensed under the GPL-2
7 * based on arm/mach-omap/pm.c
8 * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
11 #include <linux/suspend.h>
12 #include <linux/sched.h>
13 #include <linux/proc_fs.h>
15 #include <linux/irq.h>
22 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
23 #define WAKEUP_TYPE PM_WAKE_HIGH
26 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_L
27 #define WAKEUP_TYPE PM_WAKE_LOW
30 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_F
31 #define WAKEUP_TYPE PM_WAKE_FALLING
34 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_R
35 #define WAKEUP_TYPE PM_WAKE_RISING
38 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_B
39 #define WAKEUP_TYPE PM_WAKE_BOTH_EDGES
43 void bfin_pm_suspend_standby_enter(void)
47 #ifdef CONFIG_PM_WAKEUP_BY_GPIO
48 gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
51 local_irq_save_hw(flags);
52 bfin_pm_standby_setup();
54 #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
55 sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
57 sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
60 bfin_pm_standby_restore();
63 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
65 /* BF52x system reset does not properly reset SIC_IWR1 which
66 * will screw up the bootrom as it relies on MDMA0/1 waking it
67 * up from IDLE instructions. See this report for more info:
68 * http://blackfin.uclinux.org/gf/tracker/4323
71 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
73 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
76 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
79 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
82 local_irq_restore_hw(flags);
85 int bf53x_suspend_l1_mem(unsigned char *memptr)
87 dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH);
88 dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START,
90 dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
91 (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
92 memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
93 L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
99 int bf53x_resume_l1_mem(unsigned char *memptr)
101 dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
102 dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
104 dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
105 L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
106 memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
107 L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
112 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
113 static void flushinv_all_dcache(void)
115 u32 way, bank, subbank, set;
117 u32 dmem_ctl = bfin_read_DMEM_CONTROL();
119 for (bank = 0; bank < 2; ++bank) {
120 if (!(dmem_ctl & (1 << (DMC1_P - bank))))
123 for (way = 0; way < 2; ++way)
124 for (subbank = 0; subbank < 4; ++subbank)
125 for (set = 0; set < 64; ++set) {
127 bfin_write_DTEST_COMMAND(
134 status = bfin_read_DTEST_DATA0();
136 /* only worry about valid/dirty entries */
137 if ((status & 0x3) != 0x3)
140 /* construct the address using the tag */
141 addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
144 __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
150 int bfin_pm_suspend_mem_enter(void)
155 unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
156 + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
159 if (memptr == NULL) {
160 panic("bf53x_suspend_l1_mem malloc failed");
164 wakeup = bfin_read_VR_CTL() & ~FREQ;
167 #ifdef CONFIG_PM_BFIN_WAKE_PH6
170 #ifdef CONFIG_PM_BFIN_WAKE_GP
174 local_irq_save_hw(flags);
176 ret = blackfin_dma_suspend();
179 local_irq_restore_hw(flags);
184 bfin_gpio_pm_hibernate_suspend();
186 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
187 flushinv_all_dcache();
191 bf53x_suspend_l1_mem(memptr);
193 do_hibernate(wakeup | vr_wakeup); /* Goodbye */
195 bf53x_resume_l1_mem(memptr);
200 bfin_gpio_pm_hibernate_restore();
201 blackfin_dma_resume();
203 local_irq_restore_hw(flags);
210 * bfin_pm_valid - Tell the PM core that we only support the standby sleep
212 * @state: suspend state we're checking.
215 static int bfin_pm_valid(suspend_state_t state)
217 return (state == PM_SUSPEND_STANDBY
218 #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
221 * If we enter Hibernate the SCKE Pin is driven Low,
222 * so that the SDRAM enters Self Refresh Mode.
223 * However when the reset sequence that follows hibernate
224 * state is executed, SCKE is driven High, taking the
225 * SDRAM out of Self Refresh.
227 * If you reconfigure and access the SDRAM "very quickly",
228 * you are likely to avoid errors, otherwise the SDRAM
229 * start losing its contents.
230 * An external HW workaround is possible using logic gates.
232 || state == PM_SUSPEND_MEM
238 * bfin_pm_enter - Actually enter a sleep state.
239 * @state: State we're entering.
242 static int bfin_pm_enter(suspend_state_t state)
245 case PM_SUSPEND_STANDBY:
246 bfin_pm_suspend_standby_enter();
249 bfin_pm_suspend_mem_enter();
258 struct platform_suspend_ops bfin_pm_ops = {
259 .enter = bfin_pm_enter,
260 .valid = bfin_pm_valid,
263 static int __init bfin_pm_init(void)
265 suspend_set_ops(&bfin_pm_ops);
269 __initcall(bfin_pm_init);