2 * Blackfin power management
4 * Copyright 2006-2009 Analog Devices Inc.
6 * Licensed under the GPL-2
7 * based on arm/mach-omap/pm.c
8 * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
11 #include <linux/suspend.h>
12 #include <linux/sched.h>
13 #include <linux/proc_fs.h>
14 #include <linux/slab.h>
16 #include <linux/irq.h>
17 #include <linux/delay.h>
26 struct bfin_cpu_pm_fns *bfin_cpu_pm;
29 void bfin_pm_suspend_standby_enter(void)
32 bfin_pm_standby_setup();
36 bfin_cpu_pm->enter(PM_SUSPEND_STANDBY);
38 # ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
39 sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
41 sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
46 bfin_pm_standby_restore();
51 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
53 /* BF52x system reset does not properly reset SIC_IWR1 which
54 * will screw up the bootrom as it relies on MDMA0/1 waking it
55 * up from IDLE instructions. See this report for more info:
56 * http://blackfin.uclinux.org/gf/tracker/4323
59 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
61 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
64 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
67 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
73 int bf53x_suspend_l1_mem(unsigned char *memptr)
75 dma_memcpy_nocache(memptr, (const void *) L1_CODE_START,
77 dma_memcpy_nocache(memptr + L1_CODE_LENGTH,
78 (const void *) L1_DATA_A_START, L1_DATA_A_LENGTH);
79 dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
80 (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
81 memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
82 L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
88 int bf53x_resume_l1_mem(unsigned char *memptr)
90 dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
91 dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
93 dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
94 L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
95 memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
96 L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
101 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
103 __attribute__((l1_text))
105 static void flushinv_all_dcache(void)
107 register u32 way, bank, subbank, set;
108 register u32 status, addr;
109 u32 dmem_ctl = bfin_read_DMEM_CONTROL();
111 for (bank = 0; bank < 2; ++bank) {
112 if (!(dmem_ctl & (1 << (DMC1_P - bank))))
115 for (way = 0; way < 2; ++way)
116 for (subbank = 0; subbank < 4; ++subbank)
117 for (set = 0; set < 64; ++set) {
119 bfin_write_DTEST_COMMAND(
126 status = bfin_read_DTEST_DATA0();
128 /* only worry about valid/dirty entries */
129 if ((status & 0x3) != 0x3)
133 /* construct the address using the tag */
134 addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
137 __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
143 int bfin_pm_suspend_mem_enter(void)
150 unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
151 + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
154 if (memptr == NULL) {
155 panic("bf53x_suspend_l1_mem malloc failed");
160 wakeup = bfin_read_VR_CTL() & ~FREQ;
163 #ifdef CONFIG_PM_BFIN_WAKE_PH6
166 #ifdef CONFIG_PM_BFIN_WAKE_GP
171 ret = blackfin_dma_suspend();
178 #ifdef CONFIG_GPIO_ADI
179 bfin_gpio_pm_hibernate_suspend();
182 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
183 flushinv_all_dcache();
188 bf53x_suspend_l1_mem(memptr);
191 do_hibernate(wakeup | vr_wakeup); /* See you later! */
193 bfin_cpu_pm->enter(PM_SUSPEND_MEM);
196 bf53x_resume_l1_mem(memptr);
201 #ifdef CONFIG_GPIO_ADI
202 bfin_gpio_pm_hibernate_restore();
204 blackfin_dma_resume();
212 * bfin_pm_valid - Tell the PM core that we only support the standby sleep
214 * @state: suspend state we're checking.
217 static int bfin_pm_valid(suspend_state_t state)
219 return (state == PM_SUSPEND_STANDBY
220 #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
223 * If we enter Hibernate the SCKE Pin is driven Low,
224 * so that the SDRAM enters Self Refresh Mode.
225 * However when the reset sequence that follows hibernate
226 * state is executed, SCKE is driven High, taking the
227 * SDRAM out of Self Refresh.
229 * If you reconfigure and access the SDRAM "very quickly",
230 * you are likely to avoid errors, otherwise the SDRAM
231 * start losing its contents.
232 * An external HW workaround is possible using logic gates.
234 || state == PM_SUSPEND_MEM
240 * bfin_pm_enter - Actually enter a sleep state.
241 * @state: State we're entering.
244 static int bfin_pm_enter(suspend_state_t state)
247 case PM_SUSPEND_STANDBY:
248 bfin_pm_suspend_standby_enter();
251 bfin_pm_suspend_mem_enter();
260 #ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
261 void bfin_pm_end(void)
267 __asm__ __volatile__ (
273 : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC"
276 usec64 = ((u64)cycle2 << 32) + cycle;
277 do_div(usec64, get_cclk() / USEC_PER_SEC);
282 pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n",
283 usec / USEC_PER_MSEC, usec % USEC_PER_MSEC);
287 static const struct platform_suspend_ops bfin_pm_ops = {
288 .enter = bfin_pm_enter,
289 .valid = bfin_pm_valid,
290 #ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
295 static int __init bfin_pm_init(void)
297 suspend_set_ops(&bfin_pm_ops);
301 __initcall(bfin_pm_init);