2 * Blackfin power management
4 * Copyright 2006-2009 Analog Devices Inc.
6 * Licensed under the GPL-2
7 * based on arm/mach-omap/pm.c
8 * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
11 #include <linux/suspend.h>
12 #include <linux/sched.h>
13 #include <linux/proc_fs.h>
14 #include <linux/slab.h>
16 #include <linux/irq.h>
25 struct bfin_cpu_pm_fns *bfin_cpu_pm;
28 void bfin_pm_suspend_standby_enter(void)
31 bfin_pm_standby_setup();
35 bfin_cpu_pm->enter(PM_SUSPEND_STANDBY);
37 # ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
38 sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
40 sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
45 bfin_pm_standby_restore();
50 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
52 /* BF52x system reset does not properly reset SIC_IWR1 which
53 * will screw up the bootrom as it relies on MDMA0/1 waking it
54 * up from IDLE instructions. See this report for more info:
55 * http://blackfin.uclinux.org/gf/tracker/4323
58 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
60 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
63 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
66 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
72 int bf53x_suspend_l1_mem(unsigned char *memptr)
74 dma_memcpy_nocache(memptr, (const void *) L1_CODE_START,
76 dma_memcpy_nocache(memptr + L1_CODE_LENGTH,
77 (const void *) L1_DATA_A_START, L1_DATA_A_LENGTH);
78 dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
79 (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
80 memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
81 L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
87 int bf53x_resume_l1_mem(unsigned char *memptr)
89 dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
90 dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
92 dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
93 L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
94 memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
95 L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
100 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
102 __attribute__((l1_text))
104 static void flushinv_all_dcache(void)
106 register u32 way, bank, subbank, set;
107 register u32 status, addr;
108 u32 dmem_ctl = bfin_read_DMEM_CONTROL();
110 for (bank = 0; bank < 2; ++bank) {
111 if (!(dmem_ctl & (1 << (DMC1_P - bank))))
114 for (way = 0; way < 2; ++way)
115 for (subbank = 0; subbank < 4; ++subbank)
116 for (set = 0; set < 64; ++set) {
118 bfin_write_DTEST_COMMAND(
125 status = bfin_read_DTEST_DATA0();
127 /* only worry about valid/dirty entries */
128 if ((status & 0x3) != 0x3)
131 /* construct the address using the tag */
132 addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
135 __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
141 int bfin_pm_suspend_mem_enter(void)
145 unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
146 + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
149 if (memptr == NULL) {
150 panic("bf53x_suspend_l1_mem malloc failed");
155 wakeup = bfin_read_VR_CTL() & ~FREQ;
158 #ifdef CONFIG_PM_BFIN_WAKE_PH6
161 #ifdef CONFIG_PM_BFIN_WAKE_GP
166 ret = blackfin_dma_suspend();
173 bfin_gpio_pm_hibernate_suspend();
175 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
176 flushinv_all_dcache();
180 bf53x_suspend_l1_mem(memptr);
183 do_hibernate(wakeup | vr_wakeup); /* See you later! */
185 bfin_cpu_pm->enter(PM_SUSPEND_MEM);
188 bf53x_resume_l1_mem(memptr);
193 bfin_gpio_pm_hibernate_restore();
194 blackfin_dma_resume();
202 * bfin_pm_valid - Tell the PM core that we only support the standby sleep
204 * @state: suspend state we're checking.
207 static int bfin_pm_valid(suspend_state_t state)
209 return (state == PM_SUSPEND_STANDBY
210 #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
213 * If we enter Hibernate the SCKE Pin is driven Low,
214 * so that the SDRAM enters Self Refresh Mode.
215 * However when the reset sequence that follows hibernate
216 * state is executed, SCKE is driven High, taking the
217 * SDRAM out of Self Refresh.
219 * If you reconfigure and access the SDRAM "very quickly",
220 * you are likely to avoid errors, otherwise the SDRAM
221 * start losing its contents.
222 * An external HW workaround is possible using logic gates.
224 || state == PM_SUSPEND_MEM
230 * bfin_pm_enter - Actually enter a sleep state.
231 * @state: State we're entering.
234 static int bfin_pm_enter(suspend_state_t state)
237 case PM_SUSPEND_STANDBY:
238 bfin_pm_suspend_standby_enter();
241 bfin_pm_suspend_mem_enter();
250 #ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
251 void bfin_pm_end(void)
257 __asm__ __volatile__ (
263 : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC"
266 usec64 = ((u64)cycle2 << 32) + cycle;
267 do_div(usec64, get_cclk() / USEC_PER_SEC);
272 pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n",
273 usec / USEC_PER_MSEC, usec % USEC_PER_MSEC);
277 static const struct platform_suspend_ops bfin_pm_ops = {
278 .enter = bfin_pm_enter,
279 .valid = bfin_pm_valid,
280 #ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
285 static int __init bfin_pm_init(void)
287 suspend_set_ops(&bfin_pm_ops);
291 __initcall(bfin_pm_init);