2 * Copyright (C) 2010, 2011 Texas Instruments Incorporated
3 * Contributed by: Mark Salter (msalter@redhat.com)
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clockchips.h>
11 #include <linux/interrupt.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_address.h>
18 #include <asm/timer64.h>
34 static struct timer_regs __iomem *timer;
36 #define TCR_TSTATLO 0x001
37 #define TCR_INVOUTPLO 0x002
38 #define TCR_INVINPLO 0x004
39 #define TCR_CPLO 0x008
40 #define TCR_ENAMODELO_ONCE 0x040
41 #define TCR_ENAMODELO_CONT 0x080
42 #define TCR_ENAMODELO_MASK 0x0c0
43 #define TCR_PWIDLO_MASK 0x030
44 #define TCR_CLKSRCLO 0x100
45 #define TCR_TIENLO 0x200
46 #define TCR_TSTATHI (0x001 << 16)
47 #define TCR_INVOUTPHI (0x002 << 16)
48 #define TCR_CPHI (0x008 << 16)
49 #define TCR_PWIDHI_MASK (0x030 << 16)
50 #define TCR_ENAMODEHI_ONCE (0x040 << 16)
51 #define TCR_ENAMODEHI_CONT (0x080 << 16)
52 #define TCR_ENAMODEHI_MASK (0x0c0 << 16)
54 #define TGCR_TIMLORS 0x001
55 #define TGCR_TIMHIRS 0x002
56 #define TGCR_TIMMODE_UD32 0x004
57 #define TGCR_TIMMODE_WDT64 0x008
58 #define TGCR_TIMMODE_CD32 0x00c
59 #define TGCR_TIMMODE_MASK 0x00c
60 #define TGCR_PSCHI_MASK (0x00f << 8)
61 #define TGCR_TDDRHI_MASK (0x00f << 12)
64 * Timer clocks are divided down from the CPU clock
65 * The divisor is in the EMUMGTCLKSPD register
67 #define TIMER_DIVISOR \
68 ((soc_readl(&timer->emumgt) & (0xf << 16)) >> 16)
70 #define TIMER64_RATE (c6x_core_freq / TIMER_DIVISOR)
72 #define TIMER64_MODE_DISABLED 0
73 #define TIMER64_MODE_ONE_SHOT TCR_ENAMODELO_ONCE
74 #define TIMER64_MODE_PERIODIC TCR_ENAMODELO_CONT
76 static int timer64_mode;
77 static int timer64_devstate_id = -1;
79 static void timer64_config(unsigned long period)
81 u32 tcr = soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK;
83 soc_writel(tcr, &timer->tcr);
84 soc_writel(period - 1, &timer->prdlo);
85 soc_writel(0, &timer->cntlo);
87 soc_writel(tcr, &timer->tcr);
90 static void timer64_enable(void)
94 if (timer64_devstate_id >= 0)
95 dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
97 /* disable timer, reset count */
98 soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
99 soc_writel(0, &timer->prdlo);
101 /* use internal clock and 1 cycle pulse width */
102 val = soc_readl(&timer->tcr);
103 soc_writel(val & ~(TCR_CLKSRCLO | TCR_PWIDLO_MASK), &timer->tcr);
105 /* dual 32-bit unchained mode */
106 val = soc_readl(&timer->tgcr) & ~TGCR_TIMMODE_MASK;
107 soc_writel(val, &timer->tgcr);
108 soc_writel(val | (TGCR_TIMLORS | TGCR_TIMMODE_UD32), &timer->tgcr);
111 static void timer64_disable(void)
113 /* disable timer, reset count */
114 soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
115 soc_writel(0, &timer->prdlo);
117 if (timer64_devstate_id >= 0)
118 dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_DISABLED);
121 static int next_event(unsigned long delta,
122 struct clock_event_device *evt)
124 timer64_config(delta);
128 static void set_clock_mode(enum clock_event_mode mode,
129 struct clock_event_device *evt)
132 case CLOCK_EVT_MODE_PERIODIC:
134 timer64_mode = TIMER64_MODE_PERIODIC;
135 timer64_config(TIMER64_RATE / HZ);
137 case CLOCK_EVT_MODE_ONESHOT:
139 timer64_mode = TIMER64_MODE_ONE_SHOT;
141 case CLOCK_EVT_MODE_UNUSED:
142 case CLOCK_EVT_MODE_SHUTDOWN:
143 timer64_mode = TIMER64_MODE_DISABLED;
146 case CLOCK_EVT_MODE_RESUME:
151 static struct clock_event_device t64_clockevent_device = {
152 .name = "TIMER64_EVT32_TIMER",
153 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
155 .set_mode = set_clock_mode,
156 .set_next_event = next_event,
159 static irqreturn_t timer_interrupt(int irq, void *dev_id)
161 struct clock_event_device *cd = &t64_clockevent_device;
163 cd->event_handler(cd);
168 static struct irqaction timer_iact = {
171 .handler = timer_interrupt,
172 .dev_id = &t64_clockevent_device,
175 void __init timer64_init(void)
177 struct clock_event_device *cd = &t64_clockevent_device;
178 struct device_node *np, *first = NULL;
182 for_each_compatible_node(np, NULL, "ti,c64x+timer64") {
183 err = of_property_read_u32(np, "ti,core-mask", &val);
185 if (val & (1 << get_coreid())) {
193 /* try first one with no core-mask */
195 np = of_node_get(first);
197 pr_debug("Cannot find ti,c64x+timer64 timer.\n");
202 timer = of_iomap(np, 0);
204 pr_debug("%s: Cannot map timer registers.\n", np->full_name);
207 pr_debug("%s: Timer registers=%p.\n", np->full_name, timer);
209 cd->irq = irq_of_parse_and_map(np, 0);
210 if (cd->irq == NO_IRQ) {
211 pr_debug("%s: Cannot find interrupt.\n", np->full_name);
216 /* If there is a device state control, save the ID. */
217 err = of_property_read_u32(np, "ti,dscr-dev-enable", &val);
219 timer64_devstate_id = val;
222 * It is necessary to enable the timer block here because
223 * the TIMER_DIVISOR macro needs to read a timer register
224 * to get the divisor.
226 dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
229 pr_debug("%s: Timer irq=%d.\n", np->full_name, cd->irq);
231 clockevents_calc_mult_shift(cd, c6x_core_freq / TIMER_DIVISOR, 5);
233 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
234 cd->min_delta_ns = clockevent_delta2ns(250, cd);
236 cd->cpumask = cpumask_of(smp_processor_id());
238 clockevents_register_device(cd);
239 setup_irq(cd->irq, &timer_iact);