1 #include <linux/init.h>
2 #include <linux/module.h>
3 #include <linux/cpufreq.h>
4 #include <hwregs/reg_map.h>
5 #include <hwregs/reg_rdwr.h>
6 #include <hwregs/clkgen_defs.h>
7 #include <hwregs/ddr2_defs.h>
10 cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
13 static struct notifier_block cris_sdram_freq_notifier_block = {
14 .notifier_call = cris_sdram_freq_notifier
17 static struct cpufreq_frequency_table cris_freq_table[] = {
20 {0, CPUFREQ_TABLE_END},
23 static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
25 reg_clkgen_rw_clk_ctrl clk_ctrl;
26 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
27 return clk_ctrl.pll ? 200000 : 6000;
30 static void cris_freq_set_cpu_state(unsigned int state)
33 struct cpufreq_freqs freqs;
34 reg_clkgen_rw_clk_ctrl clk_ctrl;
35 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
38 for_each_present_cpu(i)
41 freqs.old = cris_freq_get_cpu_frequency(i);
42 freqs.new = cris_freq_table[state].frequency;
46 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
50 /* Even though we may be SMP they will share the same clock
51 * so all settings are made on CPU0. */
52 if (cris_freq_table[state].frequency == 200000)
56 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
60 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
63 static int cris_freq_verify(struct cpufreq_policy *policy)
65 return cpufreq_frequency_table_verify(policy, &cris_freq_table[0]);
68 static int cris_freq_target(struct cpufreq_policy *policy,
69 unsigned int target_freq,
70 unsigned int relation)
72 unsigned int newstate = 0;
74 if (cpufreq_frequency_table_target(policy, cris_freq_table,
75 target_freq, relation, &newstate))
78 cris_freq_set_cpu_state(newstate);
83 static int cris_freq_cpu_init(struct cpufreq_policy *policy)
87 /* cpuinfo and default policy values */
88 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
89 policy->cpuinfo.transition_latency = 1000000; /* 1ms */
90 policy->cur = cris_freq_get_cpu_frequency(0);
92 result = cpufreq_frequency_table_cpuinfo(policy, cris_freq_table);
96 cpufreq_frequency_table_get_attr(cris_freq_table, policy->cpu);
102 static int cris_freq_cpu_exit(struct cpufreq_policy *policy)
104 cpufreq_frequency_table_put_attr(policy->cpu);
109 static struct freq_attr *cris_freq_attr[] = {
110 &cpufreq_freq_attr_scaling_available_freqs,
114 static struct cpufreq_driver cris_freq_driver = {
115 .get = cris_freq_get_cpu_frequency,
116 .verify = cris_freq_verify,
117 .target = cris_freq_target,
118 .init = cris_freq_cpu_init,
119 .exit = cris_freq_cpu_exit,
121 .owner = THIS_MODULE,
122 .attr = cris_freq_attr,
125 static int __init cris_freq_init(void)
128 ret = cpufreq_register_driver(&cris_freq_driver);
129 cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
130 CPUFREQ_TRANSITION_NOTIFIER);
135 cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
139 struct cpufreq_freqs *freqs = data;
140 if (val == CPUFREQ_PRECHANGE) {
141 reg_ddr2_rw_cfg cfg =
142 REG_RD(ddr2, regi_ddr2_ctrl, rw_cfg);
143 cfg.ref_interval = (freqs->new == 200000 ? 1560 : 46);
145 if (freqs->new == 200000)
146 for (i = 0; i < 50000; i++);
147 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
153 module_init(cris_freq_init);