1 #ifndef __extmem_defs_h
2 #define __extmem_defs_h
5 * This file is autogenerated from
6 * file: ../../inst/ext_mem/mod/extmem_regs.r
7 * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp
8 * last modfied: Tue Mar 30 22:26:21 2004
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r
11 * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $
12 * Any changes here will be lost.
14 * -*- buffer-read-only: t -*-
16 /* Main access macros */
18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
53 #ifndef REG_RD_INT_VECT
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
66 #define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
71 #define reg_page_size 8192
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
85 /* C-code for register scope extmem */
87 /* Register rw_cse0_cfg, scope extmem, type rw */
96 unsigned int mode : 1;
97 unsigned int erc_en : 1;
98 unsigned int dummy1 : 6;
99 unsigned int size : 3;
100 unsigned int log : 1;
102 } reg_extmem_rw_cse0_cfg;
103 #define REG_RD_ADDR_extmem_rw_cse0_cfg 0
104 #define REG_WR_ADDR_extmem_rw_cse0_cfg 0
106 /* Register rw_cse1_cfg, scope extmem, type rw */
113 unsigned int ewb : 2;
115 unsigned int mode : 1;
116 unsigned int erc_en : 1;
117 unsigned int dummy1 : 6;
118 unsigned int size : 3;
119 unsigned int log : 1;
121 } reg_extmem_rw_cse1_cfg;
122 #define REG_RD_ADDR_extmem_rw_cse1_cfg 4
123 #define REG_WR_ADDR_extmem_rw_cse1_cfg 4
125 /* Register rw_csr0_cfg, scope extmem, type rw */
132 unsigned int ewb : 2;
134 unsigned int mode : 1;
135 unsigned int erc_en : 1;
136 unsigned int dummy1 : 6;
137 unsigned int size : 3;
138 unsigned int log : 1;
140 } reg_extmem_rw_csr0_cfg;
141 #define REG_RD_ADDR_extmem_rw_csr0_cfg 8
142 #define REG_WR_ADDR_extmem_rw_csr0_cfg 8
144 /* Register rw_csr1_cfg, scope extmem, type rw */
151 unsigned int ewb : 2;
153 unsigned int mode : 1;
154 unsigned int erc_en : 1;
155 unsigned int dummy1 : 6;
156 unsigned int size : 3;
157 unsigned int log : 1;
159 } reg_extmem_rw_csr1_cfg;
160 #define REG_RD_ADDR_extmem_rw_csr1_cfg 12
161 #define REG_WR_ADDR_extmem_rw_csr1_cfg 12
163 /* Register rw_csp0_cfg, scope extmem, type rw */
170 unsigned int ewb : 2;
172 unsigned int mode : 1;
173 unsigned int erc_en : 1;
174 unsigned int dummy1 : 6;
175 unsigned int size : 3;
176 unsigned int log : 1;
178 } reg_extmem_rw_csp0_cfg;
179 #define REG_RD_ADDR_extmem_rw_csp0_cfg 16
180 #define REG_WR_ADDR_extmem_rw_csp0_cfg 16
182 /* Register rw_csp1_cfg, scope extmem, type rw */
189 unsigned int ewb : 2;
191 unsigned int mode : 1;
192 unsigned int erc_en : 1;
193 unsigned int dummy1 : 6;
194 unsigned int size : 3;
195 unsigned int log : 1;
197 } reg_extmem_rw_csp1_cfg;
198 #define REG_RD_ADDR_extmem_rw_csp1_cfg 20
199 #define REG_WR_ADDR_extmem_rw_csp1_cfg 20
201 /* Register rw_csp2_cfg, scope extmem, type rw */
208 unsigned int ewb : 2;
210 unsigned int mode : 1;
211 unsigned int erc_en : 1;
212 unsigned int dummy1 : 6;
213 unsigned int size : 3;
214 unsigned int log : 1;
216 } reg_extmem_rw_csp2_cfg;
217 #define REG_RD_ADDR_extmem_rw_csp2_cfg 24
218 #define REG_WR_ADDR_extmem_rw_csp2_cfg 24
220 /* Register rw_csp3_cfg, scope extmem, type rw */
227 unsigned int ewb : 2;
229 unsigned int mode : 1;
230 unsigned int erc_en : 1;
231 unsigned int dummy1 : 6;
232 unsigned int size : 3;
233 unsigned int log : 1;
235 } reg_extmem_rw_csp3_cfg;
236 #define REG_RD_ADDR_extmem_rw_csp3_cfg 28
237 #define REG_WR_ADDR_extmem_rw_csp3_cfg 28
239 /* Register rw_csp4_cfg, scope extmem, type rw */
246 unsigned int ewb : 2;
248 unsigned int mode : 1;
249 unsigned int erc_en : 1;
250 unsigned int dummy1 : 6;
251 unsigned int size : 3;
252 unsigned int log : 1;
254 } reg_extmem_rw_csp4_cfg;
255 #define REG_RD_ADDR_extmem_rw_csp4_cfg 32
256 #define REG_WR_ADDR_extmem_rw_csp4_cfg 32
258 /* Register rw_csp5_cfg, scope extmem, type rw */
265 unsigned int ewb : 2;
267 unsigned int mode : 1;
268 unsigned int erc_en : 1;
269 unsigned int dummy1 : 6;
270 unsigned int size : 3;
271 unsigned int log : 1;
273 } reg_extmem_rw_csp5_cfg;
274 #define REG_RD_ADDR_extmem_rw_csp5_cfg 36
275 #define REG_WR_ADDR_extmem_rw_csp5_cfg 36
277 /* Register rw_csp6_cfg, scope extmem, type rw */
284 unsigned int ewb : 2;
286 unsigned int mode : 1;
287 unsigned int erc_en : 1;
288 unsigned int dummy1 : 6;
289 unsigned int size : 3;
290 unsigned int log : 1;
292 } reg_extmem_rw_csp6_cfg;
293 #define REG_RD_ADDR_extmem_rw_csp6_cfg 40
294 #define REG_WR_ADDR_extmem_rw_csp6_cfg 40
296 /* Register rw_css_cfg, scope extmem, type rw */
303 unsigned int ewb : 2;
305 unsigned int mode : 1;
306 unsigned int erc_en : 1;
307 unsigned int dummy1 : 6;
308 unsigned int size : 3;
309 unsigned int log : 1;
311 } reg_extmem_rw_css_cfg;
312 #define REG_RD_ADDR_extmem_rw_css_cfg 44
313 #define REG_WR_ADDR_extmem_rw_css_cfg 44
315 /* Register rw_status_handle, scope extmem, type rw */
318 } reg_extmem_rw_status_handle;
319 #define REG_RD_ADDR_extmem_rw_status_handle 48
320 #define REG_WR_ADDR_extmem_rw_status_handle 48
322 /* Register rw_wait_pin, scope extmem, type rw */
324 unsigned int val : 16;
325 unsigned int dummy1 : 15;
326 unsigned int start : 1;
327 } reg_extmem_rw_wait_pin;
328 #define REG_RD_ADDR_extmem_rw_wait_pin 52
329 #define REG_WR_ADDR_extmem_rw_wait_pin 52
331 /* Register rw_gated_csp, scope extmem, type rw */
333 unsigned int dummy1 : 31;
335 } reg_extmem_rw_gated_csp;
336 #define REG_RD_ADDR_extmem_rw_gated_csp 56
337 #define REG_WR_ADDR_extmem_rw_gated_csp 56
342 regk_extmem_b16 = 0x00000001,
343 regk_extmem_b32 = 0x00000000,
344 regk_extmem_bwe = 0x00000000,
345 regk_extmem_cwe = 0x00000001,
346 regk_extmem_no = 0x00000000,
347 regk_extmem_rw_cse0_cfg_default = 0x000006cf,
348 regk_extmem_rw_cse1_cfg_default = 0x000006cf,
349 regk_extmem_rw_csp0_cfg_default = 0x000006cf,
350 regk_extmem_rw_csp1_cfg_default = 0x000006cf,
351 regk_extmem_rw_csp2_cfg_default = 0x000006cf,
352 regk_extmem_rw_csp3_cfg_default = 0x000006cf,
353 regk_extmem_rw_csp4_cfg_default = 0x000006cf,
354 regk_extmem_rw_csp5_cfg_default = 0x000006cf,
355 regk_extmem_rw_csp6_cfg_default = 0x000006cf,
356 regk_extmem_rw_csr0_cfg_default = 0x000006cf,
357 regk_extmem_rw_csr1_cfg_default = 0x000006cf,
358 regk_extmem_rw_css_cfg_default = 0x000006cf,
359 regk_extmem_s128KB = 0x00000000,
360 regk_extmem_s16MB = 0x00000005,
361 regk_extmem_s1MB = 0x00000001,
362 regk_extmem_s2MB = 0x00000002,
363 regk_extmem_s32MB = 0x00000006,
364 regk_extmem_s4MB = 0x00000003,
365 regk_extmem_s64MB = 0x00000007,
366 regk_extmem_s8MB = 0x00000004,
367 regk_extmem_yes = 0x00000001
369 #endif /* __extmem_defs_h */