2 #include <asm/spr-regs.h>
6 #ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
9 #define ATOMIC_EXPORT(x) EXPORT_SYMBOL(x)
11 #else /* !OUTOFLINE && LIB */
13 #define ATOMIC_OP_RETURN(op)
14 #define ATOMIC_FETCH_OP(op)
16 #endif /* OUTOFLINE */
18 #else /* !__ATOMIC_LIB__ */
20 #define ATOMIC_EXPORT(x)
22 #ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
24 #define ATOMIC_OP_RETURN(op) \
25 extern int __atomic_##op##_return(int i, int *v); \
26 extern long long __atomic64_##op##_return(long long i, long long *v);
28 #define ATOMIC_FETCH_OP(op) \
29 extern int __atomic32_fetch_##op(int i, int *v); \
30 extern long long __atomic64_fetch_##op(long long i, long long *v);
32 #else /* !OUTOFLINE && !LIB */
34 #define ATOMIC_QUALS static inline
36 #endif /* OUTOFLINE */
37 #endif /* __ATOMIC_LIB__ */
41 * Note on the 64 bit inline asm variants...
43 * CSTD is a conditional instruction and needs a constrained memory reference.
44 * Normally 'U' provides the correct constraints for conditional instructions
45 * and this is used for the 32 bit version, however 'U' does not appear to work
46 * for 64 bit values (gcc-4.9)
48 * The exact constraint is that conditional instructions cannot deal with an
49 * immediate displacement in the memory reference, so what we do is we read the
50 * address through a volatile cast into a local variable in order to insure we
51 * _have_ to compute the correct address without displacement. This allows us
52 * to use the regular 'm' for the memory address.
54 * Furthermore, the %Ln operand, which prints the low word register (r+1),
55 * really only works for registers, this means we cannot allow immediate values
56 * for the 64 bit versions -- like we do for the 32 bit ones.
60 #ifndef ATOMIC_OP_RETURN
61 #define ATOMIC_OP_RETURN(op) \
62 ATOMIC_QUALS int __atomic_##op##_return(int i, int *v) \
68 " orcc gr0,gr0,gr0,icc3 \n" \
71 " orcr cc7,cc7,cc3 \n" \
72 " "#op"%I2 %1,%2,%1 \n" \
73 " cst.p %1,%M0 ,cc3,#1 \n" \
74 " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
75 " beq icc3,#0,0b \n" \
76 : "+U"(*v), "=&r"(val) \
78 : "memory", "cc7", "cc3", "icc3" \
83 ATOMIC_EXPORT(__atomic_##op##_return); \
85 ATOMIC_QUALS long long __atomic64_##op##_return(long long i, long long *v) \
87 long long *__v = READ_ONCE(v); \
92 " orcc gr0,gr0,gr0,icc3 \n" \
95 " orcr cc7,cc7,cc3 \n" \
96 " "#op"cc %L1,%L2,%L1,icc0 \n" \
97 " "#op"x %1,%2,%1,icc0 \n" \
98 " cstd.p %1,%M0 ,cc3,#1 \n" \
99 " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
100 " beq icc3,#0,0b \n" \
101 : "+m"(*__v), "=&e"(val) \
103 : "memory", "cc7", "cc3", "icc0", "icc3" \
108 ATOMIC_EXPORT(__atomic64_##op##_return);
111 #ifndef ATOMIC_FETCH_OP
112 #define ATOMIC_FETCH_OP(op) \
113 ATOMIC_QUALS int __atomic32_fetch_##op(int i, int *v) \
119 " orcc gr0,gr0,gr0,icc3 \n" \
120 " ckeq icc3,cc7 \n" \
122 " orcr cc7,cc7,cc3 \n" \
123 " "#op"%I3 %1,%3,%2 \n" \
124 " cst.p %2,%M0 ,cc3,#1 \n" \
125 " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
126 " beq icc3,#0,0b \n" \
127 : "+U"(*v), "=&r"(old), "=r"(tmp) \
129 : "memory", "cc7", "cc3", "icc3" \
134 ATOMIC_EXPORT(__atomic32_fetch_##op); \
136 ATOMIC_QUALS long long __atomic64_fetch_##op(long long i, long long *v) \
138 long long *__v = READ_ONCE(v); \
139 long long old, tmp; \
143 " orcc gr0,gr0,gr0,icc3 \n" \
144 " ckeq icc3,cc7 \n" \
146 " orcr cc7,cc7,cc3 \n" \
147 " "#op" %L1,%L3,%L2 \n" \
148 " "#op" %1,%3,%2 \n" \
149 " cstd.p %2,%M0 ,cc3,#1 \n" \
150 " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
151 " beq icc3,#0,0b \n" \
152 : "+m"(*__v), "=&e"(old), "=e"(tmp) \
154 : "memory", "cc7", "cc3", "icc3" \
159 ATOMIC_EXPORT(__atomic64_fetch_##op);
168 ATOMIC_OP_RETURN(add)
169 ATOMIC_OP_RETURN(sub)
171 #undef ATOMIC_FETCH_OP
172 #undef ATOMIC_OP_RETURN