arch/h8300/boot/dts/h8s_sim.dts

   1 /dts-v1/;
   2 / {
   3         compatible = "gnu,gdbsim";
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         interrupt-parent = <&h8intc>;
   7
   8         chosen {
   9                 bootargs = "earlyprintk=h8300-sim";
  10                 stdout-path = <&sci0>;
  11         };
  12         aliases {
  13                 serial0 = &sci0;
  14                 serial1 = &sci1;
  15         };
  16
  17         xclk: oscillator {
  18                 #clock-cells = <0>;
  19                 compatible = "fixed-clock";
  20                 clock-frequency = <33333333>;
  21                 clock-output-names = "xtal";
  22         };
  23         pllclk: pllclk {
  24                 compatible = "renesas,h8s2678-pll-clock";
  25                 clocks = <&xclk>;
  26                 #clock-cells = <0>;
  27                 reg = <0xfee03b 2>, <0xfee045 2>;
  28         };
  29         core_clk: core_clk {
  30                 compatible = "renesas,h8300-div-clock";
  31                 clocks = <&pllclk>;
  32                 #clock-cells = <0>;
  33                 reg = <0xfee03b 2>;
  34                 renesas,width = <3>;
  35         };
  36         fclk: fclk {
  37                 compatible = "fixed-factor-clock";
  38                 clocks = <&core_clk>;
  39                 #clock-cells = <0>;
  40                 clock-div = <1>;
  41                 clock-mult = <1>;
  42         };
  43
  44         memory@400000 {
  45                 device_type = "memory";
  46                 reg = <0x400000 0x800000>;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52                 cpu@0 {
  53                         compatible = "renesas,h8300";
  54                         clock-frequency = <33333333>;
  55                 };
  56         };
  57
  58         h8intc: interrupt-controller@fffe00 {
  59                 compatible = "renesas,h8s-intc", "renesas,h8300-intc";
  60                 #interrupt-cells = <2>;
  61                 interrupt-controller;
  62                 reg = <0xfffe00 24>;
  63         };
  64
  65         bsc: memory-controller@fffec0 {
  66                 compatible = "renesas,h8s-bsc", "renesas,h8300-bsc";
  67                 reg = <0xfffec0 24>;
  68         };
  69
  70         tpu: timer@ffffe0 {
  71                 compatible = "renesas,tpu";
  72                 reg = <0xffffe0 16>, <0xfffff0 12>;
  73                 clocks = <&fclk>;
  74                 clock-names = "fck";
  75         };
  76
  77         timer8: timer@ffffb0 {
  78                 compatible = "renesas,8bit-timer";
  79                 reg = <0xffffb0 10>;
  80                 interrupts = <72 0>;
  81                 clocks = <&fclk>;
  82                 clock-names = "fck";
  83         };
  84
  85         sci0: serial@ffff78 {
  86                 compatible = "renesas,sci";
  87                 reg = <0xffff78 8>;
  88                 interrupts = <88 0>, <89 0>, <90 0>, <91 0>;
  89                 clocks = <&fclk>;
  90                 clock-names = "sci_ick";
  91         };
  92         sci1: serial@ffff80 {
  93                 compatible = "renesas,sci";
  94                 reg = <0xffff80 8>;
  95                 interrupts = <92 0>, <93 0>, <94 0>, <95 0>;
  96                 clocks = <&fclk>;
  97                 clock-names = "sci_ick";
  98         };
  99 };