2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/bootmem.h>
23 #include <linux/smp_lock.h>
24 #include <linux/interrupt.h>
25 #include <linux/mc146818rtc.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/sysdev.h>
28 #include <linux/cpu.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/arch_hooks.h>
38 #include <asm/i8253.h>
40 #include <mach_apic.h>
46 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
47 * IPIs in place of local APIC timers
49 static cpumask_t timer_bcast_ipi;
52 * Knob to control our willingness to enable the local APIC.
54 int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
62 static void apic_pm_activate(void);
65 * 'what should we do if we get a hw irq event on an illegal vector'.
66 * each architecture has to answer this themselves.
68 void ack_bad_irq(unsigned int irq)
70 printk("unexpected IRQ trap at vector %02x\n", irq);
72 * Currently unexpected vectors happen only on SMP and APIC.
73 * We _must_ ack these because every local APIC has only N
74 * irq slots per priority level, and a 'hanging, unacked' IRQ
75 * holds up an irq slot - in excessive cases (when multiple
76 * unexpected vectors occur) that might lock up the APIC
82 void __init apic_intr_init(void)
87 /* self generated IPI for local APIC timer */
88 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
90 /* IPI vectors for APIC spurious and error interrupts */
91 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
92 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
94 /* thermal monitor LVT interrupt */
95 #ifdef CONFIG_X86_MCE_P4THERMAL
96 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
100 /* Using APIC to generate smp_local_timer_interrupt? */
101 int using_apic_timer = 0;
103 static int enabled_via_apicbase;
105 void enable_NMI_through_LVT0 (void * dummy)
109 ver = apic_read(APIC_LVR);
110 ver = GET_APIC_VERSION(ver);
111 v = APIC_DM_NMI; /* unmask and set to NMI */
112 if (!APIC_INTEGRATED(ver)) /* 82489DX */
113 v |= APIC_LVT_LEVEL_TRIGGER;
114 apic_write_around(APIC_LVT0, v);
117 int get_physical_broadcast(void)
119 unsigned int lvr, version;
120 lvr = apic_read(APIC_LVR);
121 version = GET_APIC_VERSION(lvr);
122 if (!APIC_INTEGRATED(version) || version >= 0x14)
130 unsigned int v, ver, maxlvt;
132 v = apic_read(APIC_LVR);
133 ver = GET_APIC_VERSION(v);
134 /* 82489DXs do not report # of LVT entries. */
135 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
139 void clear_local_APIC(void)
144 maxlvt = get_maxlvt();
147 * Masking an LVT entry on a P6 can trigger a local APIC error
148 * if the vector is zero. Mask LVTERR first to prevent this.
151 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
152 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
155 * Careful: we have to set masks only first to deassert
156 * any level-triggered sources.
158 v = apic_read(APIC_LVTT);
159 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
160 v = apic_read(APIC_LVT0);
161 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
162 v = apic_read(APIC_LVT1);
163 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
165 v = apic_read(APIC_LVTPC);
166 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
169 /* lets not touch this if we didn't frob it */
170 #ifdef CONFIG_X86_MCE_P4THERMAL
172 v = apic_read(APIC_LVTTHMR);
173 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
177 * Clean APIC state for other OSs:
179 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
180 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
181 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
183 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
185 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
187 #ifdef CONFIG_X86_MCE_P4THERMAL
189 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
191 v = GET_APIC_VERSION(apic_read(APIC_LVR));
192 if (APIC_INTEGRATED(v)) { /* !82489DX */
193 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
194 apic_write(APIC_ESR, 0);
199 void __init connect_bsp_APIC(void)
203 * Do not trust the local APIC being empty at bootup.
207 * PIC mode, enable APIC mode in the IMCR, i.e.
208 * connect BSP's local APIC to INT and NMI lines.
210 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
211 "enabling APIC mode.\n");
218 void disconnect_bsp_APIC(int virt_wire_setup)
222 * Put the board back into PIC mode (has an effect
223 * only on certain older boards). Note that APIC
224 * interrupts, including IPIs, won't work beyond
225 * this point! The only exception are INIT IPIs.
227 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
228 "entering PIC mode.\n");
233 /* Go back to Virtual Wire compatibility mode */
236 /* For the spurious interrupt use vector F, and enable it */
237 value = apic_read(APIC_SPIV);
238 value &= ~APIC_VECTOR_MASK;
239 value |= APIC_SPIV_APIC_ENABLED;
241 apic_write_around(APIC_SPIV, value);
243 if (!virt_wire_setup) {
244 /* For LVT0 make it edge triggered, active high, external and enabled */
245 value = apic_read(APIC_LVT0);
246 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
247 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
248 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
249 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
250 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
251 apic_write_around(APIC_LVT0, value);
255 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
258 /* For LVT1 make it edge triggered, active high, nmi and enabled */
259 value = apic_read(APIC_LVT1);
261 APIC_MODE_MASK | APIC_SEND_PENDING |
262 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
263 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
264 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
265 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
266 apic_write_around(APIC_LVT1, value);
270 void disable_local_APIC(void)
277 * Disable APIC (implies clearing of registers
280 value = apic_read(APIC_SPIV);
281 value &= ~APIC_SPIV_APIC_ENABLED;
282 apic_write_around(APIC_SPIV, value);
284 if (enabled_via_apicbase) {
286 rdmsr(MSR_IA32_APICBASE, l, h);
287 l &= ~MSR_IA32_APICBASE_ENABLE;
288 wrmsr(MSR_IA32_APICBASE, l, h);
293 * This is to verify that we're looking at a real local APIC.
294 * Check these against your board if the CPUs aren't getting
295 * started for no apparent reason.
297 int __init verify_local_APIC(void)
299 unsigned int reg0, reg1;
302 * The version register is read-only in a real APIC.
304 reg0 = apic_read(APIC_LVR);
305 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
306 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
307 reg1 = apic_read(APIC_LVR);
308 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
311 * The two version reads above should print the same
312 * numbers. If the second one is different, then we
313 * poke at a non-APIC.
319 * Check if the version looks reasonably.
321 reg1 = GET_APIC_VERSION(reg0);
322 if (reg1 == 0x00 || reg1 == 0xff)
325 if (reg1 < 0x02 || reg1 == 0xff)
329 * The ID register is read/write in a real APIC.
331 reg0 = apic_read(APIC_ID);
332 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
335 * The next two are just to see if we have sane values.
336 * They're only really relevant if we're in Virtual Wire
337 * compatibility mode, but most boxes are anymore.
339 reg0 = apic_read(APIC_LVT0);
340 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
341 reg1 = apic_read(APIC_LVT1);
342 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
347 void __init sync_Arb_IDs(void)
349 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
350 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
351 if (ver >= 0x14) /* P4 or higher */
356 apic_wait_icr_idle();
358 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
359 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
363 extern void __error_in_apic_c (void);
366 * An initial setup of the virtual wire mode.
368 void __init init_bsp_APIC(void)
370 unsigned long value, ver;
373 * Don't do the setup now if we have a SMP BIOS as the
374 * through-I/O-APIC virtual wire mode might be active.
376 if (smp_found_config || !cpu_has_apic)
379 value = apic_read(APIC_LVR);
380 ver = GET_APIC_VERSION(value);
383 * Do not trust the local APIC being empty at bootup.
390 value = apic_read(APIC_SPIV);
391 value &= ~APIC_VECTOR_MASK;
392 value |= APIC_SPIV_APIC_ENABLED;
394 /* This bit is reserved on P4/Xeon and should be cleared */
395 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
396 value &= ~APIC_SPIV_FOCUS_DISABLED;
398 value |= APIC_SPIV_FOCUS_DISABLED;
399 value |= SPURIOUS_APIC_VECTOR;
400 apic_write_around(APIC_SPIV, value);
403 * Set up the virtual wire mode.
405 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
407 if (!APIC_INTEGRATED(ver)) /* 82489DX */
408 value |= APIC_LVT_LEVEL_TRIGGER;
409 apic_write_around(APIC_LVT1, value);
412 void __devinit setup_local_APIC(void)
414 unsigned long oldvalue, value, ver, maxlvt;
416 /* Pound the ESR really hard over the head with a big hammer - mbligh */
418 apic_write(APIC_ESR, 0);
419 apic_write(APIC_ESR, 0);
420 apic_write(APIC_ESR, 0);
421 apic_write(APIC_ESR, 0);
424 value = apic_read(APIC_LVR);
425 ver = GET_APIC_VERSION(value);
427 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
431 * Double-check whether this APIC is really registered.
433 if (!apic_id_registered())
437 * Intel recommends to set DFR, LDR and TPR before enabling
438 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
439 * document number 292116). So here it goes...
444 * Set Task Priority to 'accept all'. We never change this
447 value = apic_read(APIC_TASKPRI);
448 value &= ~APIC_TPRI_MASK;
449 apic_write_around(APIC_TASKPRI, value);
452 * Now that we are all set up, enable the APIC
454 value = apic_read(APIC_SPIV);
455 value &= ~APIC_VECTOR_MASK;
459 value |= APIC_SPIV_APIC_ENABLED;
462 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
463 * certain networking cards. If high frequency interrupts are
464 * happening on a particular IOAPIC pin, plus the IOAPIC routing
465 * entry is masked/unmasked at a high rate as well then sooner or
466 * later IOAPIC line gets 'stuck', no more interrupts are received
467 * from the device. If focus CPU is disabled then the hang goes
470 * [ This bug can be reproduced easily with a level-triggered
471 * PCI Ne2000 networking cards and PII/PIII processors, dual
475 * Actually disabling the focus CPU check just makes the hang less
476 * frequent as it makes the interrupt distributon model be more
477 * like LRU than MRU (the short-term load is more even across CPUs).
478 * See also the comment in end_level_ioapic_irq(). --macro
481 /* Enable focus processor (bit==0) */
482 value &= ~APIC_SPIV_FOCUS_DISABLED;
484 /* Disable focus processor (bit==1) */
485 value |= APIC_SPIV_FOCUS_DISABLED;
488 * Set spurious IRQ vector
490 value |= SPURIOUS_APIC_VECTOR;
491 apic_write_around(APIC_SPIV, value);
496 * set up through-local-APIC on the BP's LINT0. This is not
497 * strictly necessery in pure symmetric-IO mode, but sometimes
498 * we delegate interrupts to the 8259A.
501 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
503 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
504 if (!smp_processor_id() && (pic_mode || !value)) {
505 value = APIC_DM_EXTINT;
506 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
509 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
510 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
513 apic_write_around(APIC_LVT0, value);
516 * only the BP should see the LINT1 NMI signal, obviously.
518 if (!smp_processor_id())
521 value = APIC_DM_NMI | APIC_LVT_MASKED;
522 if (!APIC_INTEGRATED(ver)) /* 82489DX */
523 value |= APIC_LVT_LEVEL_TRIGGER;
524 apic_write_around(APIC_LVT1, value);
526 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
527 maxlvt = get_maxlvt();
528 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
529 apic_write(APIC_ESR, 0);
530 oldvalue = apic_read(APIC_ESR);
532 value = ERROR_APIC_VECTOR; // enables sending errors
533 apic_write_around(APIC_LVTERR, value);
535 * spec says clear errors after enabling vector.
538 apic_write(APIC_ESR, 0);
539 value = apic_read(APIC_ESR);
540 if (value != oldvalue)
541 apic_printk(APIC_VERBOSE, "ESR value before enabling "
542 "vector: 0x%08lx after: 0x%08lx\n",
547 * Something untraceble is creating bad interrupts on
548 * secondary quads ... for the moment, just leave the
549 * ESR disabled - we can't do anything useful with the
550 * errors anyway - mbligh
552 printk("Leaving ESR disabled.\n");
554 printk("No ESR for 82489DX.\n");
557 if (nmi_watchdog == NMI_LOCAL_APIC)
558 setup_apic_nmi_watchdog();
563 * If Linux enabled the LAPIC against the BIOS default
564 * disable it down before re-entering the BIOS on shutdown.
565 * Otherwise the BIOS may get confused and not power-off.
566 * Additionally clear all LVT entries before disable_local_APIC
567 * for the case where Linux didn't enable the LAPIC.
569 void lapic_shutdown(void)
577 if (enabled_via_apicbase)
578 disable_local_APIC();
587 /* r/w apic fields */
588 unsigned int apic_id;
589 unsigned int apic_taskpri;
590 unsigned int apic_ldr;
591 unsigned int apic_dfr;
592 unsigned int apic_spiv;
593 unsigned int apic_lvtt;
594 unsigned int apic_lvtpc;
595 unsigned int apic_lvt0;
596 unsigned int apic_lvt1;
597 unsigned int apic_lvterr;
598 unsigned int apic_tmict;
599 unsigned int apic_tdcr;
600 unsigned int apic_thmr;
603 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
607 if (!apic_pm_state.active)
610 apic_pm_state.apic_id = apic_read(APIC_ID);
611 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
612 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
613 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
614 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
615 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
616 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
617 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
618 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
619 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
620 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
621 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
622 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
624 local_irq_save(flags);
625 disable_local_APIC();
626 local_irq_restore(flags);
630 static int lapic_resume(struct sys_device *dev)
635 if (!apic_pm_state.active)
638 local_irq_save(flags);
641 * Make sure the APICBASE points to the right address
643 * FIXME! This will be wrong if we ever support suspend on
644 * SMP! We'll need to do this as part of the CPU restore!
646 rdmsr(MSR_IA32_APICBASE, l, h);
647 l &= ~MSR_IA32_APICBASE_BASE;
648 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
649 wrmsr(MSR_IA32_APICBASE, l, h);
651 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
652 apic_write(APIC_ID, apic_pm_state.apic_id);
653 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
654 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
655 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
656 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
657 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
658 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
659 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
660 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
661 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
662 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
663 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
664 apic_write(APIC_ESR, 0);
666 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
667 apic_write(APIC_ESR, 0);
669 local_irq_restore(flags);
674 * This device has no shutdown method - fully functioning local APICs
675 * are needed on every CPU up until machine_halt/restart/poweroff.
678 static struct sysdev_class lapic_sysclass = {
679 set_kset_name("lapic"),
680 .resume = lapic_resume,
681 .suspend = lapic_suspend,
684 static struct sys_device device_lapic = {
686 .cls = &lapic_sysclass,
689 static void __devinit apic_pm_activate(void)
691 apic_pm_state.active = 1;
694 static int __init init_lapic_sysfs(void)
700 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
702 error = sysdev_class_register(&lapic_sysclass);
704 error = sysdev_register(&device_lapic);
707 device_initcall(init_lapic_sysfs);
709 #else /* CONFIG_PM */
711 static void apic_pm_activate(void) { }
713 #endif /* CONFIG_PM */
716 * Detect and enable local APICs on non-SMP boards.
717 * Original code written by Keir Fraser.
720 static int __init apic_set_verbosity(char *str)
722 if (strcmp("debug", str) == 0)
723 apic_verbosity = APIC_DEBUG;
724 else if (strcmp("verbose", str) == 0)
725 apic_verbosity = APIC_VERBOSE;
727 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
728 " use apic=verbose or apic=debug\n", str);
733 __setup("apic=", apic_set_verbosity);
735 static int __init detect_init_APIC (void)
739 /* Disabled by kernel option? */
740 if (enable_local_apic < 0)
743 switch (boot_cpu_data.x86_vendor) {
745 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
746 (boot_cpu_data.x86 == 15))
749 case X86_VENDOR_INTEL:
750 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
751 (boot_cpu_data.x86 == 5 && cpu_has_apic))
760 * Over-ride BIOS and try to enable the local
761 * APIC only if "lapic" specified.
763 if (enable_local_apic <= 0) {
764 printk("Local APIC disabled by BIOS -- "
765 "you can enable it with \"lapic\"\n");
769 * Some BIOSes disable the local APIC in the
770 * APIC_BASE MSR. This can only be done in
771 * software for Intel P6 or later and AMD K7
772 * (Model > 1) or later.
774 rdmsr(MSR_IA32_APICBASE, l, h);
775 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
776 printk("Local APIC disabled by BIOS -- reenabling.\n");
777 l &= ~MSR_IA32_APICBASE_BASE;
778 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
779 wrmsr(MSR_IA32_APICBASE, l, h);
780 enabled_via_apicbase = 1;
784 * The APIC feature bit should now be enabled
787 features = cpuid_edx(1);
788 if (!(features & (1 << X86_FEATURE_APIC))) {
789 printk("Could not enable APIC!\n");
792 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
793 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
795 /* The BIOS may have set up the APIC at some other address */
796 rdmsr(MSR_IA32_APICBASE, l, h);
797 if (l & MSR_IA32_APICBASE_ENABLE)
798 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
800 if (nmi_watchdog != NMI_NONE)
801 nmi_watchdog = NMI_LOCAL_APIC;
803 printk("Found and enabled local APIC!\n");
810 printk("No local APIC present or hardware disabled\n");
814 void __init init_apic_mappings(void)
816 unsigned long apic_phys;
819 * If no local APIC can be found then set up a fake all
820 * zeroes page to simulate the local APIC and another
821 * one for the IO-APIC.
823 if (!smp_found_config && detect_init_APIC()) {
824 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
825 apic_phys = __pa(apic_phys);
827 apic_phys = mp_lapic_addr;
829 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
830 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
834 * Fetch the APIC ID of the BSP in case we have a
835 * default configuration (or the MP table is broken).
837 if (boot_cpu_physical_apicid == -1U)
838 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
840 #ifdef CONFIG_X86_IO_APIC
842 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
845 for (i = 0; i < nr_ioapics; i++) {
846 if (smp_found_config) {
847 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
850 "WARNING: bogus zero IO-APIC "
851 "address found in MPTABLE, "
852 "disabling IO/APIC support!\n");
853 smp_found_config = 0;
854 skip_ioapic_setup = 1;
855 goto fake_ioapic_page;
859 ioapic_phys = (unsigned long)
860 alloc_bootmem_pages(PAGE_SIZE);
861 ioapic_phys = __pa(ioapic_phys);
863 set_fixmap_nocache(idx, ioapic_phys);
864 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
865 __fix_to_virt(idx), ioapic_phys);
873 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
874 * per second. We assume that the caller has already set up the local
877 * The APIC timer is not exactly sync with the external timer chip, it
878 * closely follows bus clocks.
882 * The timer chip is already set up at HZ interrupts per second here,
883 * but we do not accept timer interrupts yet. We only allow the BP
886 static unsigned int __devinit get_8254_timer_count(void)
892 spin_lock_irqsave(&i8253_lock, flags);
894 outb_p(0x00, PIT_MODE);
895 count = inb_p(PIT_CH0);
896 count |= inb_p(PIT_CH0) << 8;
898 spin_unlock_irqrestore(&i8253_lock, flags);
903 /* next tick in 8254 can be caught by catching timer wraparound */
904 static void __devinit wait_8254_wraparound(void)
906 unsigned int curr_count, prev_count;
908 curr_count = get_8254_timer_count();
910 prev_count = curr_count;
911 curr_count = get_8254_timer_count();
913 /* workaround for broken Mercury/Neptune */
914 if (prev_count >= curr_count + 0x100)
915 curr_count = get_8254_timer_count();
917 } while (prev_count >= curr_count);
921 * Default initialization for 8254 timers. If we use other timers like HPET,
922 * we override this later
924 void (*wait_timer_tick)(void) __devinitdata = wait_8254_wraparound;
927 * This function sets up the local APIC timer, with a timeout of
928 * 'clocks' APIC bus clock. During calibration we actually call
929 * this function twice on the boot CPU, once with a bogus timeout
930 * value, second time for real. The other (noncalibrating) CPUs
931 * call this function only once, with the real, calibrated value.
933 * We do reads before writes even if unnecessary, to get around the
934 * P5 APIC double write bug.
937 #define APIC_DIVISOR 16
939 static void __setup_APIC_LVTT(unsigned int clocks)
941 unsigned int lvtt_value, tmp_value, ver;
942 int cpu = smp_processor_id();
944 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
945 lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
946 if (!APIC_INTEGRATED(ver))
947 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
949 if (cpu_isset(cpu, timer_bcast_ipi))
950 lvtt_value |= APIC_LVT_MASKED;
952 apic_write_around(APIC_LVTT, lvtt_value);
957 tmp_value = apic_read(APIC_TDCR);
958 apic_write_around(APIC_TDCR, (tmp_value
959 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
962 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
965 static void __devinit setup_APIC_timer(unsigned int clocks)
969 local_irq_save(flags);
972 * Wait for IRQ0's slice:
976 __setup_APIC_LVTT(clocks);
978 local_irq_restore(flags);
982 * In this function we calibrate APIC bus clocks to the external
983 * timer. Unfortunately we cannot use jiffies and the timer irq
984 * to calibrate, since some later bootup code depends on getting
985 * the first irq? Ugh.
987 * We want to do the calibration only once since we
988 * want to have local timer irqs syncron. CPUs connected
989 * by the same APIC bus have the very same bus frequency.
990 * And we want to have irqs off anyways, no accidental
994 static int __init calibrate_APIC_clock(void)
996 unsigned long long t1 = 0, t2 = 0;
1000 const int LOOPS = HZ/10;
1002 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
1005 * Put whatever arbitrary (but long enough) timeout
1006 * value into the APIC clock, we just want to get the
1007 * counter running for calibration.
1009 __setup_APIC_LVTT(1000000000);
1012 * The timer chip counts down to zero. Let's wait
1013 * for a wraparound to start exact measurement:
1014 * (the current tick might have been already half done)
1020 * We wrapped around just now. Let's start:
1024 tt1 = apic_read(APIC_TMCCT);
1027 * Let's wait LOOPS wraprounds:
1029 for (i = 0; i < LOOPS; i++)
1032 tt2 = apic_read(APIC_TMCCT);
1037 * The APIC bus clock counter is 32 bits only, it
1038 * might have overflown, but note that we use signed
1039 * longs, thus no extra care needed.
1041 * underflown to be exact, as the timer counts down ;)
1044 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
1047 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
1049 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
1050 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
1052 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
1054 result/(1000000/HZ),
1055 result%(1000000/HZ));
1060 static unsigned int calibration_result;
1062 void __init setup_boot_APIC_clock(void)
1064 unsigned long flags;
1065 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
1066 using_apic_timer = 1;
1068 local_irq_save(flags);
1070 calibration_result = calibrate_APIC_clock();
1072 * Now set up the timer for real.
1074 setup_APIC_timer(calibration_result);
1076 local_irq_restore(flags);
1079 void __devinit setup_secondary_APIC_clock(void)
1081 setup_APIC_timer(calibration_result);
1084 void disable_APIC_timer(void)
1086 if (using_apic_timer) {
1089 v = apic_read(APIC_LVTT);
1090 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
1094 void enable_APIC_timer(void)
1096 int cpu = smp_processor_id();
1098 if (using_apic_timer &&
1099 !cpu_isset(cpu, timer_bcast_ipi)) {
1102 v = apic_read(APIC_LVTT);
1103 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
1107 void switch_APIC_timer_to_ipi(void *cpumask)
1109 cpumask_t mask = *(cpumask_t *)cpumask;
1110 int cpu = smp_processor_id();
1112 if (cpu_isset(cpu, mask) &&
1113 !cpu_isset(cpu, timer_bcast_ipi)) {
1114 disable_APIC_timer();
1115 cpu_set(cpu, timer_bcast_ipi);
1118 EXPORT_SYMBOL(switch_APIC_timer_to_ipi);
1120 void switch_ipi_to_APIC_timer(void *cpumask)
1122 cpumask_t mask = *(cpumask_t *)cpumask;
1123 int cpu = smp_processor_id();
1125 if (cpu_isset(cpu, mask) &&
1126 cpu_isset(cpu, timer_bcast_ipi)) {
1127 cpu_clear(cpu, timer_bcast_ipi);
1128 enable_APIC_timer();
1131 EXPORT_SYMBOL(switch_ipi_to_APIC_timer);
1136 * Local timer interrupt handler. It does both profiling and
1137 * process statistics/rescheduling.
1139 * We do profiling in every local tick, statistics/rescheduling
1140 * happen only every 'profiling multiplier' ticks. The default
1141 * multiplier is 1 and it can be changed by writing the new multiplier
1142 * value into /proc/profile.
1145 inline void smp_local_timer_interrupt(struct pt_regs * regs)
1147 profile_tick(CPU_PROFILING, regs);
1149 update_process_times(user_mode_vm(regs));
1153 * We take the 'long' return path, and there every subsystem
1154 * grabs the apropriate locks (kernel lock/ irq lock).
1156 * we might want to decouple profiling from the 'long path',
1157 * and do the profiling totally in assembly.
1159 * Currently this isn't too much of an issue (performance wise),
1160 * we can take more than 100K local irqs per second on a 100 MHz P5.
1165 * Local APIC timer interrupt. This is the most natural way for doing
1166 * local interrupts, but local timer interrupts can be emulated by
1167 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1169 * [ if a single-CPU system runs an SMP kernel then we call the local
1170 * interrupt as well. Thus we cannot inline the local irq ... ]
1173 fastcall void smp_apic_timer_interrupt(struct pt_regs *regs)
1175 int cpu = smp_processor_id();
1178 * the NMI deadlock-detector uses this.
1180 per_cpu(irq_stat, cpu).apic_timer_irqs++;
1183 * NOTE! We'd better ACK the irq immediately,
1184 * because timer handling can be slow.
1188 * update_process_times() expects us to have done irq_enter().
1189 * Besides, if we don't timer interrupts ignore the global
1190 * interrupt lock, which is the WrongThing (tm) to do.
1193 smp_local_timer_interrupt(regs);
1198 static void up_apic_timer_interrupt_call(struct pt_regs *regs)
1200 int cpu = smp_processor_id();
1203 * the NMI deadlock-detector uses this.
1205 per_cpu(irq_stat, cpu).apic_timer_irqs++;
1207 smp_local_timer_interrupt(regs);
1211 void smp_send_timer_broadcast_ipi(struct pt_regs *regs)
1215 cpus_and(mask, cpu_online_map, timer_bcast_ipi);
1216 if (!cpus_empty(mask)) {
1218 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
1221 * We can directly call the apic timer interrupt handler
1222 * in UP case. Minus all irq related functions
1224 up_apic_timer_interrupt_call(regs);
1229 int setup_profiling_timer(unsigned int multiplier)
1235 * This interrupt should _never_ happen with our APIC/SMP architecture
1237 fastcall void smp_spurious_interrupt(struct pt_regs *regs)
1243 * Check if this really is a spurious interrupt and ACK it
1244 * if it is a vectored one. Just in case...
1245 * Spurious interrupts should not be ACKed.
1247 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1248 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1251 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1252 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
1253 smp_processor_id());
1258 * This interrupt should never happen with our APIC/SMP architecture
1261 fastcall void smp_error_interrupt(struct pt_regs *regs)
1263 unsigned long v, v1;
1266 /* First tickle the hardware, only then report what went on. -- REW */
1267 v = apic_read(APIC_ESR);
1268 apic_write(APIC_ESR, 0);
1269 v1 = apic_read(APIC_ESR);
1271 atomic_inc(&irq_err_count);
1273 /* Here is what the APIC error bits mean:
1276 2: Send accept error
1277 3: Receive accept error
1279 5: Send illegal vector
1280 6: Received illegal vector
1281 7: Illegal register address
1283 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1284 smp_processor_id(), v , v1);
1289 * This initializes the IO-APIC and APIC hardware if this is
1292 int __init APIC_init_uniprocessor (void)
1294 if (enable_local_apic < 0)
1295 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1297 if (!smp_found_config && !cpu_has_apic)
1301 * Complain if the BIOS pretends there is one.
1303 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1304 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1305 boot_cpu_physical_apicid);
1309 verify_local_APIC();
1313 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
1317 #ifdef CONFIG_X86_IO_APIC
1318 if (smp_found_config)
1319 if (!skip_ioapic_setup && nr_ioapics)
1322 setup_boot_APIC_clock();