2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
41 #include <asm/timer.h>
42 #include <asm/i8259.h>
44 #include <asm/msidef.h>
45 #include <asm/hypertransport.h>
47 #include <mach_apic.h>
48 #include <mach_apicdef.h>
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
61 int timer_over_8254 __initdata = 1;
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
67 int sis_apic_bug = -1;
70 * # of IRQ routing registers
72 int nr_ioapic_registers[MAX_IO_APICS];
74 static int disable_timer_pin_1 __initdata;
77 * Rough estimation of how many shared IRQs there are, can
80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
84 * This is performance-critical, we want to do it O(1)
86 * the indexing order of this array favors 1:1 mappings
87 * between pins and IRQs.
90 static struct irq_pin_list {
92 } irq_2_pin[PIN_MAP_SIZE];
96 unsigned int unused[3];
100 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
102 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
103 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
106 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
108 struct io_apic __iomem *io_apic = io_apic_base(apic);
109 writel(reg, &io_apic->index);
110 return readl(&io_apic->data);
113 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
115 struct io_apic __iomem *io_apic = io_apic_base(apic);
116 writel(reg, &io_apic->index);
117 writel(value, &io_apic->data);
121 * Re-write a value: to be used for read-modify-write
122 * cycles where the read already set up the index register.
124 * Older SiS APIC requires we rewrite the index register
126 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
128 volatile struct io_apic *io_apic = io_apic_base(apic);
130 writel(reg, &io_apic->index);
131 writel(value, &io_apic->data);
135 struct { u32 w1, w2; };
136 struct IO_APIC_route_entry entry;
139 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
141 union entry_union eu;
143 spin_lock_irqsave(&ioapic_lock, flags);
144 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
145 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
146 spin_unlock_irqrestore(&ioapic_lock, flags);
151 * When we write a new IO APIC routing entry, we need to write the high
152 * word first! If the mask bit in the low word is clear, we will enable
153 * the interrupt, and we need to make sure the entry is fully populated
154 * before that happens.
157 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
159 union entry_union eu;
161 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
162 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
165 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
168 spin_lock_irqsave(&ioapic_lock, flags);
169 __ioapic_write_entry(apic, pin, e);
170 spin_unlock_irqrestore(&ioapic_lock, flags);
174 * When we mask an IO APIC routing entry, we need to write the low
175 * word first, in order to set the mask bit before we change the
178 static void ioapic_mask_entry(int apic, int pin)
181 union entry_union eu = { .entry.mask = 1 };
183 spin_lock_irqsave(&ioapic_lock, flags);
184 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
185 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
186 spin_unlock_irqrestore(&ioapic_lock, flags);
190 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
191 * shared ISA-space IRQs, so we have to support them. We are super
192 * fast in the common case, and fast for shared ISA-space IRQs.
194 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
196 static int first_free_entry = NR_IRQS;
197 struct irq_pin_list *entry = irq_2_pin + irq;
200 entry = irq_2_pin + entry->next;
202 if (entry->pin != -1) {
203 entry->next = first_free_entry;
204 entry = irq_2_pin + entry->next;
205 if (++first_free_entry >= PIN_MAP_SIZE)
206 panic("io_apic.c: whoops");
213 * Reroute an IRQ to a different pin.
215 static void __init replace_pin_at_irq(unsigned int irq,
216 int oldapic, int oldpin,
217 int newapic, int newpin)
219 struct irq_pin_list *entry = irq_2_pin + irq;
222 if (entry->apic == oldapic && entry->pin == oldpin) {
223 entry->apic = newapic;
228 entry = irq_2_pin + entry->next;
232 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
234 struct irq_pin_list *entry = irq_2_pin + irq;
235 unsigned int pin, reg;
241 reg = io_apic_read(entry->apic, 0x10 + pin*2);
244 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
247 entry = irq_2_pin + entry->next;
252 static void __mask_IO_APIC_irq (unsigned int irq)
254 __modify_IO_APIC_irq(irq, 0x00010000, 0);
258 static void __unmask_IO_APIC_irq (unsigned int irq)
260 __modify_IO_APIC_irq(irq, 0, 0x00010000);
263 /* mask = 1, trigger = 0 */
264 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
266 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
269 /* mask = 0, trigger = 1 */
270 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
272 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
275 static void mask_IO_APIC_irq (unsigned int irq)
279 spin_lock_irqsave(&ioapic_lock, flags);
280 __mask_IO_APIC_irq(irq);
281 spin_unlock_irqrestore(&ioapic_lock, flags);
284 static void unmask_IO_APIC_irq (unsigned int irq)
288 spin_lock_irqsave(&ioapic_lock, flags);
289 __unmask_IO_APIC_irq(irq);
290 spin_unlock_irqrestore(&ioapic_lock, flags);
293 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
295 struct IO_APIC_route_entry entry;
297 /* Check delivery_mode to be sure we're not clearing an SMI pin */
298 entry = ioapic_read_entry(apic, pin);
299 if (entry.delivery_mode == dest_SMI)
303 * Disable it in the IO-APIC irq-routing table:
305 ioapic_mask_entry(apic, pin);
308 static void clear_IO_APIC (void)
312 for (apic = 0; apic < nr_ioapics; apic++)
313 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
314 clear_IO_APIC_pin(apic, pin);
318 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
322 struct irq_pin_list *entry = irq_2_pin + irq;
323 unsigned int apicid_value;
326 cpus_and(tmp, cpumask, cpu_online_map);
330 cpus_and(cpumask, tmp, CPU_MASK_ALL);
332 apicid_value = cpu_mask_to_apicid(cpumask);
333 /* Prepare to do the io_apic_write */
334 apicid_value = apicid_value << 24;
335 spin_lock_irqsave(&ioapic_lock, flags);
340 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
343 entry = irq_2_pin + entry->next;
345 set_native_irq_info(irq, cpumask);
346 spin_unlock_irqrestore(&ioapic_lock, flags);
349 #if defined(CONFIG_IRQBALANCE)
350 # include <asm/processor.h> /* kernel_thread() */
351 # include <linux/kernel_stat.h> /* kstat */
352 # include <linux/slab.h> /* kmalloc() */
353 # include <linux/timer.h> /* time_after() */
355 #ifdef CONFIG_BALANCED_IRQ_DEBUG
356 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
357 # define Dprintk(x...) do { TDprintk(x); } while (0)
359 # define TDprintk(x...)
360 # define Dprintk(x...)
363 #define IRQBALANCE_CHECK_ARCH -999
364 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
365 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
366 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
367 #define BALANCED_IRQ_LESS_DELTA (HZ)
369 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
370 static int physical_balance __read_mostly;
371 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
373 static struct irq_cpu_info {
374 unsigned long * last_irq;
375 unsigned long * irq_delta;
377 } irq_cpu_data[NR_CPUS];
379 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
380 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
381 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
383 #define IDLE_ENOUGH(cpu,now) \
384 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
386 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
388 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
390 static cpumask_t balance_irq_affinity[NR_IRQS] = {
391 [0 ... NR_IRQS-1] = CPU_MASK_ALL
394 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
396 balance_irq_affinity[irq] = mask;
399 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
400 unsigned long now, int direction)
408 if (unlikely(cpu == curr_cpu))
411 if (direction == 1) {
420 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
421 (search_idle && !IDLE_ENOUGH(cpu,now)));
426 static inline void balance_irq(int cpu, int irq)
428 unsigned long now = jiffies;
429 cpumask_t allowed_mask;
430 unsigned int new_cpu;
432 if (irqbalance_disabled)
435 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
436 new_cpu = move(cpu, allowed_mask, now, 1);
437 if (cpu != new_cpu) {
438 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
442 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
445 Dprintk("Rotating IRQs among CPUs.\n");
446 for_each_online_cpu(i) {
447 for (j = 0; j < NR_IRQS; j++) {
448 if (!irq_desc[j].action)
450 /* Is it a significant load ? */
451 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
452 useful_load_threshold)
457 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
458 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
462 static void do_irq_balance(void)
465 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
466 unsigned long move_this_load = 0;
467 int max_loaded = 0, min_loaded = 0;
469 unsigned long useful_load_threshold = balanced_irq_interval + 10;
471 int tmp_loaded, first_attempt = 1;
472 unsigned long tmp_cpu_irq;
473 unsigned long imbalance = 0;
474 cpumask_t allowed_mask, target_cpu_mask, tmp;
476 for_each_possible_cpu(i) {
481 package_index = CPU_TO_PACKAGEINDEX(i);
482 for (j = 0; j < NR_IRQS; j++) {
483 unsigned long value_now, delta;
484 /* Is this an active IRQ? */
485 if (!irq_desc[j].action)
487 if ( package_index == i )
488 IRQ_DELTA(package_index,j) = 0;
489 /* Determine the total count per processor per IRQ */
490 value_now = (unsigned long) kstat_cpu(i).irqs[j];
492 /* Determine the activity per processor per IRQ */
493 delta = value_now - LAST_CPU_IRQ(i,j);
495 /* Update last_cpu_irq[][] for the next time */
496 LAST_CPU_IRQ(i,j) = value_now;
498 /* Ignore IRQs whose rate is less than the clock */
499 if (delta < useful_load_threshold)
501 /* update the load for the processor or package total */
502 IRQ_DELTA(package_index,j) += delta;
504 /* Keep track of the higher numbered sibling as well */
505 if (i != package_index)
508 * We have sibling A and sibling B in the package
510 * cpu_irq[A] = load for cpu A + load for cpu B
511 * cpu_irq[B] = load for cpu B
513 CPU_IRQ(package_index) += delta;
516 /* Find the least loaded processor package */
517 for_each_online_cpu(i) {
518 if (i != CPU_TO_PACKAGEINDEX(i))
520 if (min_cpu_irq > CPU_IRQ(i)) {
521 min_cpu_irq = CPU_IRQ(i);
525 max_cpu_irq = ULONG_MAX;
528 /* Look for heaviest loaded processor.
529 * We may come back to get the next heaviest loaded processor.
530 * Skip processors with trivial loads.
534 for_each_online_cpu(i) {
535 if (i != CPU_TO_PACKAGEINDEX(i))
537 if (max_cpu_irq <= CPU_IRQ(i))
539 if (tmp_cpu_irq < CPU_IRQ(i)) {
540 tmp_cpu_irq = CPU_IRQ(i);
545 if (tmp_loaded == -1) {
546 /* In the case of small number of heavy interrupt sources,
547 * loading some of the cpus too much. We use Ingo's original
548 * approach to rotate them around.
550 if (!first_attempt && imbalance >= useful_load_threshold) {
551 rotate_irqs_among_cpus(useful_load_threshold);
554 goto not_worth_the_effort;
557 first_attempt = 0; /* heaviest search */
558 max_cpu_irq = tmp_cpu_irq; /* load */
559 max_loaded = tmp_loaded; /* processor */
560 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
562 Dprintk("max_loaded cpu = %d\n", max_loaded);
563 Dprintk("min_loaded cpu = %d\n", min_loaded);
564 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
565 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
566 Dprintk("load imbalance = %lu\n", imbalance);
568 /* if imbalance is less than approx 10% of max load, then
569 * observe diminishing returns action. - quit
571 if (imbalance < (max_cpu_irq >> 3)) {
572 Dprintk("Imbalance too trivial\n");
573 goto not_worth_the_effort;
577 /* if we select an IRQ to move that can't go where we want, then
578 * see if there is another one to try.
582 for (j = 0; j < NR_IRQS; j++) {
583 /* Is this an active IRQ? */
584 if (!irq_desc[j].action)
586 if (imbalance <= IRQ_DELTA(max_loaded,j))
588 /* Try to find the IRQ that is closest to the imbalance
589 * without going over.
591 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
592 move_this_load = IRQ_DELTA(max_loaded,j);
596 if (selected_irq == -1) {
600 imbalance = move_this_load;
602 /* For physical_balance case, we accumlated both load
603 * values in the one of the siblings cpu_irq[],
604 * to use the same code for physical and logical processors
605 * as much as possible.
607 * NOTE: the cpu_irq[] array holds the sum of the load for
608 * sibling A and sibling B in the slot for the lowest numbered
609 * sibling (A), _AND_ the load for sibling B in the slot for
610 * the higher numbered sibling.
612 * We seek the least loaded sibling by making the comparison
615 load = CPU_IRQ(min_loaded) >> 1;
616 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
617 if (load > CPU_IRQ(j)) {
618 /* This won't change cpu_sibling_map[min_loaded] */
624 cpus_and(allowed_mask,
626 balance_irq_affinity[selected_irq]);
627 target_cpu_mask = cpumask_of_cpu(min_loaded);
628 cpus_and(tmp, target_cpu_mask, allowed_mask);
630 if (!cpus_empty(tmp)) {
632 Dprintk("irq = %d moved to cpu = %d\n",
633 selected_irq, min_loaded);
634 /* mark for change destination */
635 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
637 /* Since we made a change, come back sooner to
638 * check for more variation.
640 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
641 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
646 not_worth_the_effort:
648 * if we did not find an IRQ to move, then adjust the time interval
651 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
652 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
653 Dprintk("IRQ worth rotating not found\n");
657 static int balanced_irq(void *unused)
660 unsigned long prev_balance_time = jiffies;
661 long time_remaining = balanced_irq_interval;
665 /* push everything to CPU 0 to give us a starting point. */
666 for (i = 0 ; i < NR_IRQS ; i++) {
667 irq_desc[i].pending_mask = cpumask_of_cpu(0);
668 set_pending_irq(i, cpumask_of_cpu(0));
672 time_remaining = schedule_timeout_interruptible(time_remaining);
674 if (time_after(jiffies,
675 prev_balance_time+balanced_irq_interval)) {
678 prev_balance_time = jiffies;
679 time_remaining = balanced_irq_interval;
686 static int __init balanced_irq_init(void)
689 struct cpuinfo_x86 *c;
692 cpus_shift_right(tmp, cpu_online_map, 2);
694 /* When not overwritten by the command line ask subarchitecture. */
695 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
696 irqbalance_disabled = NO_BALANCE_IRQ;
697 if (irqbalance_disabled)
700 /* disable irqbalance completely if there is only one processor online */
701 if (num_online_cpus() < 2) {
702 irqbalance_disabled = 1;
706 * Enable physical balance only if more than 1 physical processor
709 if (smp_num_siblings > 1 && !cpus_empty(tmp))
710 physical_balance = 1;
712 for_each_online_cpu(i) {
713 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
714 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
715 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
716 printk(KERN_ERR "balanced_irq_init: out of memory");
719 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
720 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
723 printk(KERN_INFO "Starting balanced_irq\n");
724 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
727 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
729 for_each_possible_cpu(i) {
730 kfree(irq_cpu_data[i].irq_delta);
731 irq_cpu_data[i].irq_delta = NULL;
732 kfree(irq_cpu_data[i].last_irq);
733 irq_cpu_data[i].last_irq = NULL;
738 int __init irqbalance_disable(char *str)
740 irqbalance_disabled = 1;
744 __setup("noirqbalance", irqbalance_disable);
746 late_initcall(balanced_irq_init);
747 #endif /* CONFIG_IRQBALANCE */
748 #endif /* CONFIG_SMP */
751 void fastcall send_IPI_self(int vector)
758 apic_wait_icr_idle();
759 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
761 * Send the IPI. The write to APIC_ICR fires this off.
763 apic_write_around(APIC_ICR, cfg);
765 #endif /* !CONFIG_SMP */
769 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
770 * specific CPU-side IRQs.
774 static int pirq_entries [MAX_PIRQS];
775 static int pirqs_enabled;
776 int skip_ioapic_setup;
778 static int __init ioapic_setup(char *str)
780 skip_ioapic_setup = 1;
784 __setup("noapic", ioapic_setup);
786 static int __init ioapic_pirq_setup(char *str)
789 int ints[MAX_PIRQS+1];
791 get_options(str, ARRAY_SIZE(ints), ints);
793 for (i = 0; i < MAX_PIRQS; i++)
794 pirq_entries[i] = -1;
797 apic_printk(APIC_VERBOSE, KERN_INFO
798 "PIRQ redirection, working around broken MP-BIOS.\n");
800 if (ints[0] < MAX_PIRQS)
803 for (i = 0; i < max; i++) {
804 apic_printk(APIC_VERBOSE, KERN_DEBUG
805 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
807 * PIRQs are mapped upside down, usually.
809 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
814 __setup("pirq=", ioapic_pirq_setup);
817 * Find the IRQ entry number of a certain pin.
819 static int find_irq_entry(int apic, int pin, int type)
823 for (i = 0; i < mp_irq_entries; i++)
824 if (mp_irqs[i].mpc_irqtype == type &&
825 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
826 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
827 mp_irqs[i].mpc_dstirq == pin)
834 * Find the pin to which IRQ[irq] (ISA) is connected
836 static int __init find_isa_irq_pin(int irq, int type)
840 for (i = 0; i < mp_irq_entries; i++) {
841 int lbus = mp_irqs[i].mpc_srcbus;
843 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
844 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
845 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
846 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
848 (mp_irqs[i].mpc_irqtype == type) &&
849 (mp_irqs[i].mpc_srcbusirq == irq))
851 return mp_irqs[i].mpc_dstirq;
856 static int __init find_isa_irq_apic(int irq, int type)
860 for (i = 0; i < mp_irq_entries; i++) {
861 int lbus = mp_irqs[i].mpc_srcbus;
863 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
864 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
865 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
866 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
868 (mp_irqs[i].mpc_irqtype == type) &&
869 (mp_irqs[i].mpc_srcbusirq == irq))
872 if (i < mp_irq_entries) {
874 for(apic = 0; apic < nr_ioapics; apic++) {
875 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
884 * Find a specific PCI IRQ entry.
885 * Not an __init, possibly needed by modules
887 static int pin_2_irq(int idx, int apic, int pin);
889 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
891 int apic, i, best_guess = -1;
893 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
894 "slot:%d, pin:%d.\n", bus, slot, pin);
895 if (mp_bus_id_to_pci_bus[bus] == -1) {
896 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
899 for (i = 0; i < mp_irq_entries; i++) {
900 int lbus = mp_irqs[i].mpc_srcbus;
902 for (apic = 0; apic < nr_ioapics; apic++)
903 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
904 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
907 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
908 !mp_irqs[i].mpc_irqtype &&
910 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
911 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
913 if (!(apic || IO_APIC_IRQ(irq)))
916 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
919 * Use the first all-but-pin matching entry as a
920 * best-guess fuzzy result for broken mptables.
928 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
931 * This function currently is only a helper for the i386 smp boot process where
932 * we need to reprogram the ioredtbls to cater for the cpus which have come online
933 * so mask in all cases should simply be TARGET_CPUS
936 void __init setup_ioapic_dest(void)
938 int pin, ioapic, irq, irq_entry;
940 if (skip_ioapic_setup == 1)
943 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
944 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
945 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
948 irq = pin_2_irq(irq_entry, ioapic, pin);
949 set_ioapic_affinity_irq(irq, TARGET_CPUS);
957 * EISA Edge/Level control register, ELCR
959 static int EISA_ELCR(unsigned int irq)
962 unsigned int port = 0x4d0 + (irq >> 3);
963 return (inb(port) >> (irq & 7)) & 1;
965 apic_printk(APIC_VERBOSE, KERN_INFO
966 "Broken MPtable reports ISA irq %d\n", irq);
970 /* EISA interrupts are always polarity zero and can be edge or level
971 * trigger depending on the ELCR value. If an interrupt is listed as
972 * EISA conforming in the MP table, that means its trigger type must
973 * be read in from the ELCR */
975 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
976 #define default_EISA_polarity(idx) (0)
978 /* ISA interrupts are always polarity zero edge triggered,
979 * when listed as conforming in the MP table. */
981 #define default_ISA_trigger(idx) (0)
982 #define default_ISA_polarity(idx) (0)
984 /* PCI interrupts are always polarity one level triggered,
985 * when listed as conforming in the MP table. */
987 #define default_PCI_trigger(idx) (1)
988 #define default_PCI_polarity(idx) (1)
990 /* MCA interrupts are always polarity zero level triggered,
991 * when listed as conforming in the MP table. */
993 #define default_MCA_trigger(idx) (1)
994 #define default_MCA_polarity(idx) (0)
996 /* NEC98 interrupts are always polarity zero edge triggered,
997 * when listed as conforming in the MP table. */
999 #define default_NEC98_trigger(idx) (0)
1000 #define default_NEC98_polarity(idx) (0)
1002 static int __init MPBIOS_polarity(int idx)
1004 int bus = mp_irqs[idx].mpc_srcbus;
1008 * Determine IRQ line polarity (high active or low active):
1010 switch (mp_irqs[idx].mpc_irqflag & 3)
1012 case 0: /* conforms, ie. bus-type dependent polarity */
1014 switch (mp_bus_id_to_type[bus])
1016 case MP_BUS_ISA: /* ISA pin */
1018 polarity = default_ISA_polarity(idx);
1021 case MP_BUS_EISA: /* EISA pin */
1023 polarity = default_EISA_polarity(idx);
1026 case MP_BUS_PCI: /* PCI pin */
1028 polarity = default_PCI_polarity(idx);
1031 case MP_BUS_MCA: /* MCA pin */
1033 polarity = default_MCA_polarity(idx);
1036 case MP_BUS_NEC98: /* NEC 98 pin */
1038 polarity = default_NEC98_polarity(idx);
1043 printk(KERN_WARNING "broken BIOS!!\n");
1050 case 1: /* high active */
1055 case 2: /* reserved */
1057 printk(KERN_WARNING "broken BIOS!!\n");
1061 case 3: /* low active */
1066 default: /* invalid */
1068 printk(KERN_WARNING "broken BIOS!!\n");
1076 static int MPBIOS_trigger(int idx)
1078 int bus = mp_irqs[idx].mpc_srcbus;
1082 * Determine IRQ trigger mode (edge or level sensitive):
1084 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1086 case 0: /* conforms, ie. bus-type dependent */
1088 switch (mp_bus_id_to_type[bus])
1090 case MP_BUS_ISA: /* ISA pin */
1092 trigger = default_ISA_trigger(idx);
1095 case MP_BUS_EISA: /* EISA pin */
1097 trigger = default_EISA_trigger(idx);
1100 case MP_BUS_PCI: /* PCI pin */
1102 trigger = default_PCI_trigger(idx);
1105 case MP_BUS_MCA: /* MCA pin */
1107 trigger = default_MCA_trigger(idx);
1110 case MP_BUS_NEC98: /* NEC 98 pin */
1112 trigger = default_NEC98_trigger(idx);
1117 printk(KERN_WARNING "broken BIOS!!\n");
1129 case 2: /* reserved */
1131 printk(KERN_WARNING "broken BIOS!!\n");
1140 default: /* invalid */
1142 printk(KERN_WARNING "broken BIOS!!\n");
1150 static inline int irq_polarity(int idx)
1152 return MPBIOS_polarity(idx);
1155 static inline int irq_trigger(int idx)
1157 return MPBIOS_trigger(idx);
1160 static int pin_2_irq(int idx, int apic, int pin)
1163 int bus = mp_irqs[idx].mpc_srcbus;
1166 * Debugging check, we are in big trouble if this message pops up!
1168 if (mp_irqs[idx].mpc_dstirq != pin)
1169 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1171 switch (mp_bus_id_to_type[bus])
1173 case MP_BUS_ISA: /* ISA pin */
1178 irq = mp_irqs[idx].mpc_srcbusirq;
1181 case MP_BUS_PCI: /* PCI pin */
1184 * PCI IRQs are mapped in order
1188 irq += nr_ioapic_registers[i++];
1192 * For MPS mode, so far only needed by ES7000 platform
1194 if (ioapic_renumber_irq)
1195 irq = ioapic_renumber_irq(apic, irq);
1201 printk(KERN_ERR "unknown bus type %d.\n",bus);
1208 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1210 if ((pin >= 16) && (pin <= 23)) {
1211 if (pirq_entries[pin-16] != -1) {
1212 if (!pirq_entries[pin-16]) {
1213 apic_printk(APIC_VERBOSE, KERN_DEBUG
1214 "disabling PIRQ%d\n", pin-16);
1216 irq = pirq_entries[pin-16];
1217 apic_printk(APIC_VERBOSE, KERN_DEBUG
1218 "using PIRQ%d -> IRQ %d\n",
1226 static inline int IO_APIC_irq_trigger(int irq)
1230 for (apic = 0; apic < nr_ioapics; apic++) {
1231 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1232 idx = find_irq_entry(apic,pin,mp_INT);
1233 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1234 return irq_trigger(idx);
1238 * nonexistent IRQs are edge default
1243 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1244 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1246 static int __assign_irq_vector(int irq)
1248 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1251 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1253 if (irq_vector[irq] > 0)
1254 return irq_vector[irq];
1256 current_vector += 8;
1257 if (current_vector == SYSCALL_VECTOR)
1258 current_vector += 8;
1260 if (current_vector >= FIRST_SYSTEM_VECTOR) {
1264 current_vector = FIRST_DEVICE_VECTOR + offset;
1267 vector = current_vector;
1268 irq_vector[irq] = vector;
1273 static int assign_irq_vector(int irq)
1275 unsigned long flags;
1278 spin_lock_irqsave(&vector_lock, flags);
1279 vector = __assign_irq_vector(irq);
1280 spin_unlock_irqrestore(&vector_lock, flags);
1284 static struct irq_chip ioapic_chip;
1286 #define IOAPIC_AUTO -1
1287 #define IOAPIC_EDGE 0
1288 #define IOAPIC_LEVEL 1
1290 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1292 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1293 trigger == IOAPIC_LEVEL)
1294 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1295 handle_fasteoi_irq, "fasteoi");
1297 irq_desc[irq].status |= IRQ_DELAYED_DISABLE;
1298 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1299 handle_edge_irq, "edge");
1301 set_intr_gate(vector, interrupt[irq]);
1304 static void __init setup_IO_APIC_irqs(void)
1306 struct IO_APIC_route_entry entry;
1307 int apic, pin, idx, irq, first_notcon = 1, vector;
1308 unsigned long flags;
1310 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1312 for (apic = 0; apic < nr_ioapics; apic++) {
1313 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1316 * add it to the IO-APIC irq-routing table:
1318 memset(&entry,0,sizeof(entry));
1320 entry.delivery_mode = INT_DELIVERY_MODE;
1321 entry.dest_mode = INT_DEST_MODE;
1322 entry.mask = 0; /* enable IRQ */
1323 entry.dest.logical.logical_dest =
1324 cpu_mask_to_apicid(TARGET_CPUS);
1326 idx = find_irq_entry(apic,pin,mp_INT);
1329 apic_printk(APIC_VERBOSE, KERN_DEBUG
1330 " IO-APIC (apicid-pin) %d-%d",
1331 mp_ioapics[apic].mpc_apicid,
1335 apic_printk(APIC_VERBOSE, ", %d-%d",
1336 mp_ioapics[apic].mpc_apicid, pin);
1340 entry.trigger = irq_trigger(idx);
1341 entry.polarity = irq_polarity(idx);
1343 if (irq_trigger(idx)) {
1348 irq = pin_2_irq(idx, apic, pin);
1350 * skip adding the timer int on secondary nodes, which causes
1351 * a small but painful rift in the time-space continuum
1353 if (multi_timer_check(apic, irq))
1356 add_pin_to_irq(irq, apic, pin);
1358 if (!apic && !IO_APIC_IRQ(irq))
1361 if (IO_APIC_IRQ(irq)) {
1362 vector = assign_irq_vector(irq);
1363 entry.vector = vector;
1364 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1366 if (!apic && (irq < 16))
1367 disable_8259A_irq(irq);
1369 spin_lock_irqsave(&ioapic_lock, flags);
1370 __ioapic_write_entry(apic, pin, entry);
1371 set_native_irq_info(irq, TARGET_CPUS);
1372 spin_unlock_irqrestore(&ioapic_lock, flags);
1377 apic_printk(APIC_VERBOSE, " not connected.\n");
1381 * Set up the 8259A-master output pin:
1383 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1385 struct IO_APIC_route_entry entry;
1387 memset(&entry,0,sizeof(entry));
1389 disable_8259A_irq(0);
1392 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1395 * We use logical delivery to get the timer IRQ
1398 entry.dest_mode = INT_DEST_MODE;
1399 entry.mask = 0; /* unmask IRQ now */
1400 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1401 entry.delivery_mode = INT_DELIVERY_MODE;
1404 entry.vector = vector;
1407 * The timer IRQ doesn't have to know that behind the
1408 * scene we have a 8259A-master in AEOI mode ...
1410 irq_desc[0].chip = &ioapic_chip;
1411 set_irq_handler(0, handle_edge_irq);
1414 * Add it to the IO-APIC irq-routing table:
1416 ioapic_write_entry(apic, pin, entry);
1418 enable_8259A_irq(0);
1421 static inline void UNEXPECTED_IO_APIC(void)
1425 void __init print_IO_APIC(void)
1428 union IO_APIC_reg_00 reg_00;
1429 union IO_APIC_reg_01 reg_01;
1430 union IO_APIC_reg_02 reg_02;
1431 union IO_APIC_reg_03 reg_03;
1432 unsigned long flags;
1434 if (apic_verbosity == APIC_QUIET)
1437 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1438 for (i = 0; i < nr_ioapics; i++)
1439 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1440 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1443 * We are a bit conservative about what we expect. We have to
1444 * know about every hardware change ASAP.
1446 printk(KERN_INFO "testing the IO APIC.......................\n");
1448 for (apic = 0; apic < nr_ioapics; apic++) {
1450 spin_lock_irqsave(&ioapic_lock, flags);
1451 reg_00.raw = io_apic_read(apic, 0);
1452 reg_01.raw = io_apic_read(apic, 1);
1453 if (reg_01.bits.version >= 0x10)
1454 reg_02.raw = io_apic_read(apic, 2);
1455 if (reg_01.bits.version >= 0x20)
1456 reg_03.raw = io_apic_read(apic, 3);
1457 spin_unlock_irqrestore(&ioapic_lock, flags);
1459 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1460 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1461 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1462 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1463 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1464 if (reg_00.bits.ID >= get_physical_broadcast())
1465 UNEXPECTED_IO_APIC();
1466 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1467 UNEXPECTED_IO_APIC();
1469 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1470 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1471 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1472 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1473 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1474 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1475 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1476 (reg_01.bits.entries != 0x2E) &&
1477 (reg_01.bits.entries != 0x3F)
1479 UNEXPECTED_IO_APIC();
1481 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1482 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1483 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1484 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1485 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1486 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1487 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1489 UNEXPECTED_IO_APIC();
1490 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1491 UNEXPECTED_IO_APIC();
1494 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1495 * but the value of reg_02 is read as the previous read register
1496 * value, so ignore it if reg_02 == reg_01.
1498 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1499 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1500 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1501 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1502 UNEXPECTED_IO_APIC();
1506 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1507 * or reg_03, but the value of reg_0[23] is read as the previous read
1508 * register value, so ignore it if reg_03 == reg_0[12].
1510 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1511 reg_03.raw != reg_01.raw) {
1512 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1513 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1514 if (reg_03.bits.__reserved_1)
1515 UNEXPECTED_IO_APIC();
1518 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1520 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1521 " Stat Dest Deli Vect: \n");
1523 for (i = 0; i <= reg_01.bits.entries; i++) {
1524 struct IO_APIC_route_entry entry;
1526 entry = ioapic_read_entry(apic, i);
1528 printk(KERN_DEBUG " %02x %03X %02X ",
1530 entry.dest.logical.logical_dest,
1531 entry.dest.physical.physical_dest
1534 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1539 entry.delivery_status,
1541 entry.delivery_mode,
1546 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1547 for (i = 0; i < NR_IRQS; i++) {
1548 struct irq_pin_list *entry = irq_2_pin + i;
1551 printk(KERN_DEBUG "IRQ%d ", i);
1553 printk("-> %d:%d", entry->apic, entry->pin);
1556 entry = irq_2_pin + entry->next;
1561 printk(KERN_INFO ".................................... done.\n");
1568 static void print_APIC_bitfield (int base)
1573 if (apic_verbosity == APIC_QUIET)
1576 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1577 for (i = 0; i < 8; i++) {
1578 v = apic_read(base + i*0x10);
1579 for (j = 0; j < 32; j++) {
1589 void /*__init*/ print_local_APIC(void * dummy)
1591 unsigned int v, ver, maxlvt;
1593 if (apic_verbosity == APIC_QUIET)
1596 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1597 smp_processor_id(), hard_smp_processor_id());
1598 v = apic_read(APIC_ID);
1599 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1600 v = apic_read(APIC_LVR);
1601 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1602 ver = GET_APIC_VERSION(v);
1603 maxlvt = get_maxlvt();
1605 v = apic_read(APIC_TASKPRI);
1606 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1608 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1609 v = apic_read(APIC_ARBPRI);
1610 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1611 v & APIC_ARBPRI_MASK);
1612 v = apic_read(APIC_PROCPRI);
1613 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1616 v = apic_read(APIC_EOI);
1617 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1618 v = apic_read(APIC_RRR);
1619 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1620 v = apic_read(APIC_LDR);
1621 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1622 v = apic_read(APIC_DFR);
1623 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1624 v = apic_read(APIC_SPIV);
1625 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1627 printk(KERN_DEBUG "... APIC ISR field:\n");
1628 print_APIC_bitfield(APIC_ISR);
1629 printk(KERN_DEBUG "... APIC TMR field:\n");
1630 print_APIC_bitfield(APIC_TMR);
1631 printk(KERN_DEBUG "... APIC IRR field:\n");
1632 print_APIC_bitfield(APIC_IRR);
1634 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1635 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1636 apic_write(APIC_ESR, 0);
1637 v = apic_read(APIC_ESR);
1638 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1641 v = apic_read(APIC_ICR);
1642 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1643 v = apic_read(APIC_ICR2);
1644 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1646 v = apic_read(APIC_LVTT);
1647 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1649 if (maxlvt > 3) { /* PC is LVT#4. */
1650 v = apic_read(APIC_LVTPC);
1651 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1653 v = apic_read(APIC_LVT0);
1654 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1655 v = apic_read(APIC_LVT1);
1656 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1658 if (maxlvt > 2) { /* ERR is LVT#3. */
1659 v = apic_read(APIC_LVTERR);
1660 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1663 v = apic_read(APIC_TMICT);
1664 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1665 v = apic_read(APIC_TMCCT);
1666 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1667 v = apic_read(APIC_TDCR);
1668 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1672 void print_all_local_APICs (void)
1674 on_each_cpu(print_local_APIC, NULL, 1, 1);
1677 void /*__init*/ print_PIC(void)
1680 unsigned long flags;
1682 if (apic_verbosity == APIC_QUIET)
1685 printk(KERN_DEBUG "\nprinting PIC contents\n");
1687 spin_lock_irqsave(&i8259A_lock, flags);
1689 v = inb(0xa1) << 8 | inb(0x21);
1690 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1692 v = inb(0xa0) << 8 | inb(0x20);
1693 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1697 v = inb(0xa0) << 8 | inb(0x20);
1701 spin_unlock_irqrestore(&i8259A_lock, flags);
1703 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1705 v = inb(0x4d1) << 8 | inb(0x4d0);
1706 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1711 static void __init enable_IO_APIC(void)
1713 union IO_APIC_reg_01 reg_01;
1714 int i8259_apic, i8259_pin;
1716 unsigned long flags;
1718 for (i = 0; i < PIN_MAP_SIZE; i++) {
1719 irq_2_pin[i].pin = -1;
1720 irq_2_pin[i].next = 0;
1723 for (i = 0; i < MAX_PIRQS; i++)
1724 pirq_entries[i] = -1;
1727 * The number of IO-APIC IRQ registers (== #pins):
1729 for (apic = 0; apic < nr_ioapics; apic++) {
1730 spin_lock_irqsave(&ioapic_lock, flags);
1731 reg_01.raw = io_apic_read(apic, 1);
1732 spin_unlock_irqrestore(&ioapic_lock, flags);
1733 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1735 for(apic = 0; apic < nr_ioapics; apic++) {
1737 /* See if any of the pins is in ExtINT mode */
1738 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1739 struct IO_APIC_route_entry entry;
1740 entry = ioapic_read_entry(apic, pin);
1743 /* If the interrupt line is enabled and in ExtInt mode
1744 * I have found the pin where the i8259 is connected.
1746 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1747 ioapic_i8259.apic = apic;
1748 ioapic_i8259.pin = pin;
1754 /* Look to see what if the MP table has reported the ExtINT */
1755 /* If we could not find the appropriate pin by looking at the ioapic
1756 * the i8259 probably is not connected the ioapic but give the
1757 * mptable a chance anyway.
1759 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1760 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1761 /* Trust the MP table if nothing is setup in the hardware */
1762 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1763 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1764 ioapic_i8259.pin = i8259_pin;
1765 ioapic_i8259.apic = i8259_apic;
1767 /* Complain if the MP table and the hardware disagree */
1768 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1769 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1771 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1775 * Do not trust the IO-APIC being empty at bootup
1781 * Not an __init, needed by the reboot code
1783 void disable_IO_APIC(void)
1786 * Clear the IO-APIC before rebooting:
1791 * If the i8259 is routed through an IOAPIC
1792 * Put that IOAPIC in virtual wire mode
1793 * so legacy interrupts can be delivered.
1795 if (ioapic_i8259.pin != -1) {
1796 struct IO_APIC_route_entry entry;
1798 memset(&entry, 0, sizeof(entry));
1799 entry.mask = 0; /* Enabled */
1800 entry.trigger = 0; /* Edge */
1802 entry.polarity = 0; /* High */
1803 entry.delivery_status = 0;
1804 entry.dest_mode = 0; /* Physical */
1805 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1807 entry.dest.physical.physical_dest =
1808 GET_APIC_ID(apic_read(APIC_ID));
1811 * Add it to the IO-APIC irq-routing table:
1813 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1815 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1819 * function to set the IO-APIC physical IDs based on the
1820 * values stored in the MPC table.
1822 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1825 #ifndef CONFIG_X86_NUMAQ
1826 static void __init setup_ioapic_ids_from_mpc(void)
1828 union IO_APIC_reg_00 reg_00;
1829 physid_mask_t phys_id_present_map;
1832 unsigned char old_id;
1833 unsigned long flags;
1836 * Don't check I/O APIC IDs for xAPIC systems. They have
1837 * no meaning without the serial APIC bus.
1839 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1840 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1843 * This is broken; anything with a real cpu count has to
1844 * circumvent this idiocy regardless.
1846 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1849 * Set the IOAPIC ID to the value stored in the MPC table.
1851 for (apic = 0; apic < nr_ioapics; apic++) {
1853 /* Read the register 0 value */
1854 spin_lock_irqsave(&ioapic_lock, flags);
1855 reg_00.raw = io_apic_read(apic, 0);
1856 spin_unlock_irqrestore(&ioapic_lock, flags);
1858 old_id = mp_ioapics[apic].mpc_apicid;
1860 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1861 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1862 apic, mp_ioapics[apic].mpc_apicid);
1863 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1865 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1869 * Sanity check, is the ID really free? Every APIC in a
1870 * system must have a unique ID or we get lots of nice
1871 * 'stuck on smp_invalidate_needed IPI wait' messages.
1873 if (check_apicid_used(phys_id_present_map,
1874 mp_ioapics[apic].mpc_apicid)) {
1875 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1876 apic, mp_ioapics[apic].mpc_apicid);
1877 for (i = 0; i < get_physical_broadcast(); i++)
1878 if (!physid_isset(i, phys_id_present_map))
1880 if (i >= get_physical_broadcast())
1881 panic("Max APIC ID exceeded!\n");
1882 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1884 physid_set(i, phys_id_present_map);
1885 mp_ioapics[apic].mpc_apicid = i;
1888 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1889 apic_printk(APIC_VERBOSE, "Setting %d in the "
1890 "phys_id_present_map\n",
1891 mp_ioapics[apic].mpc_apicid);
1892 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1897 * We need to adjust the IRQ routing table
1898 * if the ID changed.
1900 if (old_id != mp_ioapics[apic].mpc_apicid)
1901 for (i = 0; i < mp_irq_entries; i++)
1902 if (mp_irqs[i].mpc_dstapic == old_id)
1903 mp_irqs[i].mpc_dstapic
1904 = mp_ioapics[apic].mpc_apicid;
1907 * Read the right value from the MPC table and
1908 * write it into the ID register.
1910 apic_printk(APIC_VERBOSE, KERN_INFO
1911 "...changing IO-APIC physical APIC ID to %d ...",
1912 mp_ioapics[apic].mpc_apicid);
1914 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1915 spin_lock_irqsave(&ioapic_lock, flags);
1916 io_apic_write(apic, 0, reg_00.raw);
1917 spin_unlock_irqrestore(&ioapic_lock, flags);
1922 spin_lock_irqsave(&ioapic_lock, flags);
1923 reg_00.raw = io_apic_read(apic, 0);
1924 spin_unlock_irqrestore(&ioapic_lock, flags);
1925 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1926 printk("could not set ID!\n");
1928 apic_printk(APIC_VERBOSE, " ok.\n");
1932 static void __init setup_ioapic_ids_from_mpc(void) { }
1935 static int no_timer_check __initdata;
1937 static int __init notimercheck(char *s)
1942 __setup("no_timer_check", notimercheck);
1945 * There is a nasty bug in some older SMP boards, their mptable lies
1946 * about the timer IRQ. We do the following to work around the situation:
1948 * - timer IRQ defaults to IO-APIC IRQ
1949 * - if this function detects that timer IRQs are defunct, then we fall
1950 * back to ISA timer IRQs
1952 int __init timer_irq_works(void)
1954 unsigned long t1 = jiffies;
1960 /* Let ten ticks pass... */
1961 mdelay((10 * 1000) / HZ);
1964 * Expect a few ticks at least, to be sure some possible
1965 * glue logic does not lock up after one or two first
1966 * ticks in a non-ExtINT mode. Also the local APIC
1967 * might have cached one ExtINT interrupt. Finally, at
1968 * least one tick may be lost due to delays.
1970 if (jiffies - t1 > 4)
1977 * In the SMP+IOAPIC case it might happen that there are an unspecified
1978 * number of pending IRQ events unhandled. These cases are very rare,
1979 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1980 * better to do it this way as thus we do not have to be aware of
1981 * 'pending' interrupts in the IRQ path, except at this point.
1984 * Edge triggered needs to resend any interrupt
1985 * that was delayed but this is now handled in the device
1992 * Starting up a edge-triggered IO-APIC interrupt is
1993 * nasty - we need to make sure that we get the edge.
1994 * If it is already asserted for some reason, we need
1995 * return 1 to indicate that is was pending.
1997 * This is not complete - we should be able to fake
1998 * an edge even if it isn't on the 8259A...
2000 * (We do this for level-triggered IRQs too - it cannot hurt.)
2002 static unsigned int startup_ioapic_irq(unsigned int irq)
2004 int was_pending = 0;
2005 unsigned long flags;
2007 spin_lock_irqsave(&ioapic_lock, flags);
2009 disable_8259A_irq(irq);
2010 if (i8259A_irq_pending(irq))
2013 __unmask_IO_APIC_irq(irq);
2014 spin_unlock_irqrestore(&ioapic_lock, flags);
2019 static void ack_ioapic_irq(unsigned int irq)
2021 move_native_irq(irq);
2025 static void ack_ioapic_quirk_irq(unsigned int irq)
2030 move_native_irq(irq);
2032 * It appears there is an erratum which affects at least version 0x11
2033 * of I/O APIC (that's the 82093AA and cores integrated into various
2034 * chipsets). Under certain conditions a level-triggered interrupt is
2035 * erroneously delivered as edge-triggered one but the respective IRR
2036 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2037 * message but it will never arrive and further interrupts are blocked
2038 * from the source. The exact reason is so far unknown, but the
2039 * phenomenon was observed when two consecutive interrupt requests
2040 * from a given source get delivered to the same CPU and the source is
2041 * temporarily disabled in between.
2043 * A workaround is to simulate an EOI message manually. We achieve it
2044 * by setting the trigger mode to edge and then to level when the edge
2045 * trigger mode gets detected in the TMR of a local APIC for a
2046 * level-triggered interrupt. We mask the source for the time of the
2047 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2048 * The idea is from Manfred Spraul. --macro
2050 i = irq_vector[irq];
2052 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2056 if (!(v & (1 << (i & 0x1f)))) {
2057 atomic_inc(&irq_mis_count);
2058 spin_lock(&ioapic_lock);
2059 __mask_and_edge_IO_APIC_irq(irq);
2060 __unmask_and_level_IO_APIC_irq(irq);
2061 spin_unlock(&ioapic_lock);
2065 static int ioapic_retrigger_irq(unsigned int irq)
2067 send_IPI_self(irq_vector[irq]);
2072 static struct irq_chip ioapic_chip __read_mostly = {
2074 .startup = startup_ioapic_irq,
2075 .mask = mask_IO_APIC_irq,
2076 .unmask = unmask_IO_APIC_irq,
2077 .ack = ack_ioapic_irq,
2078 .eoi = ack_ioapic_quirk_irq,
2080 .set_affinity = set_ioapic_affinity_irq,
2082 .retrigger = ioapic_retrigger_irq,
2086 static inline void init_IO_APIC_traps(void)
2091 * NOTE! The local APIC isn't very good at handling
2092 * multiple interrupts at the same interrupt level.
2093 * As the interrupt level is determined by taking the
2094 * vector number and shifting that right by 4, we
2095 * want to spread these out a bit so that they don't
2096 * all fall in the same interrupt level.
2098 * Also, we've got to be careful not to trash gate
2099 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2101 for (irq = 0; irq < NR_IRQS ; irq++) {
2103 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2105 * Hmm.. We don't have an entry for this,
2106 * so default to an old-fashioned 8259
2107 * interrupt if we can..
2110 make_8259A_irq(irq);
2112 /* Strange. Oh, well.. */
2113 irq_desc[irq].chip = &no_irq_chip;
2119 * The local APIC irq-chip implementation:
2122 static void ack_apic(unsigned int irq)
2127 static void mask_lapic_irq (unsigned int irq)
2131 v = apic_read(APIC_LVT0);
2132 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2135 static void unmask_lapic_irq (unsigned int irq)
2139 v = apic_read(APIC_LVT0);
2140 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2143 static struct irq_chip lapic_chip __read_mostly = {
2144 .name = "local-APIC-edge",
2145 .mask = mask_lapic_irq,
2146 .unmask = unmask_lapic_irq,
2150 static void setup_nmi (void)
2153 * Dirty trick to enable the NMI watchdog ...
2154 * We put the 8259A master into AEOI mode and
2155 * unmask on all local APICs LVT0 as NMI.
2157 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2158 * is from Maciej W. Rozycki - so we do not have to EOI from
2159 * the NMI handler or the timer interrupt.
2161 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2163 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2165 apic_printk(APIC_VERBOSE, " done.\n");
2169 * This looks a bit hackish but it's about the only one way of sending
2170 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2171 * not support the ExtINT mode, unfortunately. We need to send these
2172 * cycles as some i82489DX-based boards have glue logic that keeps the
2173 * 8259A interrupt line asserted until INTA. --macro
2175 static inline void unlock_ExtINT_logic(void)
2178 struct IO_APIC_route_entry entry0, entry1;
2179 unsigned char save_control, save_freq_select;
2181 pin = find_isa_irq_pin(8, mp_INT);
2186 apic = find_isa_irq_apic(8, mp_INT);
2192 entry0 = ioapic_read_entry(apic, pin);
2193 clear_IO_APIC_pin(apic, pin);
2195 memset(&entry1, 0, sizeof(entry1));
2197 entry1.dest_mode = 0; /* physical delivery */
2198 entry1.mask = 0; /* unmask IRQ now */
2199 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2200 entry1.delivery_mode = dest_ExtINT;
2201 entry1.polarity = entry0.polarity;
2205 ioapic_write_entry(apic, pin, entry1);
2207 save_control = CMOS_READ(RTC_CONTROL);
2208 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2209 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2211 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2216 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2220 CMOS_WRITE(save_control, RTC_CONTROL);
2221 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2222 clear_IO_APIC_pin(apic, pin);
2224 ioapic_write_entry(apic, pin, entry0);
2227 int timer_uses_ioapic_pin_0;
2230 * This code may look a bit paranoid, but it's supposed to cooperate with
2231 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2232 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2233 * fanatically on his truly buggy board.
2235 static inline void __init check_timer(void)
2237 int apic1, pin1, apic2, pin2;
2241 * get/set the timer IRQ vector:
2243 disable_8259A_irq(0);
2244 vector = assign_irq_vector(0);
2245 set_intr_gate(vector, interrupt[0]);
2248 * Subtle, code in do_timer_interrupt() expects an AEOI
2249 * mode for the 8259A whenever interrupts are routed
2250 * through I/O APICs. Also IRQ0 has to be enabled in
2251 * the 8259A which implies the virtual wire has to be
2252 * disabled in the local APIC.
2254 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2257 if (timer_over_8254 > 0)
2258 enable_8259A_irq(0);
2260 pin1 = find_isa_irq_pin(0, mp_INT);
2261 apic1 = find_isa_irq_apic(0, mp_INT);
2262 pin2 = ioapic_i8259.pin;
2263 apic2 = ioapic_i8259.apic;
2266 timer_uses_ioapic_pin_0 = 1;
2268 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2269 vector, apic1, pin1, apic2, pin2);
2273 * Ok, does IRQ0 through the IOAPIC work?
2275 unmask_IO_APIC_irq(0);
2276 if (timer_irq_works()) {
2277 if (nmi_watchdog == NMI_IO_APIC) {
2278 disable_8259A_irq(0);
2280 enable_8259A_irq(0);
2282 if (disable_timer_pin_1 > 0)
2283 clear_IO_APIC_pin(0, pin1);
2286 clear_IO_APIC_pin(apic1, pin1);
2287 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2291 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2293 printk("\n..... (found pin %d) ...", pin2);
2295 * legacy devices should be connected to IO APIC #0
2297 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2298 if (timer_irq_works()) {
2301 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2303 add_pin_to_irq(0, apic2, pin2);
2304 if (nmi_watchdog == NMI_IO_APIC) {
2310 * Cleanup, just in case ...
2312 clear_IO_APIC_pin(apic2, pin2);
2314 printk(" failed.\n");
2316 if (nmi_watchdog == NMI_IO_APIC) {
2317 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2321 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2323 disable_8259A_irq(0);
2324 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2326 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2327 enable_8259A_irq(0);
2329 if (timer_irq_works()) {
2330 printk(" works.\n");
2333 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2334 printk(" failed.\n");
2336 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2341 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2343 unlock_ExtINT_logic();
2345 if (timer_irq_works()) {
2346 printk(" works.\n");
2349 printk(" failed :(.\n");
2350 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2351 "report. Then try booting with the 'noapic' option");
2356 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2357 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2358 * Linux doesn't really care, as it's not actually used
2359 * for any interrupt handling anyway.
2361 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2363 void __init setup_IO_APIC(void)
2368 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2370 io_apic_irqs = ~PIC_IRQS;
2372 printk("ENABLING IO-APIC IRQs\n");
2375 * Set up IO-APIC IRQ routing.
2378 setup_ioapic_ids_from_mpc();
2380 setup_IO_APIC_irqs();
2381 init_IO_APIC_traps();
2387 static int __init setup_disable_8254_timer(char *s)
2389 timer_over_8254 = -1;
2392 static int __init setup_enable_8254_timer(char *s)
2394 timer_over_8254 = 2;
2398 __setup("disable_8254_timer", setup_disable_8254_timer);
2399 __setup("enable_8254_timer", setup_enable_8254_timer);
2402 * Called after all the initialization is done. If we didnt find any
2403 * APIC bugs then we can allow the modify fast path
2406 static int __init io_apic_bug_finalize(void)
2408 if(sis_apic_bug == -1)
2413 late_initcall(io_apic_bug_finalize);
2415 struct sysfs_ioapic_data {
2416 struct sys_device dev;
2417 struct IO_APIC_route_entry entry[0];
2419 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2421 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2423 struct IO_APIC_route_entry *entry;
2424 struct sysfs_ioapic_data *data;
2427 data = container_of(dev, struct sysfs_ioapic_data, dev);
2428 entry = data->entry;
2429 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2430 entry[i] = ioapic_read_entry(dev->id, i);
2435 static int ioapic_resume(struct sys_device *dev)
2437 struct IO_APIC_route_entry *entry;
2438 struct sysfs_ioapic_data *data;
2439 unsigned long flags;
2440 union IO_APIC_reg_00 reg_00;
2443 data = container_of(dev, struct sysfs_ioapic_data, dev);
2444 entry = data->entry;
2446 spin_lock_irqsave(&ioapic_lock, flags);
2447 reg_00.raw = io_apic_read(dev->id, 0);
2448 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2449 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2450 io_apic_write(dev->id, 0, reg_00.raw);
2452 spin_unlock_irqrestore(&ioapic_lock, flags);
2453 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2454 ioapic_write_entry(dev->id, i, entry[i]);
2459 static struct sysdev_class ioapic_sysdev_class = {
2460 set_kset_name("ioapic"),
2461 .suspend = ioapic_suspend,
2462 .resume = ioapic_resume,
2465 static int __init ioapic_init_sysfs(void)
2467 struct sys_device * dev;
2468 int i, size, error = 0;
2470 error = sysdev_class_register(&ioapic_sysdev_class);
2474 for (i = 0; i < nr_ioapics; i++ ) {
2475 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2476 * sizeof(struct IO_APIC_route_entry);
2477 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2478 if (!mp_ioapic_data[i]) {
2479 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2482 memset(mp_ioapic_data[i], 0, size);
2483 dev = &mp_ioapic_data[i]->dev;
2485 dev->cls = &ioapic_sysdev_class;
2486 error = sysdev_register(dev);
2488 kfree(mp_ioapic_data[i]);
2489 mp_ioapic_data[i] = NULL;
2490 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2498 device_initcall(ioapic_init_sysfs);
2501 * Dynamic irq allocate and deallocation
2503 int create_irq(void)
2505 /* Allocate an unused irq */
2506 int irq, new, vector;
2507 unsigned long flags;
2510 spin_lock_irqsave(&vector_lock, flags);
2511 for (new = (NR_IRQS - 1); new >= 0; new--) {
2512 if (platform_legacy_irq(new))
2514 if (irq_vector[new] != 0)
2516 vector = __assign_irq_vector(new);
2517 if (likely(vector > 0))
2521 spin_unlock_irqrestore(&vector_lock, flags);
2524 set_intr_gate(vector, interrupt[irq]);
2525 dynamic_irq_init(irq);
2530 void destroy_irq(unsigned int irq)
2532 unsigned long flags;
2534 dynamic_irq_cleanup(irq);
2536 spin_lock_irqsave(&vector_lock, flags);
2537 irq_vector[irq] = 0;
2538 spin_unlock_irqrestore(&vector_lock, flags);
2542 * MSI mesage composition
2544 #ifdef CONFIG_PCI_MSI
2545 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2550 vector = assign_irq_vector(irq);
2552 dest = cpu_mask_to_apicid(TARGET_CPUS);
2554 msg->address_hi = MSI_ADDR_BASE_HI;
2557 ((INT_DEST_MODE == 0) ?
2558 MSI_ADDR_DEST_MODE_PHYSICAL:
2559 MSI_ADDR_DEST_MODE_LOGICAL) |
2560 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2561 MSI_ADDR_REDIRECTION_CPU:
2562 MSI_ADDR_REDIRECTION_LOWPRI) |
2563 MSI_ADDR_DEST_ID(dest);
2566 MSI_DATA_TRIGGER_EDGE |
2567 MSI_DATA_LEVEL_ASSERT |
2568 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2569 MSI_DATA_DELIVERY_FIXED:
2570 MSI_DATA_DELIVERY_LOWPRI) |
2571 MSI_DATA_VECTOR(vector);
2577 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2584 cpus_and(tmp, mask, cpu_online_map);
2585 if (cpus_empty(tmp))
2588 vector = assign_irq_vector(irq);
2592 dest = cpu_mask_to_apicid(mask);
2594 read_msi_msg(irq, &msg);
2596 msg.data &= ~MSI_DATA_VECTOR_MASK;
2597 msg.data |= MSI_DATA_VECTOR(vector);
2598 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2599 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2601 write_msi_msg(irq, &msg);
2602 set_native_irq_info(irq, mask);
2604 #endif /* CONFIG_SMP */
2607 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2608 * which implement the MSI or MSI-X Capability Structure.
2610 static struct irq_chip msi_chip = {
2612 .unmask = unmask_msi_irq,
2613 .mask = mask_msi_irq,
2614 .ack = ack_ioapic_irq,
2616 .set_affinity = set_msi_irq_affinity,
2618 .retrigger = ioapic_retrigger_irq,
2621 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
2625 ret = msi_compose_msg(dev, irq, &msg);
2629 write_msi_msg(irq, &msg);
2631 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2637 void arch_teardown_msi_irq(unsigned int irq)
2642 #endif /* CONFIG_PCI_MSI */
2645 * Hypertransport interrupt support
2647 #ifdef CONFIG_HT_IRQ
2651 static void target_ht_irq(unsigned int irq, unsigned int dest)
2653 struct ht_irq_msg msg;
2654 fetch_ht_irq_msg(irq, &msg);
2656 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2657 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2659 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2660 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2662 write_ht_irq_msg(irq, &msg);
2665 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2670 cpus_and(tmp, mask, cpu_online_map);
2671 if (cpus_empty(tmp))
2674 cpus_and(mask, tmp, CPU_MASK_ALL);
2676 dest = cpu_mask_to_apicid(mask);
2678 target_ht_irq(irq, dest);
2679 set_native_irq_info(irq, mask);
2683 static struct irq_chip ht_irq_chip = {
2685 .mask = mask_ht_irq,
2686 .unmask = unmask_ht_irq,
2687 .ack = ack_ioapic_irq,
2689 .set_affinity = set_ht_irq_affinity,
2691 .retrigger = ioapic_retrigger_irq,
2694 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2698 vector = assign_irq_vector(irq);
2700 struct ht_irq_msg msg;
2705 cpu_set(vector >> 8, tmp);
2706 dest = cpu_mask_to_apicid(tmp);
2708 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2712 HT_IRQ_LOW_DEST_ID(dest) |
2713 HT_IRQ_LOW_VECTOR(vector) |
2714 ((INT_DEST_MODE == 0) ?
2715 HT_IRQ_LOW_DM_PHYSICAL :
2716 HT_IRQ_LOW_DM_LOGICAL) |
2717 HT_IRQ_LOW_RQEOI_EDGE |
2718 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2719 HT_IRQ_LOW_MT_FIXED :
2720 HT_IRQ_LOW_MT_ARBITRATED) |
2721 HT_IRQ_LOW_IRQ_MASKED;
2723 write_ht_irq_msg(irq, &msg);
2725 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2726 handle_edge_irq, "edge");
2730 #endif /* CONFIG_HT_IRQ */
2732 /* --------------------------------------------------------------------------
2733 ACPI-based IOAPIC Configuration
2734 -------------------------------------------------------------------------- */
2738 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2740 union IO_APIC_reg_00 reg_00;
2741 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2743 unsigned long flags;
2747 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2748 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2749 * supports up to 16 on one shared APIC bus.
2751 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2752 * advantage of new APIC bus architecture.
2755 if (physids_empty(apic_id_map))
2756 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2758 spin_lock_irqsave(&ioapic_lock, flags);
2759 reg_00.raw = io_apic_read(ioapic, 0);
2760 spin_unlock_irqrestore(&ioapic_lock, flags);
2762 if (apic_id >= get_physical_broadcast()) {
2763 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2764 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2765 apic_id = reg_00.bits.ID;
2769 * Every APIC in a system must have a unique ID or we get lots of nice
2770 * 'stuck on smp_invalidate_needed IPI wait' messages.
2772 if (check_apicid_used(apic_id_map, apic_id)) {
2774 for (i = 0; i < get_physical_broadcast(); i++) {
2775 if (!check_apicid_used(apic_id_map, i))
2779 if (i == get_physical_broadcast())
2780 panic("Max apic_id exceeded!\n");
2782 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2783 "trying %d\n", ioapic, apic_id, i);
2788 tmp = apicid_to_cpu_present(apic_id);
2789 physids_or(apic_id_map, apic_id_map, tmp);
2791 if (reg_00.bits.ID != apic_id) {
2792 reg_00.bits.ID = apic_id;
2794 spin_lock_irqsave(&ioapic_lock, flags);
2795 io_apic_write(ioapic, 0, reg_00.raw);
2796 reg_00.raw = io_apic_read(ioapic, 0);
2797 spin_unlock_irqrestore(&ioapic_lock, flags);
2800 if (reg_00.bits.ID != apic_id) {
2801 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2806 apic_printk(APIC_VERBOSE, KERN_INFO
2807 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2813 int __init io_apic_get_version (int ioapic)
2815 union IO_APIC_reg_01 reg_01;
2816 unsigned long flags;
2818 spin_lock_irqsave(&ioapic_lock, flags);
2819 reg_01.raw = io_apic_read(ioapic, 1);
2820 spin_unlock_irqrestore(&ioapic_lock, flags);
2822 return reg_01.bits.version;
2826 int __init io_apic_get_redir_entries (int ioapic)
2828 union IO_APIC_reg_01 reg_01;
2829 unsigned long flags;
2831 spin_lock_irqsave(&ioapic_lock, flags);
2832 reg_01.raw = io_apic_read(ioapic, 1);
2833 spin_unlock_irqrestore(&ioapic_lock, flags);
2835 return reg_01.bits.entries;
2839 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2841 struct IO_APIC_route_entry entry;
2842 unsigned long flags;
2844 if (!IO_APIC_IRQ(irq)) {
2845 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2851 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2852 * Note that we mask (disable) IRQs now -- these get enabled when the
2853 * corresponding device driver registers for this IRQ.
2856 memset(&entry,0,sizeof(entry));
2858 entry.delivery_mode = INT_DELIVERY_MODE;
2859 entry.dest_mode = INT_DEST_MODE;
2860 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2861 entry.trigger = edge_level;
2862 entry.polarity = active_high_low;
2866 * IRQs < 16 are already in the irq_2_pin[] map
2869 add_pin_to_irq(irq, ioapic, pin);
2871 entry.vector = assign_irq_vector(irq);
2873 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2874 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2875 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2876 edge_level, active_high_low);
2878 ioapic_register_intr(irq, entry.vector, edge_level);
2880 if (!ioapic && (irq < 16))
2881 disable_8259A_irq(irq);
2883 spin_lock_irqsave(&ioapic_lock, flags);
2884 __ioapic_write_entry(ioapic, pin, entry);
2885 set_native_irq_info(irq, TARGET_CPUS);
2886 spin_unlock_irqrestore(&ioapic_lock, flags);
2891 #endif /* CONFIG_ACPI */
2893 static int __init parse_disable_timer_pin_1(char *arg)
2895 disable_timer_pin_1 = 1;
2898 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2900 static int __init parse_enable_timer_pin_1(char *arg)
2902 disable_timer_pin_1 = -1;
2905 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2907 static int __init parse_noapic(char *arg)
2909 /* disable IO-APIC */
2910 disable_ioapic_setup();
2913 early_param("noapic", parse_noapic);