arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/pci.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/timer.h>
  40 #include <asm/i8259.h>
  41 #include <asm/nmi.h>
  42 #include <asm/msidef.h>
  43
  44 #include <mach_apic.h>
  45 #include <mach_apicdef.h>
  46
  47 #include "io_ports.h"
  48
  49 int (*ioapic_renumber_irq)(int ioapic, int irq);
  50 atomic_t irq_mis_count;
  51
  52 /* Where if anywhere is the i8259 connect in external int mode */
  53 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  54
  55 static DEFINE_SPINLOCK(ioapic_lock);
  56 static DEFINE_SPINLOCK(vector_lock);
  57
  58 int timer_over_8254 __initdata = 1;
  59
  60 /*
  61  *      Is the SiS APIC rmw bug present ?
  62  *      -1 = don't know, 0 = no, 1 = yes
  63  */
  64 int sis_apic_bug = -1;
  65
  66 /*
  67  * # of IRQ routing registers
  68  */
  69 int nr_ioapic_registers[MAX_IO_APICS];
  70
  71 static int disable_timer_pin_1 __initdata;
  72
  73 /*
  74  * Rough estimation of how many shared IRQs there are, can
  75  * be changed anytime.
  76  */
  77 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  79
  80 /*
  81  * This is performance-critical, we want to do it O(1)
  82  *
  83  * the indexing order of this array favors 1:1 mappings
  84  * between pins and IRQs.
  85  */
  86
  87 static struct irq_pin_list {
  88         int apic, pin, next;
  89 } irq_2_pin[PIN_MAP_SIZE];
  90
  91 union entry_union {
  92         struct { u32 w1, w2; };
  93         struct IO_APIC_route_entry entry;
  94 };
  95
  96 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
  97 {
  98         union entry_union eu;
  99         unsigned long flags;
 100         spin_lock_irqsave(&ioapic_lock, flags);
 101         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 102         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 103         spin_unlock_irqrestore(&ioapic_lock, flags);
 104         return eu.entry;
 105 }
 106
 107 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 108 {
 109         unsigned long flags;
 110         union entry_union eu;
 111         eu.entry = e;
 112         spin_lock_irqsave(&ioapic_lock, flags);
 113         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 114         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 115         spin_unlock_irqrestore(&ioapic_lock, flags);
 116 }
 117
 118 /*
 119  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 120  * shared ISA-space IRQs, so we have to support them. We are super
 121  * fast in the common case, and fast for shared ISA-space IRQs.
 122  */
 123 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 124 {
 125         static int first_free_entry = NR_IRQS;
 126         struct irq_pin_list *entry = irq_2_pin + irq;
 127
 128         while (entry->next)
 129                 entry = irq_2_pin + entry->next;
 130
 131         if (entry->pin != -1) {
 132                 entry->next = first_free_entry;
 133                 entry = irq_2_pin + entry->next;
 134                 if (++first_free_entry >= PIN_MAP_SIZE)
 135                         panic("io_apic.c: whoops");
 136         }
 137         entry->apic = apic;
 138         entry->pin = pin;
 139 }
 140
 141 /*
 142  * Reroute an IRQ to a different pin.
 143  */
 144 static void __init replace_pin_at_irq(unsigned int irq,
 145                                       int oldapic, int oldpin,
 146                                       int newapic, int newpin)
 147 {
 148         struct irq_pin_list *entry = irq_2_pin + irq;
 149
 150         while (1) {
 151                 if (entry->apic == oldapic && entry->pin == oldpin) {
 152                         entry->apic = newapic;
 153                         entry->pin = newpin;
 154                 }
 155                 if (!entry->next)
 156                         break;
 157                 entry = irq_2_pin + entry->next;
 158         }
 159 }
 160
 161 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 162 {
 163         struct irq_pin_list *entry = irq_2_pin + irq;
 164         unsigned int pin, reg;
 165
 166         for (;;) {
 167                 pin = entry->pin;
 168                 if (pin == -1)
 169                         break;
 170                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 171                 reg &= ~disable;
 172                 reg |= enable;
 173                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 174                 if (!entry->next)
 175                         break;
 176                 entry = irq_2_pin + entry->next;
 177         }
 178 }
 179
 180 /* mask = 1 */
 181 static void __mask_IO_APIC_irq (unsigned int irq)
 182 {
 183         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 184 }
 185
 186 /* mask = 0 */
 187 static void __unmask_IO_APIC_irq (unsigned int irq)
 188 {
 189         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 190 }
 191
 192 /* mask = 1, trigger = 0 */
 193 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 194 {
 195         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 196 }
 197
 198 /* mask = 0, trigger = 1 */
 199 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 200 {
 201         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 202 }
 203
 204 static void mask_IO_APIC_irq (unsigned int irq)
 205 {
 206         unsigned long flags;
 207
 208         spin_lock_irqsave(&ioapic_lock, flags);
 209         __mask_IO_APIC_irq(irq);
 210         spin_unlock_irqrestore(&ioapic_lock, flags);
 211 }
 212
 213 static void unmask_IO_APIC_irq (unsigned int irq)
 214 {
 215         unsigned long flags;
 216
 217         spin_lock_irqsave(&ioapic_lock, flags);
 218         __unmask_IO_APIC_irq(irq);
 219         spin_unlock_irqrestore(&ioapic_lock, flags);
 220 }
 221
 222 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 223 {
 224         struct IO_APIC_route_entry entry;
 225
 226         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 227         entry = ioapic_read_entry(apic, pin);
 228         if (entry.delivery_mode == dest_SMI)
 229                 return;
 230
 231         /*
 232          * Disable it in the IO-APIC irq-routing table:
 233          */
 234         memset(&entry, 0, sizeof(entry));
 235         entry.mask = 1;
 236         ioapic_write_entry(apic, pin, entry);
 237 }
 238
 239 static void clear_IO_APIC (void)
 240 {
 241         int apic, pin;
 242
 243         for (apic = 0; apic < nr_ioapics; apic++)
 244                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 245                         clear_IO_APIC_pin(apic, pin);
 246 }
 247
 248 #ifdef CONFIG_SMP
 249 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 250 {
 251         unsigned long flags;
 252         int pin;
 253         struct irq_pin_list *entry = irq_2_pin + irq;
 254         unsigned int apicid_value;
 255         cpumask_t tmp;
 256
 257         cpus_and(tmp, cpumask, cpu_online_map);
 258         if (cpus_empty(tmp))
 259                 tmp = TARGET_CPUS;
 260
 261         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 262
 263         apicid_value = cpu_mask_to_apicid(cpumask);
 264         /* Prepare to do the io_apic_write */
 265         apicid_value = apicid_value << 24;
 266         spin_lock_irqsave(&ioapic_lock, flags);
 267         for (;;) {
 268                 pin = entry->pin;
 269                 if (pin == -1)
 270                         break;
 271                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 272                 if (!entry->next)
 273                         break;
 274                 entry = irq_2_pin + entry->next;
 275         }
 276         set_native_irq_info(irq, cpumask);
 277         spin_unlock_irqrestore(&ioapic_lock, flags);
 278 }
 279
 280 #if defined(CONFIG_IRQBALANCE)
 281 # include <asm/processor.h>     /* kernel_thread() */
 282 # include <linux/kernel_stat.h> /* kstat */
 283 # include <linux/slab.h>                /* kmalloc() */
 284 # include <linux/timer.h>       /* time_after() */
 285
 286 #ifdef CONFIG_BALANCED_IRQ_DEBUG
 287 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 288 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 289 # else
 290 #  define TDprintk(x...)
 291 #  define Dprintk(x...)
 292 # endif
 293
 294 #define IRQBALANCE_CHECK_ARCH -999
 295 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 296 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 297 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 298 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 299
 300 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 301 static int physical_balance __read_mostly;
 302 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 303
 304 static struct irq_cpu_info {
 305         unsigned long * last_irq;
 306         unsigned long * irq_delta;
 307         unsigned long irq;
 308 } irq_cpu_data[NR_CPUS];
 309
 310 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 311 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 312 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 313
 314 #define IDLE_ENOUGH(cpu,now) \
 315         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 316
 317 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 318
 319 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 320
 321 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 322         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 323 };
 324
 325 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 326 {
 327         balance_irq_affinity[irq] = mask;
 328 }
 329
 330 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 331                         unsigned long now, int direction)
 332 {
 333         int search_idle = 1;
 334         int cpu = curr_cpu;
 335
 336         goto inside;
 337
 338         do {
 339                 if (unlikely(cpu == curr_cpu))
 340                         search_idle = 0;
 341 inside:
 342                 if (direction == 1) {
 343                         cpu++;
 344                         if (cpu >= NR_CPUS)
 345                                 cpu = 0;
 346                 } else {
 347                         cpu--;
 348                         if (cpu == -1)
 349                                 cpu = NR_CPUS-1;
 350                 }
 351         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 352                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 353
 354         return cpu;
 355 }
 356
 357 static inline void balance_irq(int cpu, int irq)
 358 {
 359         unsigned long now = jiffies;
 360         cpumask_t allowed_mask;
 361         unsigned int new_cpu;
 362
 363         if (irqbalance_disabled)
 364                 return;
 365
 366         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 367         new_cpu = move(cpu, allowed_mask, now, 1);
 368         if (cpu != new_cpu) {
 369                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 370         }
 371 }
 372
 373 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 374 {
 375         int i, j;
 376         Dprintk("Rotating IRQs among CPUs.\n");
 377         for_each_online_cpu(i) {
 378                 for (j = 0; j < NR_IRQS; j++) {
 379                         if (!irq_desc[j].action)
 380                                 continue;
 381                         /* Is it a significant load ?  */
 382                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 383                                                 useful_load_threshold)
 384                                 continue;
 385                         balance_irq(i, j);
 386                 }
 387         }
 388         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 389                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 390         return;
 391 }
 392
 393 static void do_irq_balance(void)
 394 {
 395         int i, j;
 396         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 397         unsigned long move_this_load = 0;
 398         int max_loaded = 0, min_loaded = 0;
 399         int load;
 400         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 401         int selected_irq;
 402         int tmp_loaded, first_attempt = 1;
 403         unsigned long tmp_cpu_irq;
 404         unsigned long imbalance = 0;
 405         cpumask_t allowed_mask, target_cpu_mask, tmp;
 406
 407         for_each_possible_cpu(i) {
 408                 int package_index;
 409                 CPU_IRQ(i) = 0;
 410                 if (!cpu_online(i))
 411                         continue;
 412                 package_index = CPU_TO_PACKAGEINDEX(i);
 413                 for (j = 0; j < NR_IRQS; j++) {
 414                         unsigned long value_now, delta;
 415                         /* Is this an active IRQ? */
 416                         if (!irq_desc[j].action)
 417                                 continue;
 418                         if ( package_index == i )
 419                                 IRQ_DELTA(package_index,j) = 0;
 420                         /* Determine the total count per processor per IRQ */
 421                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 422
 423                         /* Determine the activity per processor per IRQ */
 424                         delta = value_now - LAST_CPU_IRQ(i,j);
 425
 426                         /* Update last_cpu_irq[][] for the next time */
 427                         LAST_CPU_IRQ(i,j) = value_now;
 428
 429                         /* Ignore IRQs whose rate is less than the clock */
 430                         if (delta < useful_load_threshold)
 431                                 continue;
 432                         /* update the load for the processor or package total */
 433                         IRQ_DELTA(package_index,j) += delta;
 434
 435                         /* Keep track of the higher numbered sibling as well */
 436                         if (i != package_index)
 437                                 CPU_IRQ(i) += delta;
 438                         /*
 439                          * We have sibling A and sibling B in the package
 440                          *
 441                          * cpu_irq[A] = load for cpu A + load for cpu B
 442                          * cpu_irq[B] = load for cpu B
 443                          */
 444                         CPU_IRQ(package_index) += delta;
 445                 }
 446         }
 447         /* Find the least loaded processor package */
 448         for_each_online_cpu(i) {
 449                 if (i != CPU_TO_PACKAGEINDEX(i))
 450                         continue;
 451                 if (min_cpu_irq > CPU_IRQ(i)) {
 452                         min_cpu_irq = CPU_IRQ(i);
 453                         min_loaded = i;
 454                 }
 455         }
 456         max_cpu_irq = ULONG_MAX;
 457
 458 tryanothercpu:
 459         /* Look for heaviest loaded processor.
 460          * We may come back to get the next heaviest loaded processor.
 461          * Skip processors with trivial loads.
 462          */
 463         tmp_cpu_irq = 0;
 464         tmp_loaded = -1;
 465         for_each_online_cpu(i) {
 466                 if (i != CPU_TO_PACKAGEINDEX(i))
 467                         continue;
 468                 if (max_cpu_irq <= CPU_IRQ(i))
 469                         continue;
 470                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 471                         tmp_cpu_irq = CPU_IRQ(i);
 472                         tmp_loaded = i;
 473                 }
 474         }
 475
 476         if (tmp_loaded == -1) {
 477          /* In the case of small number of heavy interrupt sources,
 478           * loading some of the cpus too much. We use Ingo's original
 479           * approach to rotate them around.
 480           */
 481                 if (!first_attempt && imbalance >= useful_load_threshold) {
 482                         rotate_irqs_among_cpus(useful_load_threshold);
 483                         return;
 484                 }
 485                 goto not_worth_the_effort;
 486         }
 487
 488         first_attempt = 0;              /* heaviest search */
 489         max_cpu_irq = tmp_cpu_irq;      /* load */
 490         max_loaded = tmp_loaded;        /* processor */
 491         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 492
 493         Dprintk("max_loaded cpu = %d\n", max_loaded);
 494         Dprintk("min_loaded cpu = %d\n", min_loaded);
 495         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 496         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 497         Dprintk("load imbalance = %lu\n", imbalance);
 498
 499         /* if imbalance is less than approx 10% of max load, then
 500          * observe diminishing returns action. - quit
 501          */
 502         if (imbalance < (max_cpu_irq >> 3)) {
 503                 Dprintk("Imbalance too trivial\n");
 504                 goto not_worth_the_effort;
 505         }
 506
 507 tryanotherirq:
 508         /* if we select an IRQ to move that can't go where we want, then
 509          * see if there is another one to try.
 510          */
 511         move_this_load = 0;
 512         selected_irq = -1;
 513         for (j = 0; j < NR_IRQS; j++) {
 514                 /* Is this an active IRQ? */
 515                 if (!irq_desc[j].action)
 516                         continue;
 517                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 518                         continue;
 519                 /* Try to find the IRQ that is closest to the imbalance
 520                  * without going over.
 521                  */
 522                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 523                         move_this_load = IRQ_DELTA(max_loaded,j);
 524                         selected_irq = j;
 525                 }
 526         }
 527         if (selected_irq == -1) {
 528                 goto tryanothercpu;
 529         }
 530
 531         imbalance = move_this_load;
 532
 533         /* For physical_balance case, we accumlated both load
 534          * values in the one of the siblings cpu_irq[],
 535          * to use the same code for physical and logical processors
 536          * as much as possible.
 537          *
 538          * NOTE: the cpu_irq[] array holds the sum of the load for
 539          * sibling A and sibling B in the slot for the lowest numbered
 540          * sibling (A), _AND_ the load for sibling B in the slot for
 541          * the higher numbered sibling.
 542          *
 543          * We seek the least loaded sibling by making the comparison
 544          * (A+B)/2 vs B
 545          */
 546         load = CPU_IRQ(min_loaded) >> 1;
 547         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 548                 if (load > CPU_IRQ(j)) {
 549                         /* This won't change cpu_sibling_map[min_loaded] */
 550                         load = CPU_IRQ(j);
 551                         min_loaded = j;
 552                 }
 553         }
 554
 555         cpus_and(allowed_mask,
 556                 cpu_online_map,
 557                 balance_irq_affinity[selected_irq]);
 558         target_cpu_mask = cpumask_of_cpu(min_loaded);
 559         cpus_and(tmp, target_cpu_mask, allowed_mask);
 560
 561         if (!cpus_empty(tmp)) {
 562
 563                 Dprintk("irq = %d moved to cpu = %d\n",
 564                                 selected_irq, min_loaded);
 565                 /* mark for change destination */
 566                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 567
 568                 /* Since we made a change, come back sooner to
 569                  * check for more variation.
 570                  */
 571                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 572                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 573                 return;
 574         }
 575         goto tryanotherirq;
 576
 577 not_worth_the_effort:
 578         /*
 579          * if we did not find an IRQ to move, then adjust the time interval
 580          * upward
 581          */
 582         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 583                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 584         Dprintk("IRQ worth rotating not found\n");
 585         return;
 586 }
 587
 588 static int balanced_irq(void *unused)
 589 {
 590         int i;
 591         unsigned long prev_balance_time = jiffies;
 592         long time_remaining = balanced_irq_interval;
 593
 594         daemonize("kirqd");
 595
 596         /* push everything to CPU 0 to give us a starting point.  */
 597         for (i = 0 ; i < NR_IRQS ; i++) {
 598                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 599                 set_pending_irq(i, cpumask_of_cpu(0));
 600         }
 601
 602         for ( ; ; ) {
 603                 time_remaining = schedule_timeout_interruptible(time_remaining);
 604                 try_to_freeze();
 605                 if (time_after(jiffies,
 606                                 prev_balance_time+balanced_irq_interval)) {
 607                         preempt_disable();
 608                         do_irq_balance();
 609                         prev_balance_time = jiffies;
 610                         time_remaining = balanced_irq_interval;
 611                         preempt_enable();
 612                 }
 613         }
 614         return 0;
 615 }
 616
 617 static int __init balanced_irq_init(void)
 618 {
 619         int i;
 620         struct cpuinfo_x86 *c;
 621         cpumask_t tmp;
 622
 623         cpus_shift_right(tmp, cpu_online_map, 2);
 624         c = &boot_cpu_data;
 625         /* When not overwritten by the command line ask subarchitecture. */
 626         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 627                 irqbalance_disabled = NO_BALANCE_IRQ;
 628         if (irqbalance_disabled)
 629                 return 0;
 630
 631          /* disable irqbalance completely if there is only one processor online */
 632         if (num_online_cpus() < 2) {
 633                 irqbalance_disabled = 1;
 634                 return 0;
 635         }
 636         /*
 637          * Enable physical balance only if more than 1 physical processor
 638          * is present
 639          */
 640         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 641                 physical_balance = 1;
 642
 643         for_each_online_cpu(i) {
 644                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 645                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 646                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 647                         printk(KERN_ERR "balanced_irq_init: out of memory");
 648                         goto failed;
 649                 }
 650                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 651                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 652         }
 653
 654         printk(KERN_INFO "Starting balanced_irq\n");
 655         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 656                 return 0;
 657         else
 658                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 659 failed:
 660         for_each_possible_cpu(i) {
 661                 kfree(irq_cpu_data[i].irq_delta);
 662                 irq_cpu_data[i].irq_delta = NULL;
 663                 kfree(irq_cpu_data[i].last_irq);
 664                 irq_cpu_data[i].last_irq = NULL;
 665         }
 666         return 0;
 667 }
 668
 669 int __init irqbalance_disable(char *str)
 670 {
 671         irqbalance_disabled = 1;
 672         return 1;
 673 }
 674
 675 __setup("noirqbalance", irqbalance_disable);
 676
 677 late_initcall(balanced_irq_init);
 678 #endif /* CONFIG_IRQBALANCE */
 679 #endif /* CONFIG_SMP */
 680
 681 #ifndef CONFIG_SMP
 682 void fastcall send_IPI_self(int vector)
 683 {
 684         unsigned int cfg;
 685
 686         /*
 687          * Wait for idle.
 688          */
 689         apic_wait_icr_idle();
 690         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 691         /*
 692          * Send the IPI. The write to APIC_ICR fires this off.
 693          */
 694         apic_write_around(APIC_ICR, cfg);
 695 }
 696 #endif /* !CONFIG_SMP */
 697
 698
 699 /*
 700  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 701  * specific CPU-side IRQs.
 702  */
 703
 704 #define MAX_PIRQS 8
 705 static int pirq_entries [MAX_PIRQS];
 706 static int pirqs_enabled;
 707 int skip_ioapic_setup;
 708
 709 static int __init ioapic_setup(char *str)
 710 {
 711         skip_ioapic_setup = 1;
 712         return 1;
 713 }
 714
 715 __setup("noapic", ioapic_setup);
 716
 717 static int __init ioapic_pirq_setup(char *str)
 718 {
 719         int i, max;
 720         int ints[MAX_PIRQS+1];
 721
 722         get_options(str, ARRAY_SIZE(ints), ints);
 723
 724         for (i = 0; i < MAX_PIRQS; i++)
 725                 pirq_entries[i] = -1;
 726
 727         pirqs_enabled = 1;
 728         apic_printk(APIC_VERBOSE, KERN_INFO
 729                         "PIRQ redirection, working around broken MP-BIOS.\n");
 730         max = MAX_PIRQS;
 731         if (ints[0] < MAX_PIRQS)
 732                 max = ints[0];
 733
 734         for (i = 0; i < max; i++) {
 735                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 736                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 737                 /*
 738                  * PIRQs are mapped upside down, usually.
 739                  */
 740                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 741         }
 742         return 1;
 743 }
 744
 745 __setup("pirq=", ioapic_pirq_setup);
 746
 747 /*
 748  * Find the IRQ entry number of a certain pin.
 749  */
 750 static int find_irq_entry(int apic, int pin, int type)
 751 {
 752         int i;
 753
 754         for (i = 0; i < mp_irq_entries; i++)
 755                 if (mp_irqs[i].mpc_irqtype == type &&
 756                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 757                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 758                     mp_irqs[i].mpc_dstirq == pin)
 759                         return i;
 760
 761         return -1;
 762 }
 763
 764 /*
 765  * Find the pin to which IRQ[irq] (ISA) is connected
 766  */
 767 static int __init find_isa_irq_pin(int irq, int type)
 768 {
 769         int i;
 770
 771         for (i = 0; i < mp_irq_entries; i++) {
 772                 int lbus = mp_irqs[i].mpc_srcbus;
 773
 774                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 775                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 776                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 777                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 778                     ) &&
 779                     (mp_irqs[i].mpc_irqtype == type) &&
 780                     (mp_irqs[i].mpc_srcbusirq == irq))
 781
 782                         return mp_irqs[i].mpc_dstirq;
 783         }
 784         return -1;
 785 }
 786
 787 static int __init find_isa_irq_apic(int irq, int type)
 788 {
 789         int i;
 790
 791         for (i = 0; i < mp_irq_entries; i++) {
 792                 int lbus = mp_irqs[i].mpc_srcbus;
 793
 794                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 795                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 796                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 797                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 798                     ) &&
 799                     (mp_irqs[i].mpc_irqtype == type) &&
 800                     (mp_irqs[i].mpc_srcbusirq == irq))
 801                         break;
 802         }
 803         if (i < mp_irq_entries) {
 804                 int apic;
 805                 for(apic = 0; apic < nr_ioapics; apic++) {
 806                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 807                                 return apic;
 808                 }
 809         }
 810
 811         return -1;
 812 }
 813
 814 /*
 815  * Find a specific PCI IRQ entry.
 816  * Not an __init, possibly needed by modules
 817  */
 818 static int pin_2_irq(int idx, int apic, int pin);
 819
 820 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 821 {
 822         int apic, i, best_guess = -1;
 823
 824         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 825                 "slot:%d, pin:%d.\n", bus, slot, pin);
 826         if (mp_bus_id_to_pci_bus[bus] == -1) {
 827                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 828                 return -1;
 829         }
 830         for (i = 0; i < mp_irq_entries; i++) {
 831                 int lbus = mp_irqs[i].mpc_srcbus;
 832
 833                 for (apic = 0; apic < nr_ioapics; apic++)
 834                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 835                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 836                                 break;
 837
 838                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 839                     !mp_irqs[i].mpc_irqtype &&
 840                     (bus == lbus) &&
 841                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 842                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 843
 844                         if (!(apic || IO_APIC_IRQ(irq)))
 845                                 continue;
 846
 847                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 848                                 return irq;
 849                         /*
 850                          * Use the first all-but-pin matching entry as a
 851                          * best-guess fuzzy result for broken mptables.
 852                          */
 853                         if (best_guess < 0)
 854                                 best_guess = irq;
 855                 }
 856         }
 857         return best_guess;
 858 }
 859 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 860
 861 /*
 862  * This function currently is only a helper for the i386 smp boot process where
 863  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 864  * so mask in all cases should simply be TARGET_CPUS
 865  */
 866 #ifdef CONFIG_SMP
 867 void __init setup_ioapic_dest(void)
 868 {
 869         int pin, ioapic, irq, irq_entry;
 870
 871         if (skip_ioapic_setup == 1)
 872                 return;
 873
 874         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 875                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 876                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 877                         if (irq_entry == -1)
 878                                 continue;
 879                         irq = pin_2_irq(irq_entry, ioapic, pin);
 880                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 881                 }
 882
 883         }
 884 }
 885 #endif
 886
 887 /*
 888  * EISA Edge/Level control register, ELCR
 889  */
 890 static int EISA_ELCR(unsigned int irq)
 891 {
 892         if (irq < 16) {
 893                 unsigned int port = 0x4d0 + (irq >> 3);
 894                 return (inb(port) >> (irq & 7)) & 1;
 895         }
 896         apic_printk(APIC_VERBOSE, KERN_INFO
 897                         "Broken MPtable reports ISA irq %d\n", irq);
 898         return 0;
 899 }
 900
 901 /* EISA interrupts are always polarity zero and can be edge or level
 902  * trigger depending on the ELCR value.  If an interrupt is listed as
 903  * EISA conforming in the MP table, that means its trigger type must
 904  * be read in from the ELCR */
 905
 906 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 907 #define default_EISA_polarity(idx)      (0)
 908
 909 /* ISA interrupts are always polarity zero edge triggered,
 910  * when listed as conforming in the MP table. */
 911
 912 #define default_ISA_trigger(idx)        (0)
 913 #define default_ISA_polarity(idx)       (0)
 914
 915 /* PCI interrupts are always polarity one level triggered,
 916  * when listed as conforming in the MP table. */
 917
 918 #define default_PCI_trigger(idx)        (1)
 919 #define default_PCI_polarity(idx)       (1)
 920
 921 /* MCA interrupts are always polarity zero level triggered,
 922  * when listed as conforming in the MP table. */
 923
 924 #define default_MCA_trigger(idx)        (1)
 925 #define default_MCA_polarity(idx)       (0)
 926
 927 /* NEC98 interrupts are always polarity zero edge triggered,
 928  * when listed as conforming in the MP table. */
 929
 930 #define default_NEC98_trigger(idx)     (0)
 931 #define default_NEC98_polarity(idx)    (0)
 932
 933 static int __init MPBIOS_polarity(int idx)
 934 {
 935         int bus = mp_irqs[idx].mpc_srcbus;
 936         int polarity;
 937
 938         /*
 939          * Determine IRQ line polarity (high active or low active):
 940          */
 941         switch (mp_irqs[idx].mpc_irqflag & 3)
 942         {
 943                 case 0: /* conforms, ie. bus-type dependent polarity */
 944                 {
 945                         switch (mp_bus_id_to_type[bus])
 946                         {
 947                                 case MP_BUS_ISA: /* ISA pin */
 948                                 {
 949                                         polarity = default_ISA_polarity(idx);
 950                                         break;
 951                                 }
 952                                 case MP_BUS_EISA: /* EISA pin */
 953                                 {
 954                                         polarity = default_EISA_polarity(idx);
 955                                         break;
 956                                 }
 957                                 case MP_BUS_PCI: /* PCI pin */
 958                                 {
 959                                         polarity = default_PCI_polarity(idx);
 960                                         break;
 961                                 }
 962                                 case MP_BUS_MCA: /* MCA pin */
 963                                 {
 964                                         polarity = default_MCA_polarity(idx);
 965                                         break;
 966                                 }
 967                                 case MP_BUS_NEC98: /* NEC 98 pin */
 968                                 {
 969                                         polarity = default_NEC98_polarity(idx);
 970                                         break;
 971                                 }
 972                                 default:
 973                                 {
 974                                         printk(KERN_WARNING "broken BIOS!!\n");
 975                                         polarity = 1;
 976                                         break;
 977                                 }
 978                         }
 979                         break;
 980                 }
 981                 case 1: /* high active */
 982                 {
 983                         polarity = 0;
 984                         break;
 985                 }
 986                 case 2: /* reserved */
 987                 {
 988                         printk(KERN_WARNING "broken BIOS!!\n");
 989                         polarity = 1;
 990                         break;
 991                 }
 992                 case 3: /* low active */
 993                 {
 994                         polarity = 1;
 995                         break;
 996                 }
 997                 default: /* invalid */
 998                 {
 999                         printk(KERN_WARNING "broken BIOS!!\n");
1000                         polarity = 1;
1001                         break;
1002                 }
1003         }
1004         return polarity;
1005 }
1006
1007 static int MPBIOS_trigger(int idx)
1008 {
1009         int bus = mp_irqs[idx].mpc_srcbus;
1010         int trigger;
1011
1012         /*
1013          * Determine IRQ trigger mode (edge or level sensitive):
1014          */
1015         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1016         {
1017                 case 0: /* conforms, ie. bus-type dependent */
1018                 {
1019                         switch (mp_bus_id_to_type[bus])
1020                         {
1021                                 case MP_BUS_ISA: /* ISA pin */
1022                                 {
1023                                         trigger = default_ISA_trigger(idx);
1024                                         break;
1025                                 }
1026                                 case MP_BUS_EISA: /* EISA pin */
1027                                 {
1028                                         trigger = default_EISA_trigger(idx);
1029                                         break;
1030                                 }
1031                                 case MP_BUS_PCI: /* PCI pin */
1032                                 {
1033                                         trigger = default_PCI_trigger(idx);
1034                                         break;
1035                                 }
1036                                 case MP_BUS_MCA: /* MCA pin */
1037                                 {
1038                                         trigger = default_MCA_trigger(idx);
1039                                         break;
1040                                 }
1041                                 case MP_BUS_NEC98: /* NEC 98 pin */
1042                                 {
1043                                         trigger = default_NEC98_trigger(idx);
1044                                         break;
1045                                 }
1046                                 default:
1047                                 {
1048                                         printk(KERN_WARNING "broken BIOS!!\n");
1049                                         trigger = 1;
1050                                         break;
1051                                 }
1052                         }
1053                         break;
1054                 }
1055                 case 1: /* edge */
1056                 {
1057                         trigger = 0;
1058                         break;
1059                 }
1060                 case 2: /* reserved */
1061                 {
1062                         printk(KERN_WARNING "broken BIOS!!\n");
1063                         trigger = 1;
1064                         break;
1065                 }
1066                 case 3: /* level */
1067                 {
1068                         trigger = 1;
1069                         break;
1070                 }
1071                 default: /* invalid */
1072                 {
1073                         printk(KERN_WARNING "broken BIOS!!\n");
1074                         trigger = 0;
1075                         break;
1076                 }
1077         }
1078         return trigger;
1079 }
1080
1081 static inline int irq_polarity(int idx)
1082 {
1083         return MPBIOS_polarity(idx);
1084 }
1085
1086 static inline int irq_trigger(int idx)
1087 {
1088         return MPBIOS_trigger(idx);
1089 }
1090
1091 static int pin_2_irq(int idx, int apic, int pin)
1092 {
1093         int irq, i;
1094         int bus = mp_irqs[idx].mpc_srcbus;
1095
1096         /*
1097          * Debugging check, we are in big trouble if this message pops up!
1098          */
1099         if (mp_irqs[idx].mpc_dstirq != pin)
1100                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1101
1102         switch (mp_bus_id_to_type[bus])
1103         {
1104                 case MP_BUS_ISA: /* ISA pin */
1105                 case MP_BUS_EISA:
1106                 case MP_BUS_MCA:
1107                 case MP_BUS_NEC98:
1108                 {
1109                         irq = mp_irqs[idx].mpc_srcbusirq;
1110                         break;
1111                 }
1112                 case MP_BUS_PCI: /* PCI pin */
1113                 {
1114                         /*
1115                          * PCI IRQs are mapped in order
1116                          */
1117                         i = irq = 0;
1118                         while (i < apic)
1119                                 irq += nr_ioapic_registers[i++];
1120                         irq += pin;
1121
1122                         /*
1123                          * For MPS mode, so far only needed by ES7000 platform
1124                          */
1125                         if (ioapic_renumber_irq)
1126                                 irq = ioapic_renumber_irq(apic, irq);
1127
1128                         break;
1129                 }
1130                 default:
1131                 {
1132                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1133                         irq = 0;
1134                         break;
1135                 }
1136         }
1137
1138         /*
1139          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1140          */
1141         if ((pin >= 16) && (pin <= 23)) {
1142                 if (pirq_entries[pin-16] != -1) {
1143                         if (!pirq_entries[pin-16]) {
1144                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1145                                                 "disabling PIRQ%d\n", pin-16);
1146                         } else {
1147                                 irq = pirq_entries[pin-16];
1148                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1149                                                 "using PIRQ%d -> IRQ %d\n",
1150                                                 pin-16, irq);
1151                         }
1152                 }
1153         }
1154         return irq;
1155 }
1156
1157 static inline int IO_APIC_irq_trigger(int irq)
1158 {
1159         int apic, idx, pin;
1160
1161         for (apic = 0; apic < nr_ioapics; apic++) {
1162                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1163                         idx = find_irq_entry(apic,pin,mp_INT);
1164                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1165                                 return irq_trigger(idx);
1166                 }
1167         }
1168         /*
1169          * nonexistent IRQs are edge default
1170          */
1171         return 0;
1172 }
1173
1174 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1175 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1176
1177 static int __assign_irq_vector(int irq)
1178 {
1179         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1180         int vector;
1181
1182         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1183
1184         if (IO_APIC_VECTOR(irq) > 0)
1185                 return IO_APIC_VECTOR(irq);
1186
1187         current_vector += 8;
1188         if (current_vector == SYSCALL_VECTOR)
1189                 current_vector += 8;
1190
1191         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1192                 offset++;
1193                 if (!(offset % 8))
1194                         return -ENOSPC;
1195                 current_vector = FIRST_DEVICE_VECTOR + offset;
1196         }
1197
1198         vector = current_vector;
1199         IO_APIC_VECTOR(irq) = vector;
1200
1201         return vector;
1202 }
1203
1204 static int assign_irq_vector(int irq)
1205 {
1206         unsigned long flags;
1207         int vector;
1208
1209         spin_lock_irqsave(&vector_lock, flags);
1210         vector = __assign_irq_vector(irq);
1211         spin_unlock_irqrestore(&vector_lock, flags);
1212
1213         return vector;
1214 }
1215 static struct irq_chip ioapic_chip;
1216
1217 #define IOAPIC_AUTO     -1
1218 #define IOAPIC_EDGE     0
1219 #define IOAPIC_LEVEL    1
1220
1221 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1222 {
1223         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1224                         trigger == IOAPIC_LEVEL)
1225                 set_irq_chip_and_handler(irq, &ioapic_chip,
1226                                          handle_fasteoi_irq);
1227         else
1228                 set_irq_chip_and_handler(irq, &ioapic_chip,
1229                                          handle_edge_irq);
1230         set_intr_gate(vector, interrupt[irq]);
1231 }
1232
1233 static void __init setup_IO_APIC_irqs(void)
1234 {
1235         struct IO_APIC_route_entry entry;
1236         int apic, pin, idx, irq, first_notcon = 1, vector;
1237         unsigned long flags;
1238
1239         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1240
1241         for (apic = 0; apic < nr_ioapics; apic++) {
1242         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1243
1244                 /*
1245                  * add it to the IO-APIC irq-routing table:
1246                  */
1247                 memset(&entry,0,sizeof(entry));
1248
1249                 entry.delivery_mode = INT_DELIVERY_MODE;
1250                 entry.dest_mode = INT_DEST_MODE;
1251                 entry.mask = 0;                         /* enable IRQ */
1252                 entry.dest.logical.logical_dest =
1253                                         cpu_mask_to_apicid(TARGET_CPUS);
1254
1255                 idx = find_irq_entry(apic,pin,mp_INT);
1256                 if (idx == -1) {
1257                         if (first_notcon) {
1258                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1259                                                 " IO-APIC (apicid-pin) %d-%d",
1260                                                 mp_ioapics[apic].mpc_apicid,
1261                                                 pin);
1262                                 first_notcon = 0;
1263                         } else
1264                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1265                                         mp_ioapics[apic].mpc_apicid, pin);
1266                         continue;
1267                 }
1268
1269                 entry.trigger = irq_trigger(idx);
1270                 entry.polarity = irq_polarity(idx);
1271
1272                 if (irq_trigger(idx)) {
1273                         entry.trigger = 1;
1274                         entry.mask = 1;
1275                 }
1276
1277                 irq = pin_2_irq(idx, apic, pin);
1278                 /*
1279                  * skip adding the timer int on secondary nodes, which causes
1280                  * a small but painful rift in the time-space continuum
1281                  */
1282                 if (multi_timer_check(apic, irq))
1283                         continue;
1284                 else
1285                         add_pin_to_irq(irq, apic, pin);
1286
1287                 if (!apic && !IO_APIC_IRQ(irq))
1288                         continue;
1289
1290                 if (IO_APIC_IRQ(irq)) {
1291                         vector = assign_irq_vector(irq);
1292                         entry.vector = vector;
1293                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1294
1295                         if (!apic && (irq < 16))
1296                                 disable_8259A_irq(irq);
1297                 }
1298                 ioapic_write_entry(apic, pin, entry);
1299                 spin_lock_irqsave(&ioapic_lock, flags);
1300                 set_native_irq_info(irq, TARGET_CPUS);
1301                 spin_unlock_irqrestore(&ioapic_lock, flags);
1302         }
1303         }
1304
1305         if (!first_notcon)
1306                 apic_printk(APIC_VERBOSE, " not connected.\n");
1307 }
1308
1309 /*
1310  * Set up the 8259A-master output pin:
1311  */
1312 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1313 {
1314         struct IO_APIC_route_entry entry;
1315
1316         memset(&entry,0,sizeof(entry));
1317
1318         disable_8259A_irq(0);
1319
1320         /* mask LVT0 */
1321         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1322
1323         /*
1324          * We use logical delivery to get the timer IRQ
1325          * to the first CPU.
1326          */
1327         entry.dest_mode = INT_DEST_MODE;
1328         entry.mask = 0;                                 /* unmask IRQ now */
1329         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1330         entry.delivery_mode = INT_DELIVERY_MODE;
1331         entry.polarity = 0;
1332         entry.trigger = 0;
1333         entry.vector = vector;
1334
1335         /*
1336          * The timer IRQ doesn't have to know that behind the
1337          * scene we have a 8259A-master in AEOI mode ...
1338          */
1339         irq_desc[0].chip = &ioapic_chip;
1340         set_irq_handler(0, handle_edge_irq);
1341
1342         /*
1343          * Add it to the IO-APIC irq-routing table:
1344          */
1345         ioapic_write_entry(apic, pin, entry);
1346
1347         enable_8259A_irq(0);
1348 }
1349
1350 static inline void UNEXPECTED_IO_APIC(void)
1351 {
1352 }
1353
1354 void __init print_IO_APIC(void)
1355 {
1356         int apic, i;
1357         union IO_APIC_reg_00 reg_00;
1358         union IO_APIC_reg_01 reg_01;
1359         union IO_APIC_reg_02 reg_02;
1360         union IO_APIC_reg_03 reg_03;
1361         unsigned long flags;
1362
1363         if (apic_verbosity == APIC_QUIET)
1364                 return;
1365
1366         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1367         for (i = 0; i < nr_ioapics; i++)
1368                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1369                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1370
1371         /*
1372          * We are a bit conservative about what we expect.  We have to
1373          * know about every hardware change ASAP.
1374          */
1375         printk(KERN_INFO "testing the IO APIC.......................\n");
1376
1377         for (apic = 0; apic < nr_ioapics; apic++) {
1378
1379         spin_lock_irqsave(&ioapic_lock, flags);
1380         reg_00.raw = io_apic_read(apic, 0);
1381         reg_01.raw = io_apic_read(apic, 1);
1382         if (reg_01.bits.version >= 0x10)
1383                 reg_02.raw = io_apic_read(apic, 2);
1384         if (reg_01.bits.version >= 0x20)
1385                 reg_03.raw = io_apic_read(apic, 3);
1386         spin_unlock_irqrestore(&ioapic_lock, flags);
1387
1388         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1389         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1390         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1391         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1392         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1393         if (reg_00.bits.ID >= get_physical_broadcast())
1394                 UNEXPECTED_IO_APIC();
1395         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1396                 UNEXPECTED_IO_APIC();
1397
1398         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1399         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1400         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1401                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1402                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1403                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1404                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1405                 (reg_01.bits.entries != 0x2E) &&
1406                 (reg_01.bits.entries != 0x3F)
1407         )
1408                 UNEXPECTED_IO_APIC();
1409
1410         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1411         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1412         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1413                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1414                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1415                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1416                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1417         )
1418                 UNEXPECTED_IO_APIC();
1419         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1420                 UNEXPECTED_IO_APIC();
1421
1422         /*
1423          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1424          * but the value of reg_02 is read as the previous read register
1425          * value, so ignore it if reg_02 == reg_01.
1426          */
1427         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1428                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1429                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1430                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1431                         UNEXPECTED_IO_APIC();
1432         }
1433
1434         /*
1435          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1436          * or reg_03, but the value of reg_0[23] is read as the previous read
1437          * register value, so ignore it if reg_03 == reg_0[12].
1438          */
1439         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1440             reg_03.raw != reg_01.raw) {
1441                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1442                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1443                 if (reg_03.bits.__reserved_1)
1444                         UNEXPECTED_IO_APIC();
1445         }
1446
1447         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1448
1449         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1450                           " Stat Dest Deli Vect:   \n");
1451
1452         for (i = 0; i <= reg_01.bits.entries; i++) {
1453                 struct IO_APIC_route_entry entry;
1454
1455                 entry = ioapic_read_entry(apic, i);
1456
1457                 printk(KERN_DEBUG " %02x %03X %02X  ",
1458                         i,
1459                         entry.dest.logical.logical_dest,
1460                         entry.dest.physical.physical_dest
1461                 );
1462
1463                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1464                         entry.mask,
1465                         entry.trigger,
1466                         entry.irr,
1467                         entry.polarity,
1468                         entry.delivery_status,
1469                         entry.dest_mode,
1470                         entry.delivery_mode,
1471                         entry.vector
1472                 );
1473         }
1474         }
1475         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1476         for (i = 0; i < NR_IRQS; i++) {
1477                 struct irq_pin_list *entry = irq_2_pin + i;
1478                 if (entry->pin < 0)
1479                         continue;
1480                 printk(KERN_DEBUG "IRQ%d ", i);
1481                 for (;;) {
1482                         printk("-> %d:%d", entry->apic, entry->pin);
1483                         if (!entry->next)
1484                                 break;
1485                         entry = irq_2_pin + entry->next;
1486                 }
1487                 printk("\n");
1488         }
1489
1490         printk(KERN_INFO ".................................... done.\n");
1491
1492         return;
1493 }
1494
1495 #if 0
1496
1497 static void print_APIC_bitfield (int base)
1498 {
1499         unsigned int v;
1500         int i, j;
1501
1502         if (apic_verbosity == APIC_QUIET)
1503                 return;
1504
1505         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1506         for (i = 0; i < 8; i++) {
1507                 v = apic_read(base + i*0x10);
1508                 for (j = 0; j < 32; j++) {
1509                         if (v & (1<<j))
1510                                 printk("1");
1511                         else
1512                                 printk("0");
1513                 }
1514                 printk("\n");
1515         }
1516 }
1517
1518 void /*__init*/ print_local_APIC(void * dummy)
1519 {
1520         unsigned int v, ver, maxlvt;
1521
1522         if (apic_verbosity == APIC_QUIET)
1523                 return;
1524
1525         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1526                 smp_processor_id(), hard_smp_processor_id());
1527         v = apic_read(APIC_ID);
1528         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1529         v = apic_read(APIC_LVR);
1530         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1531         ver = GET_APIC_VERSION(v);
1532         maxlvt = get_maxlvt();
1533
1534         v = apic_read(APIC_TASKPRI);
1535         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1536
1537         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1538                 v = apic_read(APIC_ARBPRI);
1539                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1540                         v & APIC_ARBPRI_MASK);
1541                 v = apic_read(APIC_PROCPRI);
1542                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1543         }
1544
1545         v = apic_read(APIC_EOI);
1546         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1547         v = apic_read(APIC_RRR);
1548         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1549         v = apic_read(APIC_LDR);
1550         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1551         v = apic_read(APIC_DFR);
1552         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1553         v = apic_read(APIC_SPIV);
1554         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1555
1556         printk(KERN_DEBUG "... APIC ISR field:\n");
1557         print_APIC_bitfield(APIC_ISR);
1558         printk(KERN_DEBUG "... APIC TMR field:\n");
1559         print_APIC_bitfield(APIC_TMR);
1560         printk(KERN_DEBUG "... APIC IRR field:\n");
1561         print_APIC_bitfield(APIC_IRR);
1562
1563         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1564                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1565                         apic_write(APIC_ESR, 0);
1566                 v = apic_read(APIC_ESR);
1567                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1568         }
1569
1570         v = apic_read(APIC_ICR);
1571         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1572         v = apic_read(APIC_ICR2);
1573         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1574
1575         v = apic_read(APIC_LVTT);
1576         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1577
1578         if (maxlvt > 3) {                       /* PC is LVT#4. */
1579                 v = apic_read(APIC_LVTPC);
1580                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1581         }
1582         v = apic_read(APIC_LVT0);
1583         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1584         v = apic_read(APIC_LVT1);
1585         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1586
1587         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1588                 v = apic_read(APIC_LVTERR);
1589                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1590         }
1591
1592         v = apic_read(APIC_TMICT);
1593         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1594         v = apic_read(APIC_TMCCT);
1595         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1596         v = apic_read(APIC_TDCR);
1597         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1598         printk("\n");
1599 }
1600
1601 void print_all_local_APICs (void)
1602 {
1603         on_each_cpu(print_local_APIC, NULL, 1, 1);
1604 }
1605
1606 void /*__init*/ print_PIC(void)
1607 {
1608         unsigned int v;
1609         unsigned long flags;
1610
1611         if (apic_verbosity == APIC_QUIET)
1612                 return;
1613
1614         printk(KERN_DEBUG "\nprinting PIC contents\n");
1615
1616         spin_lock_irqsave(&i8259A_lock, flags);
1617
1618         v = inb(0xa1) << 8 | inb(0x21);
1619         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1620
1621         v = inb(0xa0) << 8 | inb(0x20);
1622         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1623
1624         outb(0x0b,0xa0);
1625         outb(0x0b,0x20);
1626         v = inb(0xa0) << 8 | inb(0x20);
1627         outb(0x0a,0xa0);
1628         outb(0x0a,0x20);
1629
1630         spin_unlock_irqrestore(&i8259A_lock, flags);
1631
1632         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1633
1634         v = inb(0x4d1) << 8 | inb(0x4d0);
1635         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1636 }
1637
1638 #endif  /*  0  */
1639
1640 static void __init enable_IO_APIC(void)
1641 {
1642         union IO_APIC_reg_01 reg_01;
1643         int i8259_apic, i8259_pin;
1644         int i, apic;
1645         unsigned long flags;
1646
1647         for (i = 0; i < PIN_MAP_SIZE; i++) {
1648                 irq_2_pin[i].pin = -1;
1649                 irq_2_pin[i].next = 0;
1650         }
1651         if (!pirqs_enabled)
1652                 for (i = 0; i < MAX_PIRQS; i++)
1653                         pirq_entries[i] = -1;
1654
1655         /*
1656          * The number of IO-APIC IRQ registers (== #pins):
1657          */
1658         for (apic = 0; apic < nr_ioapics; apic++) {
1659                 spin_lock_irqsave(&ioapic_lock, flags);
1660                 reg_01.raw = io_apic_read(apic, 1);
1661                 spin_unlock_irqrestore(&ioapic_lock, flags);
1662                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1663         }
1664         for(apic = 0; apic < nr_ioapics; apic++) {
1665                 int pin;
1666                 /* See if any of the pins is in ExtINT mode */
1667                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1668                         struct IO_APIC_route_entry entry;
1669                         entry = ioapic_read_entry(apic, pin);
1670
1671
1672                         /* If the interrupt line is enabled and in ExtInt mode
1673                          * I have found the pin where the i8259 is connected.
1674                          */
1675                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1676                                 ioapic_i8259.apic = apic;
1677                                 ioapic_i8259.pin  = pin;
1678                                 goto found_i8259;
1679                         }
1680                 }
1681         }
1682  found_i8259:
1683         /* Look to see what if the MP table has reported the ExtINT */
1684         /* If we could not find the appropriate pin by looking at the ioapic
1685          * the i8259 probably is not connected the ioapic but give the
1686          * mptable a chance anyway.
1687          */
1688         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1689         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1690         /* Trust the MP table if nothing is setup in the hardware */
1691         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1692                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1693                 ioapic_i8259.pin  = i8259_pin;
1694                 ioapic_i8259.apic = i8259_apic;
1695         }
1696         /* Complain if the MP table and the hardware disagree */
1697         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1698                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1699         {
1700                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1701         }
1702
1703         /*
1704          * Do not trust the IO-APIC being empty at bootup
1705          */
1706         clear_IO_APIC();
1707 }
1708
1709 /*
1710  * Not an __init, needed by the reboot code
1711  */
1712 void disable_IO_APIC(void)
1713 {
1714         /*
1715          * Clear the IO-APIC before rebooting:
1716          */
1717         clear_IO_APIC();
1718
1719         /*
1720          * If the i8259 is routed through an IOAPIC
1721          * Put that IOAPIC in virtual wire mode
1722          * so legacy interrupts can be delivered.
1723          */
1724         if (ioapic_i8259.pin != -1) {
1725                 struct IO_APIC_route_entry entry;
1726
1727                 memset(&entry, 0, sizeof(entry));
1728                 entry.mask            = 0; /* Enabled */
1729                 entry.trigger         = 0; /* Edge */
1730                 entry.irr             = 0;
1731                 entry.polarity        = 0; /* High */
1732                 entry.delivery_status = 0;
1733                 entry.dest_mode       = 0; /* Physical */
1734                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1735                 entry.vector          = 0;
1736                 entry.dest.physical.physical_dest =
1737                                         GET_APIC_ID(apic_read(APIC_ID));
1738
1739                 /*
1740                  * Add it to the IO-APIC irq-routing table:
1741                  */
1742                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1743         }
1744         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1745 }
1746
1747 /*
1748  * function to set the IO-APIC physical IDs based on the
1749  * values stored in the MPC table.
1750  *
1751  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1752  */
1753
1754 #ifndef CONFIG_X86_NUMAQ
1755 static void __init setup_ioapic_ids_from_mpc(void)
1756 {
1757         union IO_APIC_reg_00 reg_00;
1758         physid_mask_t phys_id_present_map;
1759         int apic;
1760         int i;
1761         unsigned char old_id;
1762         unsigned long flags;
1763
1764         /*
1765          * Don't check I/O APIC IDs for xAPIC systems.  They have
1766          * no meaning without the serial APIC bus.
1767          */
1768         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1769                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1770                 return;
1771         /*
1772          * This is broken; anything with a real cpu count has to
1773          * circumvent this idiocy regardless.
1774          */
1775         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1776
1777         /*
1778          * Set the IOAPIC ID to the value stored in the MPC table.
1779          */
1780         for (apic = 0; apic < nr_ioapics; apic++) {
1781
1782                 /* Read the register 0 value */
1783                 spin_lock_irqsave(&ioapic_lock, flags);
1784                 reg_00.raw = io_apic_read(apic, 0);
1785                 spin_unlock_irqrestore(&ioapic_lock, flags);
1786
1787                 old_id = mp_ioapics[apic].mpc_apicid;
1788
1789                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1790                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1791                                 apic, mp_ioapics[apic].mpc_apicid);
1792                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1793                                 reg_00.bits.ID);
1794                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1795                 }
1796
1797                 /*
1798                  * Sanity check, is the ID really free? Every APIC in a
1799                  * system must have a unique ID or we get lots of nice
1800                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1801                  */
1802                 if (check_apicid_used(phys_id_present_map,
1803                                         mp_ioapics[apic].mpc_apicid)) {
1804                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1805                                 apic, mp_ioapics[apic].mpc_apicid);
1806                         for (i = 0; i < get_physical_broadcast(); i++)
1807                                 if (!physid_isset(i, phys_id_present_map))
1808                                         break;
1809                         if (i >= get_physical_broadcast())
1810                                 panic("Max APIC ID exceeded!\n");
1811                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1812                                 i);
1813                         physid_set(i, phys_id_present_map);
1814                         mp_ioapics[apic].mpc_apicid = i;
1815                 } else {
1816                         physid_mask_t tmp;
1817                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1818                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1819                                         "phys_id_present_map\n",
1820                                         mp_ioapics[apic].mpc_apicid);
1821                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1822                 }
1823
1824
1825                 /*
1826                  * We need to adjust the IRQ routing table
1827                  * if the ID changed.
1828                  */
1829                 if (old_id != mp_ioapics[apic].mpc_apicid)
1830                         for (i = 0; i < mp_irq_entries; i++)
1831                                 if (mp_irqs[i].mpc_dstapic == old_id)
1832                                         mp_irqs[i].mpc_dstapic
1833                                                 = mp_ioapics[apic].mpc_apicid;
1834
1835                 /*
1836                  * Read the right value from the MPC table and
1837                  * write it into the ID register.
1838                  */
1839                 apic_printk(APIC_VERBOSE, KERN_INFO
1840                         "...changing IO-APIC physical APIC ID to %d ...",
1841                         mp_ioapics[apic].mpc_apicid);
1842
1843                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1844                 spin_lock_irqsave(&ioapic_lock, flags);
1845                 io_apic_write(apic, 0, reg_00.raw);
1846                 spin_unlock_irqrestore(&ioapic_lock, flags);
1847
1848                 /*
1849                  * Sanity check
1850                  */
1851                 spin_lock_irqsave(&ioapic_lock, flags);
1852                 reg_00.raw = io_apic_read(apic, 0);
1853                 spin_unlock_irqrestore(&ioapic_lock, flags);
1854                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1855                         printk("could not set ID!\n");
1856                 else
1857                         apic_printk(APIC_VERBOSE, " ok.\n");
1858         }
1859 }
1860 #else
1861 static void __init setup_ioapic_ids_from_mpc(void) { }
1862 #endif
1863
1864 /*
1865  * There is a nasty bug in some older SMP boards, their mptable lies
1866  * about the timer IRQ. We do the following to work around the situation:
1867  *
1868  *      - timer IRQ defaults to IO-APIC IRQ
1869  *      - if this function detects that timer IRQs are defunct, then we fall
1870  *        back to ISA timer IRQs
1871  */
1872 static int __init timer_irq_works(void)
1873 {
1874         unsigned long t1 = jiffies;
1875
1876         local_irq_enable();
1877         /* Let ten ticks pass... */
1878         mdelay((10 * 1000) / HZ);
1879
1880         /*
1881          * Expect a few ticks at least, to be sure some possible
1882          * glue logic does not lock up after one or two first
1883          * ticks in a non-ExtINT mode.  Also the local APIC
1884          * might have cached one ExtINT interrupt.  Finally, at
1885          * least one tick may be lost due to delays.
1886          */
1887         if (jiffies - t1 > 4)
1888                 return 1;
1889
1890         return 0;
1891 }
1892
1893 /*
1894  * In the SMP+IOAPIC case it might happen that there are an unspecified
1895  * number of pending IRQ events unhandled. These cases are very rare,
1896  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1897  * better to do it this way as thus we do not have to be aware of
1898  * 'pending' interrupts in the IRQ path, except at this point.
1899  */
1900 /*
1901  * Edge triggered needs to resend any interrupt
1902  * that was delayed but this is now handled in the device
1903  * independent code.
1904  */
1905
1906 /*
1907  * Startup quirk:
1908  *
1909  * Starting up a edge-triggered IO-APIC interrupt is
1910  * nasty - we need to make sure that we get the edge.
1911  * If it is already asserted for some reason, we need
1912  * return 1 to indicate that is was pending.
1913  *
1914  * This is not complete - we should be able to fake
1915  * an edge even if it isn't on the 8259A...
1916  *
1917  * (We do this for level-triggered IRQs too - it cannot hurt.)
1918  */
1919 static unsigned int startup_ioapic_irq(unsigned int irq)
1920 {
1921         int was_pending = 0;
1922         unsigned long flags;
1923
1924         spin_lock_irqsave(&ioapic_lock, flags);
1925         if (irq < 16) {
1926                 disable_8259A_irq(irq);
1927                 if (i8259A_irq_pending(irq))
1928                         was_pending = 1;
1929         }
1930         __unmask_IO_APIC_irq(irq);
1931         spin_unlock_irqrestore(&ioapic_lock, flags);
1932
1933         return was_pending;
1934 }
1935
1936 static void ack_ioapic_irq(unsigned int irq)
1937 {
1938         move_native_irq(irq);
1939         ack_APIC_irq();
1940 }
1941
1942 static void ack_ioapic_quirk_irq(unsigned int irq)
1943 {
1944         unsigned long v;
1945         int i;
1946
1947         move_native_irq(irq);
1948 /*
1949  * It appears there is an erratum which affects at least version 0x11
1950  * of I/O APIC (that's the 82093AA and cores integrated into various
1951  * chipsets).  Under certain conditions a level-triggered interrupt is
1952  * erroneously delivered as edge-triggered one but the respective IRR
1953  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1954  * message but it will never arrive and further interrupts are blocked
1955  * from the source.  The exact reason is so far unknown, but the
1956  * phenomenon was observed when two consecutive interrupt requests
1957  * from a given source get delivered to the same CPU and the source is
1958  * temporarily disabled in between.
1959  *
1960  * A workaround is to simulate an EOI message manually.  We achieve it
1961  * by setting the trigger mode to edge and then to level when the edge
1962  * trigger mode gets detected in the TMR of a local APIC for a
1963  * level-triggered interrupt.  We mask the source for the time of the
1964  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1965  * The idea is from Manfred Spraul.  --macro
1966  */
1967         i = IO_APIC_VECTOR(irq);
1968
1969         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1970
1971         ack_APIC_irq();
1972
1973         if (!(v & (1 << (i & 0x1f)))) {
1974                 atomic_inc(&irq_mis_count);
1975                 spin_lock(&ioapic_lock);
1976                 __mask_and_edge_IO_APIC_irq(irq);
1977                 __unmask_and_level_IO_APIC_irq(irq);
1978                 spin_unlock(&ioapic_lock);
1979         }
1980 }
1981
1982 static int ioapic_retrigger_irq(unsigned int irq)
1983 {
1984         send_IPI_self(IO_APIC_VECTOR(irq));
1985
1986         return 1;
1987 }
1988
1989 static struct irq_chip ioapic_chip __read_mostly = {
1990         .name           = "IO-APIC",
1991         .startup        = startup_ioapic_irq,
1992         .mask           = mask_IO_APIC_irq,
1993         .unmask         = unmask_IO_APIC_irq,
1994         .ack            = ack_ioapic_irq,
1995         .eoi            = ack_ioapic_quirk_irq,
1996 #ifdef CONFIG_SMP
1997         .set_affinity   = set_ioapic_affinity_irq,
1998 #endif
1999         .retrigger      = ioapic_retrigger_irq,
2000 };
2001
2002
2003 static inline void init_IO_APIC_traps(void)
2004 {
2005         int irq;
2006
2007         /*
2008          * NOTE! The local APIC isn't very good at handling
2009          * multiple interrupts at the same interrupt level.
2010          * As the interrupt level is determined by taking the
2011          * vector number and shifting that right by 4, we
2012          * want to spread these out a bit so that they don't
2013          * all fall in the same interrupt level.
2014          *
2015          * Also, we've got to be careful not to trash gate
2016          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2017          */
2018         for (irq = 0; irq < NR_IRQS ; irq++) {
2019                 int tmp = irq;
2020                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2021                         /*
2022                          * Hmm.. We don't have an entry for this,
2023                          * so default to an old-fashioned 8259
2024                          * interrupt if we can..
2025                          */
2026                         if (irq < 16)
2027                                 make_8259A_irq(irq);
2028                         else
2029                                 /* Strange. Oh, well.. */
2030                                 irq_desc[irq].chip = &no_irq_chip;
2031                 }
2032         }
2033 }
2034
2035 /*
2036  * The local APIC irq-chip implementation:
2037  */
2038
2039 static void ack_apic(unsigned int irq)
2040 {
2041         ack_APIC_irq();
2042 }
2043
2044 static void mask_lapic_irq (unsigned int irq)
2045 {
2046         unsigned long v;
2047
2048         v = apic_read(APIC_LVT0);
2049         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2050 }
2051
2052 static void unmask_lapic_irq (unsigned int irq)
2053 {
2054         unsigned long v;
2055
2056         v = apic_read(APIC_LVT0);
2057         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2058 }
2059
2060 static struct irq_chip lapic_chip __read_mostly = {
2061         .name           = "local-APIC-edge",
2062         .mask           = mask_lapic_irq,
2063         .unmask         = unmask_lapic_irq,
2064         .eoi            = ack_apic,
2065 };
2066
2067 static void setup_nmi (void)
2068 {
2069         /*
2070          * Dirty trick to enable the NMI watchdog ...
2071          * We put the 8259A master into AEOI mode and
2072          * unmask on all local APICs LVT0 as NMI.
2073          *
2074          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2075          * is from Maciej W. Rozycki - so we do not have to EOI from
2076          * the NMI handler or the timer interrupt.
2077          */
2078         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2079
2080         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2081
2082         apic_printk(APIC_VERBOSE, " done.\n");
2083 }
2084
2085 /*
2086  * This looks a bit hackish but it's about the only one way of sending
2087  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2088  * not support the ExtINT mode, unfortunately.  We need to send these
2089  * cycles as some i82489DX-based boards have glue logic that keeps the
2090  * 8259A interrupt line asserted until INTA.  --macro
2091  */
2092 static inline void unlock_ExtINT_logic(void)
2093 {
2094         int apic, pin, i;
2095         struct IO_APIC_route_entry entry0, entry1;
2096         unsigned char save_control, save_freq_select;
2097
2098         pin  = find_isa_irq_pin(8, mp_INT);
2099         apic = find_isa_irq_apic(8, mp_INT);
2100         if (pin == -1)
2101                 return;
2102
2103         entry0 = ioapic_read_entry(apic, pin);
2104         clear_IO_APIC_pin(apic, pin);
2105
2106         memset(&entry1, 0, sizeof(entry1));
2107
2108         entry1.dest_mode = 0;                   /* physical delivery */
2109         entry1.mask = 0;                        /* unmask IRQ now */
2110         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2111         entry1.delivery_mode = dest_ExtINT;
2112         entry1.polarity = entry0.polarity;
2113         entry1.trigger = 0;
2114         entry1.vector = 0;
2115
2116         ioapic_write_entry(apic, pin, entry1);
2117
2118         save_control = CMOS_READ(RTC_CONTROL);
2119         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2120         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2121                    RTC_FREQ_SELECT);
2122         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2123
2124         i = 100;
2125         while (i-- > 0) {
2126                 mdelay(10);
2127                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2128                         i -= 10;
2129         }
2130
2131         CMOS_WRITE(save_control, RTC_CONTROL);
2132         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2133         clear_IO_APIC_pin(apic, pin);
2134
2135         ioapic_write_entry(apic, pin, entry0);
2136 }
2137
2138 int timer_uses_ioapic_pin_0;
2139
2140 /*
2141  * This code may look a bit paranoid, but it's supposed to cooperate with
2142  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2143  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2144  * fanatically on his truly buggy board.
2145  */
2146 static inline void check_timer(void)
2147 {
2148         int apic1, pin1, apic2, pin2;
2149         int vector;
2150
2151         /*
2152          * get/set the timer IRQ vector:
2153          */
2154         disable_8259A_irq(0);
2155         vector = assign_irq_vector(0);
2156         set_intr_gate(vector, interrupt[0]);
2157
2158         /*
2159          * Subtle, code in do_timer_interrupt() expects an AEOI
2160          * mode for the 8259A whenever interrupts are routed
2161          * through I/O APICs.  Also IRQ0 has to be enabled in
2162          * the 8259A which implies the virtual wire has to be
2163          * disabled in the local APIC.
2164          */
2165         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2166         init_8259A(1);
2167         timer_ack = 1;
2168         if (timer_over_8254 > 0)
2169                 enable_8259A_irq(0);
2170
2171         pin1  = find_isa_irq_pin(0, mp_INT);
2172         apic1 = find_isa_irq_apic(0, mp_INT);
2173         pin2  = ioapic_i8259.pin;
2174         apic2 = ioapic_i8259.apic;
2175
2176         if (pin1 == 0)
2177                 timer_uses_ioapic_pin_0 = 1;
2178
2179         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2180                 vector, apic1, pin1, apic2, pin2);
2181
2182         if (pin1 != -1) {
2183                 /*
2184                  * Ok, does IRQ0 through the IOAPIC work?
2185                  */
2186                 unmask_IO_APIC_irq(0);
2187                 if (timer_irq_works()) {
2188                         if (nmi_watchdog == NMI_IO_APIC) {
2189                                 disable_8259A_irq(0);
2190                                 setup_nmi();
2191                                 enable_8259A_irq(0);
2192                         }
2193                         if (disable_timer_pin_1 > 0)
2194                                 clear_IO_APIC_pin(0, pin1);
2195                         return;
2196                 }
2197                 clear_IO_APIC_pin(apic1, pin1);
2198                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2199                                 "IO-APIC\n");
2200         }
2201
2202         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2203         if (pin2 != -1) {
2204                 printk("\n..... (found pin %d) ...", pin2);
2205                 /*
2206                  * legacy devices should be connected to IO APIC #0
2207                  */
2208                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2209                 if (timer_irq_works()) {
2210                         printk("works.\n");
2211                         if (pin1 != -1)
2212                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2213                         else
2214                                 add_pin_to_irq(0, apic2, pin2);
2215                         if (nmi_watchdog == NMI_IO_APIC) {
2216                                 setup_nmi();
2217                         }
2218                         return;
2219                 }
2220                 /*
2221                  * Cleanup, just in case ...
2222                  */
2223                 clear_IO_APIC_pin(apic2, pin2);
2224         }
2225         printk(" failed.\n");
2226
2227         if (nmi_watchdog == NMI_IO_APIC) {
2228                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2229                 nmi_watchdog = 0;
2230         }
2231
2232         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2233
2234         disable_8259A_irq(0);
2235         set_irq_chip_and_handler(0, &lapic_chip, handle_fasteoi_irq);
2236         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2237         enable_8259A_irq(0);
2238
2239         if (timer_irq_works()) {
2240                 printk(" works.\n");
2241                 return;
2242         }
2243         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2244         printk(" failed.\n");
2245
2246         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2247
2248         timer_ack = 0;
2249         init_8259A(0);
2250         make_8259A_irq(0);
2251         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2252
2253         unlock_ExtINT_logic();
2254
2255         if (timer_irq_works()) {
2256                 printk(" works.\n");
2257                 return;
2258         }
2259         printk(" failed :(.\n");
2260         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2261                 "report.  Then try booting with the 'noapic' option");
2262 }
2263
2264 /*
2265  *
2266  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2267  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2268  *   Linux doesn't really care, as it's not actually used
2269  *   for any interrupt handling anyway.
2270  */
2271 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2272
2273 void __init setup_IO_APIC(void)
2274 {
2275         enable_IO_APIC();
2276
2277         if (acpi_ioapic)
2278                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2279         else
2280                 io_apic_irqs = ~PIC_IRQS;
2281
2282         printk("ENABLING IO-APIC IRQs\n");
2283
2284         /*
2285          * Set up IO-APIC IRQ routing.
2286          */
2287         if (!acpi_ioapic)
2288                 setup_ioapic_ids_from_mpc();
2289         sync_Arb_IDs();
2290         setup_IO_APIC_irqs();
2291         init_IO_APIC_traps();
2292         check_timer();
2293         if (!acpi_ioapic)
2294                 print_IO_APIC();
2295 }
2296
2297 static int __init setup_disable_8254_timer(char *s)
2298 {
2299         timer_over_8254 = -1;
2300         return 1;
2301 }
2302 static int __init setup_enable_8254_timer(char *s)
2303 {
2304         timer_over_8254 = 2;
2305         return 1;
2306 }
2307
2308 __setup("disable_8254_timer", setup_disable_8254_timer);
2309 __setup("enable_8254_timer", setup_enable_8254_timer);
2310
2311 /*
2312  *      Called after all the initialization is done. If we didnt find any
2313  *      APIC bugs then we can allow the modify fast path
2314  */
2315
2316 static int __init io_apic_bug_finalize(void)
2317 {
2318         if(sis_apic_bug == -1)
2319                 sis_apic_bug = 0;
2320         return 0;
2321 }
2322
2323 late_initcall(io_apic_bug_finalize);
2324
2325 struct sysfs_ioapic_data {
2326         struct sys_device dev;
2327         struct IO_APIC_route_entry entry[0];
2328 };
2329 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2330
2331 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2332 {
2333         struct IO_APIC_route_entry *entry;
2334         struct sysfs_ioapic_data *data;
2335         int i;
2336
2337         data = container_of(dev, struct sysfs_ioapic_data, dev);
2338         entry = data->entry;
2339         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2340                 entry[i] = ioapic_read_entry(dev->id, i);
2341
2342         return 0;
2343 }
2344
2345 static int ioapic_resume(struct sys_device *dev)
2346 {
2347         struct IO_APIC_route_entry *entry;
2348         struct sysfs_ioapic_data *data;
2349         unsigned long flags;
2350         union IO_APIC_reg_00 reg_00;
2351         int i;
2352
2353         data = container_of(dev, struct sysfs_ioapic_data, dev);
2354         entry = data->entry;
2355
2356         spin_lock_irqsave(&ioapic_lock, flags);
2357         reg_00.raw = io_apic_read(dev->id, 0);
2358         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2359                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2360                 io_apic_write(dev->id, 0, reg_00.raw);
2361         }
2362         spin_unlock_irqrestore(&ioapic_lock, flags);
2363         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2364                 ioapic_write_entry(dev->id, i, entry[i]);
2365
2366         return 0;
2367 }
2368
2369 static struct sysdev_class ioapic_sysdev_class = {
2370         set_kset_name("ioapic"),
2371         .suspend = ioapic_suspend,
2372         .resume = ioapic_resume,
2373 };
2374
2375 static int __init ioapic_init_sysfs(void)
2376 {
2377         struct sys_device * dev;
2378         int i, size, error = 0;
2379
2380         error = sysdev_class_register(&ioapic_sysdev_class);
2381         if (error)
2382                 return error;
2383
2384         for (i = 0; i < nr_ioapics; i++ ) {
2385                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2386                         * sizeof(struct IO_APIC_route_entry);
2387                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2388                 if (!mp_ioapic_data[i]) {
2389                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2390                         continue;
2391                 }
2392                 memset(mp_ioapic_data[i], 0, size);
2393                 dev = &mp_ioapic_data[i]->dev;
2394                 dev->id = i;
2395                 dev->cls = &ioapic_sysdev_class;
2396                 error = sysdev_register(dev);
2397                 if (error) {
2398                         kfree(mp_ioapic_data[i]);
2399                         mp_ioapic_data[i] = NULL;
2400                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2401                         continue;
2402                 }
2403         }
2404
2405         return 0;
2406 }
2407
2408 device_initcall(ioapic_init_sysfs);
2409
2410 #ifdef CONFIG_PCI_MSI
2411 /*
2412  * Dynamic irq allocate and deallocation for MSI
2413  */
2414 int create_irq(void)
2415 {
2416         /* Allocate an unused irq */
2417         int irq, new, vector;
2418         unsigned long flags;
2419
2420         irq = -ENOSPC;
2421         spin_lock_irqsave(&vector_lock, flags);
2422         for (new = (NR_IRQS - 1); new >= 0; new--) {
2423                 if (platform_legacy_irq(new))
2424                         continue;
2425                 if (irq_vector[new] != 0)
2426                         continue;
2427                 vector = __assign_irq_vector(new);
2428                 if (likely(vector > 0))
2429                         irq = new;
2430                 break;
2431         }
2432         spin_unlock_irqrestore(&vector_lock, flags);
2433
2434         if (irq >= 0) {
2435                 set_intr_gate(vector, interrupt[irq]);
2436                 dynamic_irq_init(irq);
2437         }
2438         return irq;
2439 }
2440
2441 void destroy_irq(unsigned int irq)
2442 {
2443         unsigned long flags;
2444
2445         dynamic_irq_cleanup(irq);
2446
2447         spin_lock_irqsave(&vector_lock, flags);
2448         irq_vector[irq] = 0;
2449         spin_unlock_irqrestore(&vector_lock, flags);
2450 }
2451 #endif /* CONFIG_PCI_MSI */
2452
2453 /*
2454  * MSI mesage composition
2455  */
2456 #ifdef CONFIG_PCI_MSI
2457 static int msi_msg_setup(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2458 {
2459         /* For now always this code always uses physical delivery
2460          * mode.
2461          */
2462         int vector;
2463         unsigned dest;
2464
2465         vector = assign_irq_vector(irq);
2466         if (vector >= 0) {
2467                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2468
2469                 msg->address_hi = MSI_ADDR_BASE_HI;
2470                 msg->address_lo =
2471                         MSI_ADDR_BASE_LO |
2472                         ((INT_DEST_MODE == 0) ?
2473                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2474                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2475                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2476                                 MSI_ADDR_REDIRECTION_CPU:
2477                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2478                         MSI_ADDR_DEST_ID(dest);
2479
2480                 msg->data =
2481                         MSI_DATA_TRIGGER_EDGE |
2482                         MSI_DATA_LEVEL_ASSERT |
2483                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2484                                 MSI_DATA_DELIVERY_FIXED:
2485                                 MSI_DATA_DELIVERY_LOWPRI) |
2486                         MSI_DATA_VECTOR(vector);
2487         }
2488         return vector;
2489 }
2490
2491 static void msi_msg_teardown(unsigned int irq)
2492 {
2493         return;
2494 }
2495
2496 static void msi_msg_set_affinity(unsigned int irq, cpumask_t mask, struct msi_msg *msg)
2497 {
2498         int vector;
2499         unsigned dest;
2500
2501         vector = assign_irq_vector(irq);
2502         if (vector > 0) {
2503                 dest = cpu_mask_to_apicid(mask);
2504
2505                 msg->data &= ~MSI_DATA_VECTOR_MASK;
2506                 msg->data |= MSI_DATA_VECTOR(vector);
2507                 msg->address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2508                 msg->address_lo |= MSI_ADDR_DEST_ID(dest);
2509         }
2510 }
2511
2512 struct msi_ops arch_msi_ops = {
2513         .needs_64bit_address = 0,
2514         .setup = msi_msg_setup,
2515         .teardown = msi_msg_teardown,
2516         .target = msi_msg_set_affinity,
2517 };
2518
2519 #endif /* CONFIG_PCI_MSI */
2520
2521 /* --------------------------------------------------------------------------
2522                           ACPI-based IOAPIC Configuration
2523    -------------------------------------------------------------------------- */
2524
2525 #ifdef CONFIG_ACPI
2526
2527 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2528 {
2529         union IO_APIC_reg_00 reg_00;
2530         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2531         physid_mask_t tmp;
2532         unsigned long flags;
2533         int i = 0;
2534
2535         /*
2536          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2537          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2538          * supports up to 16 on one shared APIC bus.
2539          *
2540          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2541          *      advantage of new APIC bus architecture.
2542          */
2543
2544         if (physids_empty(apic_id_map))
2545                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2546
2547         spin_lock_irqsave(&ioapic_lock, flags);
2548         reg_00.raw = io_apic_read(ioapic, 0);
2549         spin_unlock_irqrestore(&ioapic_lock, flags);
2550
2551         if (apic_id >= get_physical_broadcast()) {
2552                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2553                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2554                 apic_id = reg_00.bits.ID;
2555         }
2556
2557         /*
2558          * Every APIC in a system must have a unique ID or we get lots of nice
2559          * 'stuck on smp_invalidate_needed IPI wait' messages.
2560          */
2561         if (check_apicid_used(apic_id_map, apic_id)) {
2562
2563                 for (i = 0; i < get_physical_broadcast(); i++) {
2564                         if (!check_apicid_used(apic_id_map, i))
2565                                 break;
2566                 }
2567
2568                 if (i == get_physical_broadcast())
2569                         panic("Max apic_id exceeded!\n");
2570
2571                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2572                         "trying %d\n", ioapic, apic_id, i);
2573
2574                 apic_id = i;
2575         }
2576
2577         tmp = apicid_to_cpu_present(apic_id);
2578         physids_or(apic_id_map, apic_id_map, tmp);
2579
2580         if (reg_00.bits.ID != apic_id) {
2581                 reg_00.bits.ID = apic_id;
2582
2583                 spin_lock_irqsave(&ioapic_lock, flags);
2584                 io_apic_write(ioapic, 0, reg_00.raw);
2585                 reg_00.raw = io_apic_read(ioapic, 0);
2586                 spin_unlock_irqrestore(&ioapic_lock, flags);
2587
2588                 /* Sanity check */
2589                 if (reg_00.bits.ID != apic_id) {
2590                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2591                         return -1;
2592                 }
2593         }
2594
2595         apic_printk(APIC_VERBOSE, KERN_INFO
2596                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2597
2598         return apic_id;
2599 }
2600
2601
2602 int __init io_apic_get_version (int ioapic)
2603 {
2604         union IO_APIC_reg_01    reg_01;
2605         unsigned long flags;
2606
2607         spin_lock_irqsave(&ioapic_lock, flags);
2608         reg_01.raw = io_apic_read(ioapic, 1);
2609         spin_unlock_irqrestore(&ioapic_lock, flags);
2610
2611         return reg_01.bits.version;
2612 }
2613
2614
2615 int __init io_apic_get_redir_entries (int ioapic)
2616 {
2617         union IO_APIC_reg_01    reg_01;
2618         unsigned long flags;
2619
2620         spin_lock_irqsave(&ioapic_lock, flags);
2621         reg_01.raw = io_apic_read(ioapic, 1);
2622         spin_unlock_irqrestore(&ioapic_lock, flags);
2623
2624         return reg_01.bits.entries;
2625 }
2626
2627
2628 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2629 {
2630         struct IO_APIC_route_entry entry;
2631         unsigned long flags;
2632
2633         if (!IO_APIC_IRQ(irq)) {
2634                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2635                         ioapic);
2636                 return -EINVAL;
2637         }
2638
2639         /*
2640          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2641          * Note that we mask (disable) IRQs now -- these get enabled when the
2642          * corresponding device driver registers for this IRQ.
2643          */
2644
2645         memset(&entry,0,sizeof(entry));
2646
2647         entry.delivery_mode = INT_DELIVERY_MODE;
2648         entry.dest_mode = INT_DEST_MODE;
2649         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2650         entry.trigger = edge_level;
2651         entry.polarity = active_high_low;
2652         entry.mask  = 1;
2653
2654         /*
2655          * IRQs < 16 are already in the irq_2_pin[] map
2656          */
2657         if (irq >= 16)
2658                 add_pin_to_irq(irq, ioapic, pin);
2659
2660         entry.vector = assign_irq_vector(irq);
2661
2662         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2663                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2664                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2665                 edge_level, active_high_low);
2666
2667         ioapic_register_intr(irq, entry.vector, edge_level);
2668
2669         if (!ioapic && (irq < 16))
2670                 disable_8259A_irq(irq);
2671
2672         ioapic_write_entry(ioapic, pin, entry);
2673         spin_lock_irqsave(&ioapic_lock, flags);
2674         set_native_irq_info(irq, TARGET_CPUS);
2675         spin_unlock_irqrestore(&ioapic_lock, flags);
2676
2677         return 0;
2678 }
2679
2680 #endif /* CONFIG_ACPI */
2681
2682 static int __init parse_disable_timer_pin_1(char *arg)
2683 {
2684         disable_timer_pin_1 = 1;
2685         return 0;
2686 }
2687 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2688
2689 static int __init parse_enable_timer_pin_1(char *arg)
2690 {
2691         disable_timer_pin_1 = -1;
2692         return 0;
2693 }
2694 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2695
2696 static int __init parse_noapic(char *arg)
2697 {
2698         /* disable IO-APIC */
2699         disable_ioapic_setup();
2700         return 0;
2701 }
2702 early_param("noapic", parse_noapic);