2 * linux/arch/i386/mach_visws/visws_apic.c
4 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
6 * SGI Visual Workstation interrupt controller
8 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
9 * which serves as the main interrupt controller in the system. Non-legacy
10 * hardware in the system uses this controller directly. Legacy devices
11 * are connected to the PIIX4 which in turn has its 8259(s) connected to
12 * a of the Cobalt APIC entry.
14 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
16 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
19 #include <linux/kernel_stat.h>
20 #include <linux/interrupt.h>
21 #include <linux/smp_lock.h>
22 #include <linux/init.h>
26 #include <asm/i8259.h>
29 #include "irq_vectors.h"
32 static DEFINE_SPINLOCK(cobalt_lock);
35 * Set the given Cobalt APIC Redirection Table entry to point
36 * to the given IDT vector/index.
38 static inline void co_apic_set(int entry, int irq)
40 co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
41 co_apic_write(CO_APIC_HI(entry), 0);
45 * Cobalt (IO)-APIC functions to handle PCI devices.
47 static inline int co_apic_ide0_hack(void)
49 extern char visws_board_type;
50 extern char visws_board_rev;
52 if (visws_board_type == VISWS_320 && visws_board_rev == 5)
57 static int is_co_apic(unsigned int irq)
63 case 0: return CO_APIC_CPU;
64 case CO_IRQ_IDE0: return co_apic_ide0_hack();
65 case CO_IRQ_IDE1: return CO_APIC_IDE1;
72 * This is the SGI Cobalt (IO-)APIC:
75 static void enable_cobalt_irq(unsigned int irq)
77 co_apic_set(is_co_apic(irq), irq);
80 static void disable_cobalt_irq(unsigned int irq)
82 int entry = is_co_apic(irq);
84 co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
85 co_apic_read(CO_APIC_LO(entry));
89 * "irq" really just serves to identify the device. Here is where we
90 * map this to the Cobalt APIC entry where it's physically wired.
91 * This is called via request_irq -> setup_irq -> irq_desc->startup()
93 static unsigned int startup_cobalt_irq(unsigned int irq)
97 spin_lock_irqsave(&cobalt_lock, flags);
98 if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
99 irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
100 enable_cobalt_irq(irq);
101 spin_unlock_irqrestore(&cobalt_lock, flags);
105 static void ack_cobalt_irq(unsigned int irq)
109 spin_lock_irqsave(&cobalt_lock, flags);
110 disable_cobalt_irq(irq);
111 apic_write(APIC_EOI, APIC_EIO_ACK);
112 spin_unlock_irqrestore(&cobalt_lock, flags);
115 static void end_cobalt_irq(unsigned int irq)
119 spin_lock_irqsave(&cobalt_lock, flags);
120 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
121 enable_cobalt_irq(irq);
122 spin_unlock_irqrestore(&cobalt_lock, flags);
125 static struct hw_interrupt_type cobalt_irq_type = {
126 .typename = "Cobalt-APIC",
127 .startup = startup_cobalt_irq,
128 .shutdown = disable_cobalt_irq,
129 .enable = enable_cobalt_irq,
130 .disable = disable_cobalt_irq,
131 .ack = ack_cobalt_irq,
132 .end = end_cobalt_irq,
137 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
138 * -- not the manner expected by the code in i8259.c.
140 * there is a 'master' physical interrupt source that gets sent to
141 * the CPU. But in the chipset there are various 'virtual' interrupts
142 * waiting to be handled. We represent this to Linux through a 'master'
143 * interrupt controller type, and through a special virtual interrupt-
144 * controller. Device drivers only see the virtual interrupt sources.
146 static unsigned int startup_piix4_master_irq(unsigned int irq)
150 return startup_cobalt_irq(irq);
153 static void end_piix4_master_irq(unsigned int irq)
157 spin_lock_irqsave(&cobalt_lock, flags);
158 enable_cobalt_irq(irq);
159 spin_unlock_irqrestore(&cobalt_lock, flags);
162 static struct hw_interrupt_type piix4_master_irq_type = {
163 .typename = "PIIX4-master",
164 .startup = startup_piix4_master_irq,
165 .ack = ack_cobalt_irq,
166 .end = end_piix4_master_irq,
170 static struct hw_interrupt_type piix4_virtual_irq_type = {
171 .typename = "PIIX4-virtual",
172 .startup = startup_8259A_irq,
173 .shutdown = disable_8259A_irq,
174 .enable = enable_8259A_irq,
175 .disable = disable_8259A_irq,
180 * PIIX4-8259 master/virtual functions to handle interrupt requests
181 * from legacy devices: floppy, parallel, serial, rtc.
183 * None of these get Cobalt APIC entries, neither do they have IDT
184 * entries. These interrupts are purely virtual and distributed from
185 * the 'master' interrupt source: CO_IRQ_8259.
187 * When the 8259 interrupts its handler figures out which of these
188 * devices is interrupting and dispatches to its handler.
190 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
191 * enable_irq gets the right irq. This 'master' irq is never directly
192 * manipulated by any driver.
194 static irqreturn_t piix4_master_intr(int irq, void *dev_id, struct pt_regs * regs)
200 spin_lock_irqsave(&i8259A_lock, flags);
202 /* Find out what's interrupting in the PIIX4 master 8259 */
203 outb(0x0c, 0x20); /* OCW3 Poll command */
207 * Bit 7 == 0 means invalid/spurious
209 if (unlikely(!(realirq & 0x80)))
214 if (unlikely(realirq == 2)) {
218 if (unlikely(!(realirq & 0x80)))
221 realirq = (realirq & 7) + 8;
224 /* mask and ack interrupt */
225 cached_irq_mask |= 1 << realirq;
226 if (unlikely(realirq > 7)) {
228 outb(cached_slave_mask, 0xa1);
229 outb(0x60 + (realirq & 7), 0xa0);
230 outb(0x60 + 2, 0x20);
233 outb(cached_master_mask, 0x21);
234 outb(0x60 + realirq, 0x20);
237 spin_unlock_irqrestore(&i8259A_lock, flags);
239 desc = irq_desc + realirq;
242 * handle this 'virtual interrupt' as a Cobalt one now.
244 kstat_cpu(smp_processor_id()).irqs[realirq]++;
246 if (likely(desc->action != NULL))
247 handle_IRQ_event(realirq, regs, desc->action);
249 if (!(desc->status & IRQ_DISABLED))
250 enable_8259A_irq(realirq);
255 spin_unlock_irqrestore(&i8259A_lock, flags);
259 static struct irqaction master_action = {
260 .handler = piix4_master_intr,
261 .name = "PIIX4-8259",
264 static struct irqaction cascade_action = {
265 .handler = no_action,
270 void init_VISWS_APIC_irqs(void)
274 for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
275 irq_desc[i].status = IRQ_DISABLED;
276 irq_desc[i].action = 0;
277 irq_desc[i].depth = 1;
280 irq_desc[i].chip = &cobalt_irq_type;
282 else if (i == CO_IRQ_IDE0) {
283 irq_desc[i].chip = &cobalt_irq_type;
285 else if (i == CO_IRQ_IDE1) {
286 irq_desc[i].chip = &cobalt_irq_type;
288 else if (i == CO_IRQ_8259) {
289 irq_desc[i].chip = &piix4_master_irq_type;
291 else if (i < CO_IRQ_APIC0) {
292 irq_desc[i].chip = &piix4_virtual_irq_type;
294 else if (IS_CO_APIC(i)) {
295 irq_desc[i].chip = &cobalt_irq_type;
299 setup_irq(CO_IRQ_8259, &master_action);
300 setup_irq(2, &cascade_action);