arch/ia64/kernel/iosapic.c

   1 /*
   2  * I/O SAPIC support.
   3  *
   4  * Copyright (C) 1999 Intel Corp.
   5  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   6  * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
   7  * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
   8  *      David Mosberger-Tang <davidm@hpl.hp.com>
   9  * Copyright (C) 1999 VA Linux Systems
  10  * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
  11  *
  12  * 00/04/19     D. Mosberger    Rewritten to mirror more closely the x86 I/O
  13  *                              APIC code.  In particular, we now have separate
  14  *                              handlers for edge and level triggered
  15  *                              interrupts.
  16  * 00/10/27     Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
  17  *                              allocation PCI to vector mapping, shared PCI
  18  *                              interrupts.
  19  * 00/10/27     D. Mosberger    Document things a bit more to make them more
  20  *                              understandable.  Clean up much of the old
  21  *                              IOSAPIC cruft.
  22  * 01/07/27     J.I. Lee        PCI irq routing, Platform/Legacy interrupts
  23  *                              and fixes for ACPI S5(SoftOff) support.
  24  * 02/01/23     J.I. Lee        iosapic pgm fixes for PCI irq routing from _PRT
  25  * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt
  26  *                              vectors in iosapic_set_affinity(),
  27  *                              initializations for /proc/irq/#/smp_affinity
  28  * 02/04/02     P. Diefenbaugh  Cleaned up ACPI PCI IRQ routing.
  29  * 02/04/18     J.I. Lee        bug fix in iosapic_init_pci_irq
  30  * 02/04/30     J.I. Lee        bug fix in find_iosapic to fix ACPI PCI IRQ to
  31  *                              IOSAPIC mapping error
  32  * 02/07/29     T. Kochi        Allocate interrupt vectors dynamically
  33  * 02/08/04     T. Kochi        Cleaned up terminology (irq, global system
  34  *                              interrupt, vector, etc.)
  35  * 02/09/20     D. Mosberger    Simplified by taking advantage of ACPI's
  36  *                              pci_irq code.
  37  * 03/02/19     B. Helgaas      Make pcat_compat system-wide, not per-IOSAPIC.
  38  *                              Remove iosapic_address & gsi_base from
  39  *                              external interfaces.  Rationalize
  40  *                              __init/__devinit attributes.
  41  * 04/12/04 Ashok Raj   <ashok.raj@intel.com> Intel Corporation 2004
  42  *                              Updated to work with irq migration necessary
  43  *                              for CPU Hotplug
  44  */
  45 /*
  46  * Here is what the interrupt logic between a PCI device and the kernel looks
  47  * like:
  48  *
  49  * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
  50  *     INTD).  The device is uniquely identified by its bus-, and slot-number
  51  *     (the function number does not matter here because all functions share
  52  *     the same interrupt lines).
  53  *
  54  * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
  55  *     controller.  Multiple interrupt lines may have to share the same
  56  *     IOSAPIC pin (if they're level triggered and use the same polarity).
  57  *     Each interrupt line has a unique Global System Interrupt (GSI) number
  58  *     which can be calculated as the sum of the controller's base GSI number
  59  *     and the IOSAPIC pin number to which the line connects.
  60  *
  61  * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
  62  * IOSAPIC pin into the IA-64 interrupt vector.  This interrupt vector is then
  63  * sent to the CPU.
  64  *
  65  * (4) The kernel recognizes an interrupt as an IRQ.  The IRQ interface is
  66  *     used as architecture-independent interrupt handling mechanism in Linux.
  67  *     As an IRQ is a number, we have to have
  68  *     IA-64 interrupt vector number <-> IRQ number mapping.  On smaller
  69  *     systems, we use one-to-one mapping between IA-64 vector and IRQ.  A
  70  *     platform can implement platform_irq_to_vector(irq) and
  71  *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
  72  *     Please see also arch/ia64/include/asm/hw_irq.h for those APIs.
  73  *
  74  * To sum up, there are three levels of mappings involved:
  75  *
  76  *      PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
  77  *
  78  * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
  79  * describeinterrupts.  Now we use "IRQ" only for Linux IRQ's.  ISA IRQ
  80  * (isa_irq) is the only exception in this source code.
  81  */
  82
  83 #include <linux/acpi.h>
  84 #include <linux/init.h>
  85 #include <linux/irq.h>
  86 #include <linux/kernel.h>
  87 #include <linux/list.h>
  88 #include <linux/pci.h>
  89 #include <linux/slab.h>
  90 #include <linux/smp.h>
  91 #include <linux/string.h>
  92 #include <linux/bootmem.h>
  93
  94 #include <asm/delay.h>
  95 #include <asm/hw_irq.h>
  96 #include <asm/io.h>
  97 #include <asm/iosapic.h>
  98 #include <asm/machvec.h>
  99 #include <asm/processor.h>
 100 #include <asm/ptrace.h>
 101 #include <asm/system.h>
 102
 103 #undef DEBUG_INTERRUPT_ROUTING
 104
 105 #ifdef DEBUG_INTERRUPT_ROUTING
 106 #define DBG(fmt...)     printk(fmt)
 107 #else
 108 #define DBG(fmt...)
 109 #endif
 110
 111 static DEFINE_SPINLOCK(iosapic_lock);
 112
 113 /*
 114  * These tables map IA-64 vectors to the IOSAPIC pin that generates this
 115  * vector.
 116  */
 117
 118 #define NO_REF_RTE      0
 119
 120 static struct iosapic {
 121         char __iomem    *addr;          /* base address of IOSAPIC */
 122         unsigned int    gsi_base;       /* GSI base */
 123         unsigned short  num_rte;        /* # of RTEs on this IOSAPIC */
 124         int             rtes_inuse;     /* # of RTEs in use on this IOSAPIC */
 125 #ifdef CONFIG_NUMA
 126         unsigned short  node;           /* numa node association via pxm */
 127 #endif
 128         spinlock_t      lock;           /* lock for indirect reg access */
 129 } iosapic_lists[NR_IOSAPICS];
 130
 131 struct iosapic_rte_info {
 132         struct list_head rte_list;      /* RTEs sharing the same vector */
 133         char            rte_index;      /* IOSAPIC RTE index */
 134         int             refcnt;         /* reference counter */
 135         struct iosapic  *iosapic;
 136 } ____cacheline_aligned;
 137
 138 static struct iosapic_intr_info {
 139         struct list_head rtes;          /* RTEs using this vector (empty =>
 140                                          * not an IOSAPIC interrupt) */
 141         int             count;          /* # of registered RTEs */
 142         u32             low32;          /* current value of low word of
 143                                          * Redirection table entry */
 144         unsigned int    dest;           /* destination CPU physical ID */
 145         unsigned char   dmode   : 3;    /* delivery mode (see iosapic.h) */
 146         unsigned char   polarity: 1;    /* interrupt polarity
 147                                          * (see iosapic.h) */
 148         unsigned char   trigger : 1;    /* trigger mode (see iosapic.h) */
 149 } iosapic_intr_info[NR_IRQS];
 150
 151 static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
 152
 153 static inline void
 154 iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val)
 155 {
 156         unsigned long flags;
 157
 158         spin_lock_irqsave(&iosapic->lock, flags);
 159         __iosapic_write(iosapic->addr, reg, val);
 160         spin_unlock_irqrestore(&iosapic->lock, flags);
 161 }
 162
 163 /*
 164  * Find an IOSAPIC associated with a GSI
 165  */
 166 static inline int
 167 find_iosapic (unsigned int gsi)
 168 {
 169         int i;
 170
 171         for (i = 0; i < NR_IOSAPICS; i++) {
 172                 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) <
 173                     iosapic_lists[i].num_rte)
 174                         return i;
 175         }
 176
 177         return -1;
 178 }
 179
 180 static inline int __gsi_to_irq(unsigned int gsi)
 181 {
 182         int irq;
 183         struct iosapic_intr_info *info;
 184         struct iosapic_rte_info *rte;
 185
 186         for (irq = 0; irq < NR_IRQS; irq++) {
 187                 info = &iosapic_intr_info[irq];
 188                 list_for_each_entry(rte, &info->rtes, rte_list)
 189                         if (rte->iosapic->gsi_base + rte->rte_index == gsi)
 190                                 return irq;
 191         }
 192         return -1;
 193 }
 194
 195 int
 196 gsi_to_irq (unsigned int gsi)
 197 {
 198         unsigned long flags;
 199         int irq;
 200
 201         spin_lock_irqsave(&iosapic_lock, flags);
 202         irq = __gsi_to_irq(gsi);
 203         spin_unlock_irqrestore(&iosapic_lock, flags);
 204         return irq;
 205 }
 206
 207 static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi)
 208 {
 209         struct iosapic_rte_info *rte;
 210
 211         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
 212                 if (rte->iosapic->gsi_base + rte->rte_index == gsi)
 213                         return rte;
 214         return NULL;
 215 }
 216
 217 static void
 218 set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask)
 219 {
 220         unsigned long pol, trigger, dmode;
 221         u32 low32, high32;
 222         int rte_index;
 223         char redir;
 224         struct iosapic_rte_info *rte;
 225         ia64_vector vector = irq_to_vector(irq);
 226
 227         DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
 228
 229         rte = find_rte(irq, gsi);
 230         if (!rte)
 231                 return;         /* not an IOSAPIC interrupt */
 232
 233         rte_index = rte->rte_index;
 234         pol     = iosapic_intr_info[irq].polarity;
 235         trigger = iosapic_intr_info[irq].trigger;
 236         dmode   = iosapic_intr_info[irq].dmode;
 237
 238         redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
 239
 240 #ifdef CONFIG_SMP
 241         set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
 242 #endif
 243
 244         low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
 245                  (trigger << IOSAPIC_TRIGGER_SHIFT) |
 246                  (dmode << IOSAPIC_DELIVERY_SHIFT) |
 247                  ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
 248                  vector);
 249
 250         /* dest contains both id and eid */
 251         high32 = (dest << IOSAPIC_DEST_SHIFT);
 252
 253         iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
 254         iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 255         iosapic_intr_info[irq].low32 = low32;
 256         iosapic_intr_info[irq].dest = dest;
 257 }
 258
 259 static void
 260 nop (unsigned int irq)
 261 {
 262         /* do nothing... */
 263 }
 264
 265
 266 #ifdef CONFIG_KEXEC
 267 void
 268 kexec_disable_iosapic(void)
 269 {
 270         struct iosapic_intr_info *info;
 271         struct iosapic_rte_info *rte;
 272         ia64_vector vec;
 273         int irq;
 274
 275         for (irq = 0; irq < NR_IRQS; irq++) {
 276                 info = &iosapic_intr_info[irq];
 277                 vec = irq_to_vector(irq);
 278                 list_for_each_entry(rte, &info->rtes,
 279                                 rte_list) {
 280                         iosapic_write(rte->iosapic,
 281                                         IOSAPIC_RTE_LOW(rte->rte_index),
 282                                         IOSAPIC_MASK|vec);
 283                         iosapic_eoi(rte->iosapic->addr, vec);
 284                 }
 285         }
 286 }
 287 #endif
 288
 289 static void
 290 mask_irq (unsigned int irq)
 291 {
 292         u32 low32;
 293         int rte_index;
 294         struct iosapic_rte_info *rte;
 295
 296         if (!iosapic_intr_info[irq].count)
 297                 return;                 /* not an IOSAPIC interrupt! */
 298
 299         /* set only the mask bit */
 300         low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
 301         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
 302                 rte_index = rte->rte_index;
 303                 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 304         }
 305 }
 306
 307 static void
 308 unmask_irq (unsigned int irq)
 309 {
 310         u32 low32;
 311         int rte_index;
 312         struct iosapic_rte_info *rte;
 313
 314         if (!iosapic_intr_info[irq].count)
 315                 return;                 /* not an IOSAPIC interrupt! */
 316
 317         low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK;
 318         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
 319                 rte_index = rte->rte_index;
 320                 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 321         }
 322 }
 323
 324
 325 static int
 326 iosapic_set_affinity(unsigned int irq, const struct cpumask *mask)
 327 {
 328 #ifdef CONFIG_SMP
 329         u32 high32, low32;
 330         int cpu, dest, rte_index;
 331         int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
 332         struct iosapic_rte_info *rte;
 333         struct iosapic *iosapic;
 334
 335         irq &= (~IA64_IRQ_REDIRECTED);
 336
 337         cpu = cpumask_first_and(cpu_online_mask, mask);
 338         if (cpu >= nr_cpu_ids)
 339                 return -1;
 340
 341         if (irq_prepare_move(irq, cpu))
 342                 return -1;
 343
 344         dest = cpu_physical_id(cpu);
 345
 346         if (!iosapic_intr_info[irq].count)
 347                 return -1;                      /* not an IOSAPIC interrupt */
 348
 349         set_irq_affinity_info(irq, dest, redir);
 350
 351         /* dest contains both id and eid */
 352         high32 = dest << IOSAPIC_DEST_SHIFT;
 353
 354         low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
 355         if (redir)
 356                 /* change delivery mode to lowest priority */
 357                 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
 358         else
 359                 /* change delivery mode to fixed */
 360                 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
 361         low32 &= IOSAPIC_VECTOR_MASK;
 362         low32 |= irq_to_vector(irq);
 363
 364         iosapic_intr_info[irq].low32 = low32;
 365         iosapic_intr_info[irq].dest = dest;
 366         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
 367                 iosapic = rte->iosapic;
 368                 rte_index = rte->rte_index;
 369                 iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
 370                 iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 371         }
 372
 373 #endif
 374         return 0;
 375 }
 376
 377 /*
 378  * Handlers for level-triggered interrupts.
 379  */
 380
 381 static unsigned int
 382 iosapic_startup_level_irq (unsigned int irq)
 383 {
 384         unmask_irq(irq);
 385         return 0;
 386 }
 387
 388 static void
 389 iosapic_unmask_level_irq (unsigned int irq)
 390 {
 391         ia64_vector vec = irq_to_vector(irq);
 392         struct iosapic_rte_info *rte;
 393         int do_unmask_irq = 0;
 394
 395         irq_complete_move(irq);
 396         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
 397                 do_unmask_irq = 1;
 398                 mask_irq(irq);
 399         } else
 400                 unmask_irq(irq);
 401
 402         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
 403                 iosapic_eoi(rte->iosapic->addr, vec);
 404
 405         if (unlikely(do_unmask_irq)) {
 406                 move_masked_irq(irq);
 407                 unmask_irq(irq);
 408         }
 409 }
 410
 411 #define iosapic_shutdown_level_irq      mask_irq
 412 #define iosapic_enable_level_irq        unmask_irq
 413 #define iosapic_disable_level_irq       mask_irq
 414 #define iosapic_ack_level_irq           nop
 415
 416 static struct irq_chip irq_type_iosapic_level = {
 417         .name =         "IO-SAPIC-level",
 418         .startup =      iosapic_startup_level_irq,
 419         .shutdown =     iosapic_shutdown_level_irq,
 420         .enable =       iosapic_enable_level_irq,
 421         .disable =      iosapic_disable_level_irq,
 422         .ack =          iosapic_ack_level_irq,
 423         .mask =         mask_irq,
 424         .unmask =       iosapic_unmask_level_irq,
 425         .set_affinity = iosapic_set_affinity
 426 };
 427
 428 /*
 429  * Handlers for edge-triggered interrupts.
 430  */
 431
 432 static unsigned int
 433 iosapic_startup_edge_irq (unsigned int irq)
 434 {
 435         unmask_irq(irq);
 436         /*
 437          * IOSAPIC simply drops interrupts pended while the
 438          * corresponding pin was masked, so we can't know if an
 439          * interrupt is pending already.  Let's hope not...
 440          */
 441         return 0;
 442 }
 443
 444 static void
 445 iosapic_ack_edge_irq (unsigned int irq)
 446 {
 447         struct irq_desc *idesc = irq_desc + irq;
 448
 449         irq_complete_move(irq);
 450         move_native_irq(irq);
 451         /*
 452          * Once we have recorded IRQ_PENDING already, we can mask the
 453          * interrupt for real. This prevents IRQ storms from unhandled
 454          * devices.
 455          */
 456         if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
 457             (IRQ_PENDING|IRQ_DISABLED))
 458                 mask_irq(irq);
 459 }
 460
 461 #define iosapic_enable_edge_irq         unmask_irq
 462 #define iosapic_disable_edge_irq        nop
 463
 464 static struct irq_chip irq_type_iosapic_edge = {
 465         .name =         "IO-SAPIC-edge",
 466         .startup =      iosapic_startup_edge_irq,
 467         .shutdown =     iosapic_disable_edge_irq,
 468         .enable =       iosapic_enable_edge_irq,
 469         .disable =      iosapic_disable_edge_irq,
 470         .ack =          iosapic_ack_edge_irq,
 471         .mask =         mask_irq,
 472         .unmask =       unmask_irq,
 473         .set_affinity = iosapic_set_affinity
 474 };
 475
 476 static unsigned int
 477 iosapic_version (char __iomem *addr)
 478 {
 479         /*
 480          * IOSAPIC Version Register return 32 bit structure like:
 481          * {
 482          *      unsigned int version   : 8;
 483          *      unsigned int reserved1 : 8;
 484          *      unsigned int max_redir : 8;
 485          *      unsigned int reserved2 : 8;
 486          * }
 487          */
 488         return __iosapic_read(addr, IOSAPIC_VERSION);
 489 }
 490
 491 static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol)
 492 {
 493         int i, irq = -ENOSPC, min_count = -1;
 494         struct iosapic_intr_info *info;
 495
 496         /*
 497          * shared vectors for edge-triggered interrupts are not
 498          * supported yet
 499          */
 500         if (trigger == IOSAPIC_EDGE)
 501                 return -EINVAL;
 502
 503         for (i = 0; i < NR_IRQS; i++) {
 504                 info = &iosapic_intr_info[i];
 505                 if (info->trigger == trigger && info->polarity == pol &&
 506                     (info->dmode == IOSAPIC_FIXED ||
 507                      info->dmode == IOSAPIC_LOWEST_PRIORITY) &&
 508                     can_request_irq(i, IRQF_SHARED)) {
 509                         if (min_count == -1 || info->count < min_count) {
 510                                 irq = i;
 511                                 min_count = info->count;
 512                         }
 513                 }
 514         }
 515         return irq;
 516 }
 517
 518 /*
 519  * if the given vector is already owned by other,
 520  *  assign a new vector for the other and make the vector available
 521  */
 522 static void __init
 523 iosapic_reassign_vector (int irq)
 524 {
 525         int new_irq;
 526
 527         if (iosapic_intr_info[irq].count) {
 528                 new_irq = create_irq();
 529                 if (new_irq < 0)
 530                         panic("%s: out of interrupt vectors!\n", __func__);
 531                 printk(KERN_INFO "Reassigning vector %d to %d\n",
 532                        irq_to_vector(irq), irq_to_vector(new_irq));
 533                 memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq],
 534                        sizeof(struct iosapic_intr_info));
 535                 INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes);
 536                 list_move(iosapic_intr_info[irq].rtes.next,
 537                           &iosapic_intr_info[new_irq].rtes);
 538                 memset(&iosapic_intr_info[irq], 0,
 539                        sizeof(struct iosapic_intr_info));
 540                 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
 541                 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
 542         }
 543 }
 544
 545 static inline int irq_is_shared (int irq)
 546 {
 547         return (iosapic_intr_info[irq].count > 1);
 548 }
 549
 550 struct irq_chip*
 551 ia64_native_iosapic_get_irq_chip(unsigned long trigger)
 552 {
 553         if (trigger == IOSAPIC_EDGE)
 554                 return &irq_type_iosapic_edge;
 555         else
 556                 return &irq_type_iosapic_level;
 557 }
 558
 559 static int
 560 register_intr (unsigned int gsi, int irq, unsigned char delivery,
 561                unsigned long polarity, unsigned long trigger)
 562 {
 563         struct irq_desc *idesc;
 564         struct irq_chip *irq_type;
 565         int index;
 566         struct iosapic_rte_info *rte;
 567
 568         index = find_iosapic(gsi);
 569         if (index < 0) {
 570                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
 571                        __func__, gsi);
 572                 return -ENODEV;
 573         }
 574
 575         rte = find_rte(irq, gsi);
 576         if (!rte) {
 577                 rte = kzalloc(sizeof (*rte), GFP_ATOMIC);
 578                 if (!rte) {
 579                         printk(KERN_WARNING "%s: cannot allocate memory\n",
 580                                __func__);
 581                         return -ENOMEM;
 582                 }
 583
 584                 rte->iosapic    = &iosapic_lists[index];
 585                 rte->rte_index  = gsi - rte->iosapic->gsi_base;
 586                 rte->refcnt++;
 587                 list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes);
 588                 iosapic_intr_info[irq].count++;
 589                 iosapic_lists[index].rtes_inuse++;
 590         }
 591         else if (rte->refcnt == NO_REF_RTE) {
 592                 struct iosapic_intr_info *info = &iosapic_intr_info[irq];
 593                 if (info->count > 0 &&
 594                     (info->trigger != trigger || info->polarity != polarity)){
 595                         printk (KERN_WARNING
 596                                 "%s: cannot override the interrupt\n",
 597                                 __func__);
 598                         return -EINVAL;
 599                 }
 600                 rte->refcnt++;
 601                 iosapic_intr_info[irq].count++;
 602                 iosapic_lists[index].rtes_inuse++;
 603         }
 604
 605         iosapic_intr_info[irq].polarity = polarity;
 606         iosapic_intr_info[irq].dmode    = delivery;
 607         iosapic_intr_info[irq].trigger  = trigger;
 608
 609         irq_type = iosapic_get_irq_chip(trigger);
 610
 611         idesc = irq_desc + irq;
 612         if (irq_type != NULL && idesc->chip != irq_type) {
 613                 if (idesc->chip != &no_irq_chip)
 614                         printk(KERN_WARNING
 615                                "%s: changing vector %d from %s to %s\n",
 616                                __func__, irq_to_vector(irq),
 617                                idesc->chip->name, irq_type->name);
 618                 idesc->chip = irq_type;
 619         }
 620         if (trigger == IOSAPIC_EDGE)
 621                 __set_irq_handler_unlocked(irq, handle_edge_irq);
 622         else
 623                 __set_irq_handler_unlocked(irq, handle_level_irq);
 624         return 0;
 625 }
 626
 627 static unsigned int
 628 get_target_cpu (unsigned int gsi, int irq)
 629 {
 630 #ifdef CONFIG_SMP
 631         static int cpu = -1;
 632         extern int cpe_vector;
 633         cpumask_t domain = irq_to_domain(irq);
 634
 635         /*
 636          * In case of vector shared by multiple RTEs, all RTEs that
 637          * share the vector need to use the same destination CPU.
 638          */
 639         if (iosapic_intr_info[irq].count)
 640                 return iosapic_intr_info[irq].dest;
 641
 642         /*
 643          * If the platform supports redirection via XTP, let it
 644          * distribute interrupts.
 645          */
 646         if (smp_int_redirect & SMP_IRQ_REDIRECTION)
 647                 return cpu_physical_id(smp_processor_id());
 648
 649         /*
 650          * Some interrupts (ACPI SCI, for instance) are registered
 651          * before the BSP is marked as online.
 652          */
 653         if (!cpu_online(smp_processor_id()))
 654                 return cpu_physical_id(smp_processor_id());
 655
 656 #ifdef CONFIG_ACPI
 657         if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR)
 658                 return get_cpei_target_cpu();
 659 #endif
 660
 661 #ifdef CONFIG_NUMA
 662         {
 663                 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
 664                 const struct cpumask *cpu_mask;
 665
 666                 iosapic_index = find_iosapic(gsi);
 667                 if (iosapic_index < 0 ||
 668                     iosapic_lists[iosapic_index].node == MAX_NUMNODES)
 669                         goto skip_numa_setup;
 670
 671                 cpu_mask = cpumask_of_node(iosapic_lists[iosapic_index].node);
 672                 num_cpus = 0;
 673                 for_each_cpu_and(numa_cpu, cpu_mask, &domain) {
 674                         if (cpu_online(numa_cpu))
 675                                 num_cpus++;
 676                 }
 677
 678                 if (!num_cpus)
 679                         goto skip_numa_setup;
 680
 681                 /* Use irq assignment to distribute across cpus in node */
 682                 cpu_index = irq % num_cpus;
 683
 684                 for_each_cpu_and(numa_cpu, cpu_mask, &domain)
 685                         if (cpu_online(numa_cpu) && i++ >= cpu_index)
 686                                 break;
 687
 688                 if (numa_cpu < nr_cpu_ids)
 689                         return cpu_physical_id(numa_cpu);
 690         }
 691 skip_numa_setup:
 692 #endif
 693         /*
 694          * Otherwise, round-robin interrupt vectors across all the
 695          * processors.  (It'd be nice if we could be smarter in the
 696          * case of NUMA.)
 697          */
 698         do {
 699                 if (++cpu >= nr_cpu_ids)
 700                         cpu = 0;
 701         } while (!cpu_online(cpu) || !cpu_isset(cpu, domain));
 702
 703         return cpu_physical_id(cpu);
 704 #else  /* CONFIG_SMP */
 705         return cpu_physical_id(smp_processor_id());
 706 #endif
 707 }
 708
 709 static inline unsigned char choose_dmode(void)
 710 {
 711 #ifdef CONFIG_SMP
 712         if (smp_int_redirect & SMP_IRQ_REDIRECTION)
 713                 return IOSAPIC_LOWEST_PRIORITY;
 714 #endif
 715         return IOSAPIC_FIXED;
 716 }
 717
 718 /*
 719  * ACPI can describe IOSAPIC interrupts via static tables and namespace
 720  * methods.  This provides an interface to register those interrupts and
 721  * program the IOSAPIC RTE.
 722  */
 723 int
 724 iosapic_register_intr (unsigned int gsi,
 725                        unsigned long polarity, unsigned long trigger)
 726 {
 727         int irq, mask = 1, err;
 728         unsigned int dest;
 729         unsigned long flags;
 730         struct iosapic_rte_info *rte;
 731         u32 low32;
 732         unsigned char dmode;
 733
 734         /*
 735          * If this GSI has already been registered (i.e., it's a
 736          * shared interrupt, or we lost a race to register it),
 737          * don't touch the RTE.
 738          */
 739         spin_lock_irqsave(&iosapic_lock, flags);
 740         irq = __gsi_to_irq(gsi);
 741         if (irq > 0) {
 742                 rte = find_rte(irq, gsi);
 743                 if(iosapic_intr_info[irq].count == 0) {
 744                         assign_irq_vector(irq);
 745                         dynamic_irq_init(irq);
 746                 } else if (rte->refcnt != NO_REF_RTE) {
 747                         rte->refcnt++;
 748                         goto unlock_iosapic_lock;
 749                 }
 750         } else
 751                 irq = create_irq();
 752
 753         /* If vector is running out, we try to find a sharable vector */
 754         if (irq < 0) {
 755                 irq = iosapic_find_sharable_irq(trigger, polarity);
 756                 if (irq < 0)
 757                         goto unlock_iosapic_lock;
 758         }
 759
 760         raw_spin_lock(&irq_desc[irq].lock);
 761         dest = get_target_cpu(gsi, irq);
 762         dmode = choose_dmode();
 763         err = register_intr(gsi, irq, dmode, polarity, trigger);
 764         if (err < 0) {
 765                 raw_spin_unlock(&irq_desc[irq].lock);
 766                 irq = err;
 767                 goto unlock_iosapic_lock;
 768         }
 769
 770         /*
 771          * If the vector is shared and already unmasked for other
 772          * interrupt sources, don't mask it.
 773          */
 774         low32 = iosapic_intr_info[irq].low32;
 775         if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK))
 776                 mask = 0;
 777         set_rte(gsi, irq, dest, mask);
 778
 779         printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
 780                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 781                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 782                cpu_logical_id(dest), dest, irq_to_vector(irq));
 783
 784         raw_spin_unlock(&irq_desc[irq].lock);
 785  unlock_iosapic_lock:
 786         spin_unlock_irqrestore(&iosapic_lock, flags);
 787         return irq;
 788 }
 789
 790 void
 791 iosapic_unregister_intr (unsigned int gsi)
 792 {
 793         unsigned long flags;
 794         int irq, index;
 795         struct irq_desc *idesc;
 796         u32 low32;
 797         unsigned long trigger, polarity;
 798         unsigned int dest;
 799         struct iosapic_rte_info *rte;
 800
 801         /*
 802          * If the irq associated with the gsi is not found,
 803          * iosapic_unregister_intr() is unbalanced. We need to check
 804          * this again after getting locks.
 805          */
 806         irq = gsi_to_irq(gsi);
 807         if (irq < 0) {
 808                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
 809                        gsi);
 810                 WARN_ON(1);
 811                 return;
 812         }
 813
 814         spin_lock_irqsave(&iosapic_lock, flags);
 815         if ((rte = find_rte(irq, gsi)) == NULL) {
 816                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
 817                        gsi);
 818                 WARN_ON(1);
 819                 goto out;
 820         }
 821
 822         if (--rte->refcnt > 0)
 823                 goto out;
 824
 825         idesc = irq_desc + irq;
 826         rte->refcnt = NO_REF_RTE;
 827
 828         /* Mask the interrupt */
 829         low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK;
 830         iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32);
 831
 832         iosapic_intr_info[irq].count--;
 833         index = find_iosapic(gsi);
 834         iosapic_lists[index].rtes_inuse--;
 835         WARN_ON(iosapic_lists[index].rtes_inuse < 0);
 836
 837         trigger  = iosapic_intr_info[irq].trigger;
 838         polarity = iosapic_intr_info[irq].polarity;
 839         dest     = iosapic_intr_info[irq].dest;
 840         printk(KERN_INFO
 841                "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
 842                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 843                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 844                cpu_logical_id(dest), dest, irq_to_vector(irq));
 845
 846         if (iosapic_intr_info[irq].count == 0) {
 847 #ifdef CONFIG_SMP
 848                 /* Clear affinity */
 849                 cpumask_setall(idesc->affinity);
 850 #endif
 851                 /* Clear the interrupt information */
 852                 iosapic_intr_info[irq].dest = 0;
 853                 iosapic_intr_info[irq].dmode = 0;
 854                 iosapic_intr_info[irq].polarity = 0;
 855                 iosapic_intr_info[irq].trigger = 0;
 856                 iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
 857
 858                 /* Destroy and reserve IRQ */
 859                 destroy_and_reserve_irq(irq);
 860         }
 861  out:
 862         spin_unlock_irqrestore(&iosapic_lock, flags);
 863 }
 864
 865 /*
 866  * ACPI calls this when it finds an entry for a platform interrupt.
 867  */
 868 int __init
 869 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
 870                                 int iosapic_vector, u16 eid, u16 id,
 871                                 unsigned long polarity, unsigned long trigger)
 872 {
 873         static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
 874         unsigned char delivery;
 875         int irq, vector, mask = 0;
 876         unsigned int dest = ((id << 8) | eid) & 0xffff;
 877
 878         switch (int_type) {
 879               case ACPI_INTERRUPT_PMI:
 880                 irq = vector = iosapic_vector;
 881                 bind_irq_vector(irq, vector, CPU_MASK_ALL);
 882                 /*
 883                  * since PMI vector is alloc'd by FW(ACPI) not by kernel,
 884                  * we need to make sure the vector is available
 885                  */
 886                 iosapic_reassign_vector(irq);
 887                 delivery = IOSAPIC_PMI;
 888                 break;
 889               case ACPI_INTERRUPT_INIT:
 890                 irq = create_irq();
 891                 if (irq < 0)
 892                         panic("%s: out of interrupt vectors!\n", __func__);
 893                 vector = irq_to_vector(irq);
 894                 delivery = IOSAPIC_INIT;
 895                 break;
 896               case ACPI_INTERRUPT_CPEI:
 897                 irq = vector = IA64_CPE_VECTOR;
 898                 BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
 899                 delivery = IOSAPIC_FIXED;
 900                 mask = 1;
 901                 break;
 902               default:
 903                 printk(KERN_ERR "%s: invalid int type 0x%x\n", __func__,
 904                        int_type);
 905                 return -1;
 906         }
 907
 908         register_intr(gsi, irq, delivery, polarity, trigger);
 909
 910         printk(KERN_INFO
 911                "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
 912                " vector %d\n",
 913                int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
 914                int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 915                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 916                cpu_logical_id(dest), dest, vector);
 917
 918         set_rte(gsi, irq, dest, mask);
 919         return vector;
 920 }
 921
 922 /*
 923  * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
 924  */
 925 void __devinit
 926 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
 927                           unsigned long polarity,
 928                           unsigned long trigger)
 929 {
 930         int vector, irq;
 931         unsigned int dest = cpu_physical_id(smp_processor_id());
 932         unsigned char dmode;
 933
 934         irq = vector = isa_irq_to_vector(isa_irq);
 935         BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
 936         dmode = choose_dmode();
 937         register_intr(gsi, irq, dmode, polarity, trigger);
 938
 939         DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
 940             isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
 941             polarity == IOSAPIC_POL_HIGH ? "high" : "low",
 942             cpu_logical_id(dest), dest, vector);
 943
 944         set_rte(gsi, irq, dest, 1);
 945 }
 946
 947 void __init
 948 ia64_native_iosapic_pcat_compat_init(void)
 949 {
 950         if (pcat_compat) {
 951                 /*
 952                  * Disable the compatibility mode interrupts (8259 style),
 953                  * needs IN/OUT support enabled.
 954                  */
 955                 printk(KERN_INFO
 956                        "%s: Disabling PC-AT compatible 8259 interrupts\n",
 957                        __func__);
 958                 outb(0xff, 0xA1);
 959                 outb(0xff, 0x21);
 960         }
 961 }
 962
 963 void __init
 964 iosapic_system_init (int system_pcat_compat)
 965 {
 966         int irq;
 967
 968         for (irq = 0; irq < NR_IRQS; ++irq) {
 969                 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
 970                 /* mark as unused */
 971                 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
 972
 973                 iosapic_intr_info[irq].count = 0;
 974         }
 975
 976         pcat_compat = system_pcat_compat;
 977         if (pcat_compat)
 978                 iosapic_pcat_compat_init();
 979 }
 980
 981 static inline int
 982 iosapic_alloc (void)
 983 {
 984         int index;
 985
 986         for (index = 0; index < NR_IOSAPICS; index++)
 987                 if (!iosapic_lists[index].addr)
 988                         return index;
 989
 990         printk(KERN_WARNING "%s: failed to allocate iosapic\n", __func__);
 991         return -1;
 992 }
 993
 994 static inline void
 995 iosapic_free (int index)
 996 {
 997         memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0]));
 998 }
 999
1000 static inline int
1001 iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
1002 {
1003         int index;
1004         unsigned int gsi_end, base, end;
1005
1006         /* check gsi range */
1007         gsi_end = gsi_base + ((ver >> 16) & 0xff);
1008         for (index = 0; index < NR_IOSAPICS; index++) {
1009                 if (!iosapic_lists[index].addr)
1010                         continue;
1011
1012                 base = iosapic_lists[index].gsi_base;
1013                 end  = base + iosapic_lists[index].num_rte - 1;
1014
1015                 if (gsi_end < base || end < gsi_base)
1016                         continue; /* OK */
1017
1018                 return -EBUSY;
1019         }
1020         return 0;
1021 }
1022
1023 int __devinit
1024 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1025 {
1026         int num_rte, err, index;
1027         unsigned int isa_irq, ver;
1028         char __iomem *addr;
1029         unsigned long flags;
1030
1031         spin_lock_irqsave(&iosapic_lock, flags);
1032         index = find_iosapic(gsi_base);
1033         if (index >= 0) {
1034                 spin_unlock_irqrestore(&iosapic_lock, flags);
1035                 return -EBUSY;
1036         }
1037
1038         addr = ioremap(phys_addr, 0);
1039         if (addr == NULL) {
1040                 spin_unlock_irqrestore(&iosapic_lock, flags);
1041                 return -ENOMEM;
1042         }
1043         ver = iosapic_version(addr);
1044         if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1045                 iounmap(addr);
1046                 spin_unlock_irqrestore(&iosapic_lock, flags);
1047                 return err;
1048         }
1049
1050         /*
1051          * The MAX_REDIR register holds the highest input pin number
1052          * (starting from 0).  We add 1 so that we can use it for
1053          * number of pins (= RTEs)
1054          */
1055         num_rte = ((ver >> 16) & 0xff) + 1;
1056
1057         index = iosapic_alloc();
1058         iosapic_lists[index].addr = addr;
1059         iosapic_lists[index].gsi_base = gsi_base;
1060         iosapic_lists[index].num_rte = num_rte;
1061 #ifdef CONFIG_NUMA
1062         iosapic_lists[index].node = MAX_NUMNODES;
1063 #endif
1064         spin_lock_init(&iosapic_lists[index].lock);
1065         spin_unlock_irqrestore(&iosapic_lock, flags);
1066
1067         if ((gsi_base == 0) && pcat_compat) {
1068                 /*
1069                  * Map the legacy ISA devices into the IOSAPIC data.  Some of
1070                  * these may get reprogrammed later on with data from the ACPI
1071                  * Interrupt Source Override table.
1072                  */
1073                 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
1074                         iosapic_override_isa_irq(isa_irq, isa_irq,
1075                                                  IOSAPIC_POL_HIGH,
1076                                                  IOSAPIC_EDGE);
1077         }
1078         return 0;
1079 }
1080
1081 #ifdef CONFIG_HOTPLUG
1082 int
1083 iosapic_remove (unsigned int gsi_base)
1084 {
1085         int index, err = 0;
1086         unsigned long flags;
1087
1088         spin_lock_irqsave(&iosapic_lock, flags);
1089         index = find_iosapic(gsi_base);
1090         if (index < 0) {
1091                 printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1092                        __func__, gsi_base);
1093                 goto out;
1094         }
1095
1096         if (iosapic_lists[index].rtes_inuse) {
1097                 err = -EBUSY;
1098                 printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
1099                        __func__, gsi_base);
1100                 goto out;
1101         }
1102
1103         iounmap(iosapic_lists[index].addr);
1104         iosapic_free(index);
1105  out:
1106         spin_unlock_irqrestore(&iosapic_lock, flags);
1107         return err;
1108 }
1109 #endif /* CONFIG_HOTPLUG */
1110
1111 #ifdef CONFIG_NUMA
1112 void __devinit
1113 map_iosapic_to_node(unsigned int gsi_base, int node)
1114 {
1115         int index;
1116
1117         index = find_iosapic(gsi_base);
1118         if (index < 0) {
1119                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1120                        __func__, gsi_base);
1121                 return;
1122         }
1123         iosapic_lists[index].node = node;
1124         return;
1125 }
1126 #endif