2 * linux/arch/ia64/kernel/irq_ia64.c
4 * Copyright (C) 1998-2001 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * 6/10/99: Updated to bring in sync with x86 version to facilitate
9 * support for SMP and different interrupt controllers.
11 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
12 * PCI to vector allocation routine.
13 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
14 * Added CPU Hotplug handling for IPF.
17 #include <linux/module.h>
19 #include <linux/jiffies.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/slab.h>
26 #include <linux/ptrace.h>
27 #include <linux/random.h> /* for rand_initialize_irq() */
28 #include <linux/signal.h>
29 #include <linux/smp.h>
30 #include <linux/threads.h>
31 #include <linux/bitops.h>
32 #include <linux/irq.h>
34 #include <asm/delay.h>
35 #include <asm/intrinsics.h>
37 #include <asm/hw_irq.h>
38 #include <asm/machvec.h>
39 #include <asm/pgtable.h>
40 #include <asm/system.h>
41 #include <asm/tlbflush.h>
44 # include <asm/perfmon.h>
49 #define IRQ_VECTOR_UNASSIGNED (0)
51 #define IRQ_UNUSED (0)
55 /* These can be overridden in platform_irq_init */
56 int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
57 int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
59 /* default base addr of IPI table */
60 void __iomem *ipi_base_addr = ((void __iomem *)
61 (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));
63 static cpumask_t vector_allocation_domain(int cpu);
66 * Legacy IRQ to IA-64 vector translation table.
68 __u8 isa_irq_to_vector_map[16] = {
69 /* 8259 IRQ translation, first 16 entries */
70 0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
71 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
73 EXPORT_SYMBOL(isa_irq_to_vector_map);
75 DEFINE_SPINLOCK(vector_lock);
77 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
78 [0 ... NR_IRQS - 1] = {
79 .vector = IRQ_VECTOR_UNASSIGNED,
80 .domain = CPU_MASK_NONE
84 DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
85 [0 ... IA64_NUM_VECTORS - 1] = IA64_SPURIOUS_INT_VECTOR
88 static cpumask_t vector_table[IA64_NUM_VECTORS] = {
89 [0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
92 static int irq_status[NR_IRQS] = {
93 [0 ... NR_IRQS -1] = IRQ_UNUSED
96 int check_irq_used(int irq)
98 if (irq_status[irq] == IRQ_USED)
104 static void reserve_irq(unsigned int irq)
108 spin_lock_irqsave(&vector_lock, flags);
109 irq_status[irq] = IRQ_RSVD;
110 spin_unlock_irqrestore(&vector_lock, flags);
113 static inline int find_unassigned_irq(void)
117 for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
118 if (irq_status[irq] == IRQ_UNUSED)
123 static inline int find_unassigned_vector(cpumask_t domain)
128 cpus_and(mask, domain, cpu_online_map);
129 if (cpus_empty(mask))
132 for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
133 vector = IA64_FIRST_DEVICE_VECTOR + pos;
134 cpus_and(mask, domain, vector_table[vector]);
135 if (!cpus_empty(mask))
142 static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
146 struct irq_cfg *cfg = &irq_cfg[irq];
148 cpus_and(mask, domain, cpu_online_map);
149 if (cpus_empty(mask))
151 if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
153 if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
155 for_each_cpu_mask(cpu, mask)
156 per_cpu(vector_irq, cpu)[vector] = irq;
157 cfg->vector = vector;
158 cfg->domain = domain;
159 irq_status[irq] = IRQ_USED;
160 cpus_or(vector_table[vector], vector_table[vector], domain);
164 int bind_irq_vector(int irq, int vector, cpumask_t domain)
169 spin_lock_irqsave(&vector_lock, flags);
170 ret = __bind_irq_vector(irq, vector, domain);
171 spin_unlock_irqrestore(&vector_lock, flags);
175 static void __clear_irq_vector(int irq)
180 struct irq_cfg *cfg = &irq_cfg[irq];
182 BUG_ON((unsigned)irq >= NR_IRQS);
183 BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
184 vector = cfg->vector;
185 domain = cfg->domain;
186 cpus_and(mask, cfg->domain, cpu_online_map);
187 for_each_cpu_mask(cpu, mask)
188 per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
189 cfg->vector = IRQ_VECTOR_UNASSIGNED;
190 cfg->domain = CPU_MASK_NONE;
191 irq_status[irq] = IRQ_UNUSED;
192 cpus_andnot(vector_table[vector], vector_table[vector], domain);
195 static void clear_irq_vector(int irq)
199 spin_lock_irqsave(&vector_lock, flags);
200 __clear_irq_vector(irq);
201 spin_unlock_irqrestore(&vector_lock, flags);
205 assign_irq_vector (int irq)
213 spin_lock_irqsave(&vector_lock, flags);
214 for_each_online_cpu(cpu) {
215 domain = vector_allocation_domain(cpu);
216 vector = find_unassigned_vector(domain);
222 if (irq == AUTO_ASSIGN)
224 BUG_ON(__bind_irq_vector(irq, vector, domain));
226 spin_unlock_irqrestore(&vector_lock, flags);
231 free_irq_vector (int vector)
233 if (vector < IA64_FIRST_DEVICE_VECTOR ||
234 vector > IA64_LAST_DEVICE_VECTOR)
236 clear_irq_vector(vector);
240 reserve_irq_vector (int vector)
242 if (vector < IA64_FIRST_DEVICE_VECTOR ||
243 vector > IA64_LAST_DEVICE_VECTOR)
245 return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
249 * Initialize vector_irq on a new cpu. This function must be called
250 * with vector_lock held.
252 void __setup_vector_irq(int cpu)
256 /* Clear vector_irq */
257 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
258 per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
259 /* Mark the inuse vectors */
260 for (irq = 0; irq < NR_IRQS; ++irq) {
261 if (!cpu_isset(cpu, irq_cfg[irq].domain))
263 vector = irq_to_vector(irq);
264 per_cpu(vector_irq, cpu)[vector] = irq;
268 #if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
269 static enum vector_domain_type {
272 } vector_domain_type = VECTOR_DOMAIN_NONE;
274 static cpumask_t vector_allocation_domain(int cpu)
276 if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
277 return cpumask_of_cpu(cpu);
281 static int __init parse_vector_domain(char *arg)
285 if (!strcmp(arg, "percpu")) {
286 vector_domain_type = VECTOR_DOMAIN_PERCPU;
291 early_param("vector", parse_vector_domain);
293 static cpumask_t vector_allocation_domain(int cpu)
300 void destroy_and_reserve_irq(unsigned int irq)
302 dynamic_irq_cleanup(irq);
304 clear_irq_vector(irq);
308 static int __reassign_irq_vector(int irq, int cpu)
310 struct irq_cfg *cfg = &irq_cfg[irq];
314 if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
316 if (cpu_isset(cpu, cfg->domain))
318 domain = vector_allocation_domain(cpu);
319 vector = find_unassigned_vector(domain);
322 __clear_irq_vector(irq);
323 BUG_ON(__bind_irq_vector(irq, vector, domain));
327 int reassign_irq_vector(int irq, int cpu)
332 spin_lock_irqsave(&vector_lock, flags);
333 ret = __reassign_irq_vector(irq, cpu);
334 spin_unlock_irqrestore(&vector_lock, flags);
339 * Dynamic irq allocate and deallocation for MSI
344 int irq, vector, cpu;
347 irq = vector = -ENOSPC;
348 spin_lock_irqsave(&vector_lock, flags);
349 for_each_online_cpu(cpu) {
350 domain = vector_allocation_domain(cpu);
351 vector = find_unassigned_vector(domain);
357 irq = find_unassigned_irq();
360 BUG_ON(__bind_irq_vector(irq, vector, domain));
362 spin_unlock_irqrestore(&vector_lock, flags);
364 dynamic_irq_init(irq);
368 void destroy_irq(unsigned int irq)
370 dynamic_irq_cleanup(irq);
371 clear_irq_vector(irq);
375 # define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
376 # define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
378 # define IS_RESCHEDULE(vec) (0)
379 # define IS_LOCAL_TLB_FLUSH(vec) (0)
382 * That's where the IVT branches when we get an external
383 * interrupt. This branches to the correct hardware IRQ handler via
387 ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
389 struct pt_regs *old_regs = set_irq_regs(regs);
390 unsigned long saved_tpr;
394 unsigned long bsp, sp;
397 * Note: if the interrupt happened while executing in
398 * the context switch routine (ia64_switch_to), we may
399 * get a spurious stack overflow here. This is
400 * because the register and the memory stack are not
401 * switched atomically.
403 bsp = ia64_getreg(_IA64_REG_AR_BSP);
404 sp = ia64_getreg(_IA64_REG_SP);
406 if ((sp - bsp) < 1024) {
407 static unsigned char count;
408 static long last_time;
410 if (jiffies - last_time > 5*HZ)
414 printk("ia64_handle_irq: DANGER: less than "
415 "1KB of free stack space!!\n"
416 "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
420 #endif /* IRQ_DEBUG */
423 * Always set TPR to limit maximum interrupt nesting depth to
424 * 16 (without this, it would be ~240, which could easily lead
425 * to kernel stack overflows).
428 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
430 while (vector != IA64_SPURIOUS_INT_VECTOR) {
431 if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
432 smp_local_flush_tlb();
433 kstat_this_cpu.irqs[vector]++;
434 } else if (unlikely(IS_RESCHEDULE(vector)))
435 kstat_this_cpu.irqs[vector]++;
437 ia64_setreg(_IA64_REG_CR_TPR, vector);
440 generic_handle_irq(local_vector_to_irq(vector));
443 * Disable interrupts and send EOI:
446 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
449 vector = ia64_get_ivr();
452 * This must be done *after* the ia64_eoi(). For example, the keyboard softirq
453 * handler needs to be able to wait for further keyboard interrupts, which can't
454 * come through until ia64_eoi() has been done.
457 set_irq_regs(old_regs);
460 #ifdef CONFIG_HOTPLUG_CPU
462 * This function emulates a interrupt processing when a cpu is about to be
465 void ia64_process_pending_intr(void)
468 unsigned long saved_tpr;
469 extern unsigned int vectors_in_migration[NR_IRQS];
471 vector = ia64_get_ivr();
474 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
478 * Perform normal interrupt style processing
480 while (vector != IA64_SPURIOUS_INT_VECTOR) {
481 if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
482 smp_local_flush_tlb();
483 kstat_this_cpu.irqs[vector]++;
484 } else if (unlikely(IS_RESCHEDULE(vector)))
485 kstat_this_cpu.irqs[vector]++;
487 struct pt_regs *old_regs = set_irq_regs(NULL);
489 ia64_setreg(_IA64_REG_CR_TPR, vector);
493 * Now try calling normal ia64_handle_irq as it would have got called
494 * from a real intr handler. Try passing null for pt_regs, hopefully
495 * it will work. I hope it works!.
496 * Probably could shared code.
498 vectors_in_migration[local_vector_to_irq(vector)]=0;
499 generic_handle_irq(local_vector_to_irq(vector));
500 set_irq_regs(old_regs);
503 * Disable interrupts and send EOI
506 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
509 vector = ia64_get_ivr();
518 static irqreturn_t dummy_handler (int irq, void *dev_id)
522 extern irqreturn_t handle_IPI (int irq, void *dev_id);
524 static struct irqaction ipi_irqaction = {
525 .handler = handle_IPI,
526 .flags = IRQF_DISABLED,
530 static struct irqaction resched_irqaction = {
531 .handler = dummy_handler,
532 .flags = IRQF_DISABLED,
536 static struct irqaction tlb_irqaction = {
537 .handler = dummy_handler,
538 .flags = IRQF_DISABLED,
545 register_percpu_irq (ia64_vector vec, struct irqaction *action)
551 BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
552 desc = irq_desc + irq;
553 desc->status |= IRQ_PER_CPU;
554 desc->chip = &irq_type_ia64_lsapic;
556 setup_irq(irq, action);
562 register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
564 register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
565 register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
566 register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
568 #ifdef CONFIG_PERFMON
575 ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
577 void __iomem *ipi_addr;
578 unsigned long ipi_data;
579 unsigned long phys_cpu_id;
582 phys_cpu_id = cpu_physical_id(cpu);
584 phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
588 * cpu number is in 8bit ID and 8bit EID
591 ipi_data = (delivery_mode << 8) | (vector & 0xff);
592 ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));
594 writeq(ipi_data, ipi_addr);