2 * Architecture-specific setup.
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
24 #include <linux/config.h>
25 #include <linux/module.h>
26 #include <linux/init.h>
28 #include <linux/acpi.h>
29 #include <linux/bootmem.h>
30 #include <linux/console.h>
31 #include <linux/delay.h>
32 #include <linux/kernel.h>
33 #include <linux/reboot.h>
34 #include <linux/sched.h>
35 #include <linux/seq_file.h>
36 #include <linux/string.h>
37 #include <linux/threads.h>
38 #include <linux/tty.h>
39 #include <linux/serial.h>
40 #include <linux/serial_core.h>
41 #include <linux/efi.h>
42 #include <linux/initrd.h>
45 #include <asm/machvec.h>
47 #include <asm/meminit.h>
49 #include <asm/patch.h>
50 #include <asm/pgtable.h>
51 #include <asm/processor.h>
53 #include <asm/sections.h>
54 #include <asm/serial.h>
55 #include <asm/setup.h>
57 #include <asm/system.h>
58 #include <asm/unistd.h>
60 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
61 # error "struct cpuinfo_ia64 too big!"
65 unsigned long __per_cpu_offset[NR_CPUS];
66 EXPORT_SYMBOL(__per_cpu_offset);
69 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
70 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
71 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
72 unsigned long ia64_cycles_per_usec;
73 struct ia64_boot_param *ia64_boot_param;
74 struct screen_info screen_info;
75 unsigned long vga_console_iobase;
76 unsigned long vga_console_membase;
78 unsigned long ia64_max_cacheline_size;
79 unsigned long ia64_iobase; /* virtual address for I/O accesses */
80 EXPORT_SYMBOL(ia64_iobase);
81 struct io_space io_space[MAX_IO_SPACES];
82 EXPORT_SYMBOL(io_space);
83 unsigned int num_io_spaces;
86 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
87 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
88 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
89 * address of the second buffer must be aligned to (merge_mask+1) in order to be
90 * mergeable). By default, we assume there is no I/O MMU which can merge physically
91 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
94 unsigned long ia64_max_iommu_merge_mask = ~0UL;
95 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
98 * We use a special marker for the end of memory and it uses the extra (+1) slot
100 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
101 int num_rsvd_regions;
105 * Filter incoming memory segments based on the primitive map created from the boot
106 * parameters. Segments contained in the map are removed from the memory ranges. A
107 * caller-specified function is called with the memory ranges that remain after filtering.
108 * This routine does not assume the incoming segments are sorted.
111 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
113 unsigned long range_start, range_end, prev_start;
114 void (*func)(unsigned long, unsigned long, int);
118 if (start == PAGE_OFFSET) {
119 printk(KERN_WARNING "warning: skipping physical page 0\n");
121 if (start >= end) return 0;
125 * lowest possible address(walker uses virtual)
127 prev_start = PAGE_OFFSET;
130 for (i = 0; i < num_rsvd_regions; ++i) {
131 range_start = max(start, prev_start);
132 range_end = min(end, rsvd_region[i].start);
134 if (range_start < range_end)
135 call_pernode_memory(__pa(range_start), range_end - range_start, func);
137 /* nothing more available in this segment */
138 if (range_end == end) return 0;
140 prev_start = rsvd_region[i].end;
142 /* end of memory marker allows full processing inside loop body */
147 sort_regions (struct rsvd_region *rsvd_region, int max)
151 /* simple bubble sorting */
153 for (j = 0; j < max; ++j) {
154 if (rsvd_region[j].start > rsvd_region[j+1].start) {
155 struct rsvd_region tmp;
156 tmp = rsvd_region[j];
157 rsvd_region[j] = rsvd_region[j + 1];
158 rsvd_region[j + 1] = tmp;
165 * reserve_memory - setup reserved memory areas
167 * Setup the reserved memory areas set aside for the boot parameters,
168 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
169 * see include/asm-ia64/meminit.h if you need to define more.
172 reserve_memory (void)
177 * none of the entries in this table overlap
179 rsvd_region[n].start = (unsigned long) ia64_boot_param;
180 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
183 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
184 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
187 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
188 rsvd_region[n].end = (rsvd_region[n].start
189 + strlen(__va(ia64_boot_param->command_line)) + 1);
192 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
193 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
196 #ifdef CONFIG_BLK_DEV_INITRD
197 if (ia64_boot_param->initrd_start) {
198 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
199 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
204 /* end of memory marker */
205 rsvd_region[n].start = ~0UL;
206 rsvd_region[n].end = ~0UL;
209 num_rsvd_regions = n;
211 sort_regions(rsvd_region, num_rsvd_regions);
215 * find_initrd - get initrd parameters from the boot parameter structure
217 * Grab the initrd start and end from the boot parameter struct given us by
223 #ifdef CONFIG_BLK_DEV_INITRD
224 if (ia64_boot_param->initrd_start) {
225 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
226 initrd_end = initrd_start+ia64_boot_param->initrd_size;
228 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
229 initrd_start, ia64_boot_param->initrd_size);
237 extern unsigned long ia64_iobase;
238 unsigned long phys_iobase;
241 * Set `iobase' to the appropriate address in region 6 (uncached access range).
243 * The EFI memory map is the "preferred" location to get the I/O port space base,
244 * rather the relying on AR.KR0. This should become more clear in future SAL
245 * specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
246 * found in the memory map.
248 phys_iobase = efi_get_iobase();
250 /* set AR.KR0 since this is all we use it for anyway */
251 ia64_set_kr(IA64_KR_IO_BASE, phys_iobase);
253 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
254 printk(KERN_INFO "No I/O port range found in EFI memory map, falling back "
256 printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase);
258 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
260 /* setup legacy IO port space */
261 io_space[0].mmio_base = ia64_iobase;
262 io_space[0].sparse = 1;
267 * early_console_setup - setup debugging console
269 * Consoles started here require little enough setup that we can start using
270 * them very early in the boot process, either right after the machine
271 * vector initialization, or even before if the drivers can detect their hw.
273 * Returns non-zero if a console couldn't be setup.
275 static inline int __init
276 early_console_setup (char *cmdline)
280 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
282 extern int sn_serial_console_early_setup(void);
283 if (!sn_serial_console_early_setup())
287 #ifdef CONFIG_EFI_PCDP
288 if (!efi_setup_pcdp_console(cmdline))
291 #ifdef CONFIG_SERIAL_8250_CONSOLE
292 if (!early_serial_console_init(cmdline))
296 return (earlycons) ? 0 : -1;
300 mark_bsp_online (void)
303 /* If we register an early console, allow CPU 0 to printk */
304 cpu_set(smp_processor_id(), cpu_online_map);
310 check_for_logical_procs (void)
312 pal_logical_to_physical_t info;
315 status = ia64_pal_logical_to_phys(0, &info);
317 printk(KERN_INFO "No logical to physical processor mapping "
322 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
327 * Total number of siblings that BSP has. Though not all of them
328 * may have booted successfully. The correct number of siblings
329 * booted is in info.overview_num_log.
331 smp_num_siblings = info.overview_tpc;
332 smp_num_cpucores = info.overview_cpp;
337 setup_arch (char **cmdline_p)
341 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
343 *cmdline_p = __va(ia64_boot_param->command_line);
344 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
349 #ifdef CONFIG_IA64_GENERIC
351 const char *mvec_name = strstr (*cmdline_p, "machvec=");
359 end = strchr (mvec_name, ' ');
361 len = end - mvec_name;
363 len = strlen (mvec_name);
364 len = min(len, sizeof (str) - 1);
365 strncpy (str, mvec_name, len);
369 mvec_name = acpi_get_sysname();
370 machvec_init(mvec_name);
374 if (early_console_setup(*cmdline_p) == 0)
377 #ifdef CONFIG_ACPI_BOOT
378 /* Initialize the ACPI boot-time table parser */
380 # ifdef CONFIG_ACPI_NUMA
385 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
387 #endif /* CONFIG_APCI_BOOT */
391 /* process SAL system table: */
392 ia64_sal_init(efi.sal_systab);
395 cpu_physical_id(0) = hard_smp_processor_id();
397 cpu_set(0, cpu_sibling_map[0]);
398 cpu_set(0, cpu_core_map[0]);
400 check_for_logical_procs();
401 if (smp_num_cpucores > 1)
403 "cpu package is Multi-Core capable: number of cores=%d\n",
405 if (smp_num_siblings > 1)
407 "cpu package is Multi-Threading capable: number of siblings=%d\n",
411 cpu_init(); /* initialize the bootstrap CPU */
413 #ifdef CONFIG_ACPI_BOOT
419 # if defined(CONFIG_DUMMY_CONSOLE)
420 conswitchp = &dummy_con;
422 # if defined(CONFIG_VGA_CONSOLE)
424 * Non-legacy systems may route legacy VGA MMIO range to system
425 * memory. vga_con probes the MMIO hole, so memory looks like
426 * a VGA device to it. The EFI memory map can tell us if it's
427 * memory so we can avoid this problem.
429 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
430 conswitchp = &vga_con;
435 /* enable IA-64 Machine Check Abort Handling unless disabled */
436 if (!strstr(saved_command_line, "nomca"))
439 platform_setup(cmdline_p);
444 * Display cpu info for all cpu's.
447 show_cpuinfo (struct seq_file *m, void *v)
450 # define lpj c->loops_per_jiffy
451 # define cpunum c->cpu
453 # define lpj loops_per_jiffy
458 const char *feature_name;
460 { 1UL << 0, "branchlong" },
461 { 1UL << 1, "spontaneous deferral"},
462 { 1UL << 2, "16-byte atomic ops" }
464 char family[32], features[128], *cp, sep;
465 struct cpuinfo_ia64 *c = v;
472 case 0x07: memcpy(family, "Itanium", 8); break;
473 case 0x1f: memcpy(family, "Itanium 2", 10); break;
474 default: sprintf(family, "%u", c->family); break;
477 /* build the feature string: */
478 memcpy(features, " standard", 10);
481 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
482 if (mask & feature_bits[i].mask) {
487 strcpy(cp, feature_bits[i].feature_name);
488 cp += strlen(feature_bits[i].feature_name);
489 mask &= ~feature_bits[i].mask;
493 /* print unknown features as a hex value: */
496 sprintf(cp, " 0x%lx", mask);
507 "features :%s\n" /* don't change this---it _is_ right! */
510 "cpu MHz : %lu.%06lu\n"
511 "itc MHz : %lu.%06lu\n"
512 "BogoMIPS : %lu.%02lu\n",
513 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
514 features, c->ppn, c->number,
515 c->proc_freq / 1000000, c->proc_freq % 1000000,
516 c->itc_freq / 1000000, c->itc_freq % 1000000,
517 lpj*HZ/500000, (lpj*HZ/5000) % 100);
519 seq_printf(m, "siblings : %u\n", c->num_log);
520 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
525 c->socket_id, c->core_id, c->thread_id);
533 c_start (struct seq_file *m, loff_t *pos)
536 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
539 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
543 c_next (struct seq_file *m, void *v, loff_t *pos)
546 return c_start(m, pos);
550 c_stop (struct seq_file *m, void *v)
554 struct seq_operations cpuinfo_op = {
562 identify_cpu (struct cpuinfo_ia64 *c)
565 unsigned long bits[5];
571 u64 ppn; /* processor serial number */
575 unsigned revision : 8;
578 unsigned archrev : 8;
579 unsigned reserved : 24;
585 pal_vm_info_1_u_t vm1;
586 pal_vm_info_2_u_t vm2;
588 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
591 for (i = 0; i < 5; ++i)
592 cpuid.bits[i] = ia64_get_cpuid(i);
594 memcpy(c->vendor, cpuid.field.vendor, 16);
596 c->cpu = smp_processor_id();
598 /* below default values will be overwritten by identify_siblings()
599 * for Multi-Threading/Multi-Core capable cpu's
601 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
604 identify_siblings(c);
606 c->ppn = cpuid.field.ppn;
607 c->number = cpuid.field.number;
608 c->revision = cpuid.field.revision;
609 c->model = cpuid.field.model;
610 c->family = cpuid.field.family;
611 c->archrev = cpuid.field.archrev;
612 c->features = cpuid.field.features;
614 status = ia64_pal_vm_summary(&vm1, &vm2);
615 if (status == PAL_STATUS_SUCCESS) {
616 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
617 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
619 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
620 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
624 setup_per_cpu_areas (void)
626 /* start_kernel() requires this... */
630 get_max_cacheline_size (void)
632 unsigned long line_size, max = 1;
633 u64 l, levels, unique_caches;
634 pal_cache_config_info_t cci;
637 status = ia64_pal_cache_summary(&levels, &unique_caches);
639 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
640 __FUNCTION__, status);
641 max = SMP_CACHE_BYTES;
645 for (l = 0; l < levels; ++l) {
646 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
650 "%s: ia64_pal_cache_config_info(l=%lu) failed (status=%ld)\n",
651 __FUNCTION__, l, status);
652 max = SMP_CACHE_BYTES;
654 line_size = 1 << cci.pcci_line_size;
659 if (max > ia64_max_cacheline_size)
660 ia64_max_cacheline_size = max;
664 * cpu_init() initializes state that is per-CPU. This function acts
665 * as a 'CPU state barrier', nothing should get across.
670 extern void __devinit ia64_mmu_init (void *);
671 unsigned long num_phys_stacked;
672 pal_vm_info_2_u_t vmi;
673 unsigned int max_ctx;
674 struct cpuinfo_ia64 *cpu_info;
677 cpu_data = per_cpu_init();
680 * We set ar.k3 so that assembly code in MCA handler can compute
681 * physical addresses of per cpu variables with a simple:
682 * phys = ar.k3 + &per_cpu_var
684 ia64_set_kr(IA64_KR_PER_CPU_DATA,
685 ia64_tpa(cpu_data) - (long) __per_cpu_start);
687 get_max_cacheline_size();
690 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
691 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
692 * depends on the data returned by identify_cpu(). We break the dependency by
693 * accessing cpu_data() through the canonical per-CPU address.
695 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
696 identify_cpu(cpu_info);
698 #ifdef CONFIG_MCKINLEY
700 # define FEATURE_SET 16
701 struct ia64_pal_retval iprv;
703 if (cpu_info->family == 0x1f) {
704 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
705 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
706 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
707 (iprv.v1 | 0x80), FEATURE_SET, 0);
712 /* Clear the stack memory reserved for pt_regs: */
713 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
715 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
718 * Initialize the page-table base register to a global
719 * directory with all zeroes. This ensure that we can handle
720 * TLB-misses to user address-space even before we created the
721 * first user address-space. This may happen, e.g., due to
722 * aggressive use of lfetch.fault.
724 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
727 * Initialize default control register to defer speculative faults except
728 * for those arising from TLB misses, which are not deferred. The
729 * kernel MUST NOT depend on a particular setting of these bits (in other words,
730 * the kernel must have recovery code for all speculative accesses). Turn on
731 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
732 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
735 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
736 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
737 atomic_inc(&init_mm.mm_count);
738 current->active_mm = &init_mm;
742 ia64_mmu_init(ia64_imva(cpu_data));
743 ia64_mca_cpu_init(ia64_imva(cpu_data));
745 #ifdef CONFIG_IA32_SUPPORT
749 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
752 /* disable all local interrupt sources: */
753 ia64_set_itv(1 << 16);
754 ia64_set_lrr0(1 << 16);
755 ia64_set_lrr1(1 << 16);
756 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
757 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
759 /* clear TPR & XTP to enable all interrupt classes: */
760 ia64_setreg(_IA64_REG_CR_TPR, 0);
765 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
766 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
767 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
769 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
770 max_ctx = (1U << 15) - 1; /* use architected minimum */
772 while (max_ctx < ia64_ctx.max_ctx) {
773 unsigned int old = ia64_ctx.max_ctx;
774 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
778 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
779 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
781 num_phys_stacked = 96;
783 /* size of physical stacked register partition plus 8 bytes: */
784 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
791 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
792 (unsigned long) __end___mckinley_e9_bundles);