2 * linux/arch/m32r/platforms/m32700ut/setup.c
4 * Setup routines for Renesas M32700UT Board
6 * Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto, Takeo Takahashi
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file "COPYING" in the main directory of this
11 * archive for more details.
14 #include <linux/irq.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
19 #include <asm/system.h>
24 * M32700 Interrupt Control Unit (Level 1)
26 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
28 icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
30 static void disable_m32700ut_irq(unsigned int irq)
32 unsigned long port, data;
35 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
39 static void enable_m32700ut_irq(unsigned int irq)
41 unsigned long port, data;
44 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
48 static void mask_m32700ut(struct irq_data *data)
50 disable_m32700ut_irq(data->irq);
53 static void unmask_m32700ut(struct irq_data *data)
55 enable_m32700ut_irq(data->irq);
58 static void shutdown_m32700ut(struct irq_data *data)
62 port = irq2port(data->irq);
63 outl(M32R_ICUCR_ILEVEL7, port);
66 static struct irq_chip m32700ut_irq_type =
68 .name = "M32700UT-IRQ",
69 .irq_shutdown = shutdown_m32700ut,
70 .irq_mask = mask_m32700ut,
71 .irq_unmask = unmask_m32700ut
75 * Interrupt Control Unit of PLD on M32700UT (Level 2)
77 #define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
78 #define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
79 (((x) - 1) * sizeof(unsigned short)))
82 unsigned short icucr; /* ICU Control Register */
85 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
87 static void disable_m32700ut_pld_irq(unsigned int irq)
89 unsigned long port, data;
92 pldirq = irq2pldirq(irq);
93 port = pldirq2port(pldirq);
94 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
98 static void enable_m32700ut_pld_irq(unsigned int irq)
100 unsigned long port, data;
103 pldirq = irq2pldirq(irq);
104 port = pldirq2port(pldirq);
105 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
109 static void mask_m32700ut_pld(struct irq_data *data)
111 disable_m32700ut_pld_irq(data->irq);
114 static void unmask_m32700ut_pld(struct irq_data *data)
116 enable_m32700ut_pld_irq(data->irq);
117 enable_m32700ut_irq(M32R_IRQ_INT1);
120 static void shutdown_m32700ut_pld_irq(struct irq_data *data)
125 pldirq = irq2pldirq(data->irq);
126 port = pldirq2port(pldirq);
127 outw(PLD_ICUCR_ILEVEL7, port);
130 static struct irq_chip m32700ut_pld_irq_type =
132 .name = "M32700UT-PLD-IRQ",
133 .irq_shutdown = shutdown_m32700ut_pld_irq,
134 .irq_mask = mask_m32700ut_pld,
135 .irq_unmask = unmask_m32700ut_pld,
139 * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
141 #define irq2lanpldirq(x) ((x) - M32700UT_LAN_PLD_IRQ_BASE)
142 #define lanpldirq2port(x) (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
143 (((x) - 1) * sizeof(unsigned short)))
145 static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
147 static void disable_m32700ut_lanpld_irq(unsigned int irq)
149 unsigned long port, data;
152 pldirq = irq2lanpldirq(irq);
153 port = lanpldirq2port(pldirq);
154 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
158 static void enable_m32700ut_lanpld_irq(unsigned int irq)
160 unsigned long port, data;
163 pldirq = irq2lanpldirq(irq);
164 port = lanpldirq2port(pldirq);
165 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
169 static void mask_m32700ut_lanpld(struct irq_data *data)
171 disable_m32700ut_lanpld_irq(data->irq);
174 static void unmask_m32700ut_lanpld(struct irq_data *data)
176 enable_m32700ut_lanpld_irq(data->irq);
177 enable_m32700ut_irq(M32R_IRQ_INT0);
180 static void shutdown_m32700ut_lanpld(struct irq_data *data)
185 pldirq = irq2lanpldirq(data->irq);
186 port = lanpldirq2port(pldirq);
187 outw(PLD_ICUCR_ILEVEL7, port);
190 static struct irq_chip m32700ut_lanpld_irq_type =
192 .name = "M32700UT-PLD-LAN-IRQ",
193 .irq_shutdown = shutdown_m32700ut_lanpld,
194 .irq_mask = mask_m32700ut_lanpld,
195 .irq_unmask = unmask_m32700ut_lanpld,
199 * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
201 #define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE)
202 #define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
203 (((x) - 1) * sizeof(unsigned short)))
205 static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
207 static void disable_m32700ut_lcdpld_irq(unsigned int irq)
209 unsigned long port, data;
212 pldirq = irq2lcdpldirq(irq);
213 port = lcdpldirq2port(pldirq);
214 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
218 static void enable_m32700ut_lcdpld_irq(unsigned int irq)
220 unsigned long port, data;
223 pldirq = irq2lcdpldirq(irq);
224 port = lcdpldirq2port(pldirq);
225 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
229 static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
231 disable_m32700ut_lcdpld_irq(irq);
234 static void end_m32700ut_lcdpld_irq(unsigned int irq)
236 enable_m32700ut_lcdpld_irq(irq);
237 enable_m32700ut_irq(M32R_IRQ_INT2);
240 static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
242 enable_m32700ut_lcdpld_irq(irq);
246 static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
251 pldirq = irq2lcdpldirq(irq);
252 port = lcdpldirq2port(pldirq);
253 outw(PLD_ICUCR_ILEVEL7, port);
256 static struct irq_chip m32700ut_lcdpld_irq_type =
258 .name = "M32700UT-PLD-LCD-IRQ",
259 .startup = startup_m32700ut_lcdpld_irq,
260 .shutdown = shutdown_m32700ut_lcdpld_irq,
261 .enable = enable_m32700ut_lcdpld_irq,
262 .disable = disable_m32700ut_lcdpld_irq,
263 .ack = mask_and_ack_m32700ut_lcdpld,
264 .end = end_m32700ut_lcdpld_irq
267 void __init init_IRQ(void)
269 #if defined(CONFIG_SMC91X)
270 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
271 set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN,
272 &m32700ut_lanpld_irq_type, handle_level_irq);
273 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
274 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
275 #endif /* CONFIG_SMC91X */
277 /* MFT2 : system timer */
278 set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
280 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
281 disable_m32700ut_irq(M32R_IRQ_MFT2);
284 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
286 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
287 disable_m32700ut_irq(M32R_IRQ_SIO0_R);
290 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
292 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
293 disable_m32700ut_irq(M32R_IRQ_SIO0_S);
296 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
298 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
299 disable_m32700ut_irq(M32R_IRQ_SIO1_R);
302 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
304 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
305 disable_m32700ut_irq(M32R_IRQ_SIO1_S);
308 set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
310 icu_data[M32R_IRQ_DMA1].icucr = 0;
311 disable_m32700ut_irq(M32R_IRQ_DMA1);
313 #ifdef CONFIG_SERIAL_M32R_PLDSIO
314 /* INT#1: SIO0 Receive on PLD */
315 set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
317 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
318 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
320 /* INT#1: SIO0 Send on PLD */
321 set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
323 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
324 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
325 #endif /* CONFIG_SERIAL_M32R_PLDSIO */
327 /* INT#1: CFC IREQ on PLD */
328 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
330 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
331 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
333 /* INT#1: CFC Insert on PLD */
334 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
336 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
337 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
339 /* INT#1: CFC Eject on PLD */
340 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
342 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
343 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
346 * INT0# is used for LAN, DIO
349 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
350 enable_m32700ut_irq(M32R_IRQ_INT0);
353 * INT1# is used for UART, MMC, CF Controller in FPGA.
356 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
357 enable_m32700ut_irq(M32R_IRQ_INT1);
359 #if defined(CONFIG_USB)
360 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
361 set_irq_chip(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type);
363 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
364 disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
367 * INT2# is used for BAT, USB, AUDIO
370 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
371 enable_m32700ut_irq(M32R_IRQ_INT2);
373 #if defined(CONFIG_VIDEO_M32R_AR)
375 * INT3# is used for AR
377 set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
379 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
380 disable_m32700ut_irq(M32R_IRQ_INT3);
381 #endif /* CONFIG_VIDEO_M32R_AR */
384 #if defined(CONFIG_SMC91X)
386 #define LAN_IOSTART 0x300
387 #define LAN_IOEND 0x320
388 static struct resource smc91x_resources[] = {
390 .start = (LAN_IOSTART),
392 .flags = IORESOURCE_MEM,
395 .start = M32700UT_LAN_IRQ_LAN,
396 .end = M32700UT_LAN_IRQ_LAN,
397 .flags = IORESOURCE_IRQ,
401 static struct platform_device smc91x_device = {
404 .num_resources = ARRAY_SIZE(smc91x_resources),
405 .resource = smc91x_resources,
409 #if defined(CONFIG_FB_S1D13XXX)
411 #include <video/s1d13xxxfb.h>
412 #include <asm/s1d13806.h>
414 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
415 .initregs = s1d13xxxfb_initregs,
416 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
417 .platform_init_video = NULL,
419 .platform_suspend_video = NULL,
420 .platform_resume_video = NULL,
424 static struct resource s1d13xxxfb_resources[] = {
426 .start = 0x10600000UL,
428 .flags = IORESOURCE_MEM,
431 .start = 0x10400000UL,
433 .flags = IORESOURCE_MEM,
437 static struct platform_device s1d13xxxfb_device = {
438 .name = S1D_DEVICENAME,
441 .platform_data = &s1d13xxxfb_data,
443 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
444 .resource = s1d13xxxfb_resources,
448 static int __init platform_init(void)
450 #if defined(CONFIG_SMC91X)
451 platform_device_register(&smc91x_device);
453 #if defined(CONFIG_FB_S1D13XXX)
454 platform_device_register(&s1d13xxxfb_device);
458 arch_initcall(platform_init);