2 * linux/arch/m32r/platforms/opsput/setup.c
4 * Setup routines for Renesas OPSPUT Board
6 * Copyright (c) 2002-2005
7 * Hiroyuki Kondo, Hirokazu Takata,
8 * Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
10 * This file is subject to the terms and conditions of the GNU General
11 * Public License. See the file "COPYING" in the main directory of this
12 * archive for more details.
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
20 #include <asm/system.h>
25 * OPSP Interrupt Control Unit (Level 1)
27 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
29 icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
31 static void disable_opsput_irq(unsigned int irq)
33 unsigned long port, data;
36 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
40 static void enable_opsput_irq(unsigned int irq)
42 unsigned long port, data;
45 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
49 static void mask_and_ack_opsput(unsigned int irq)
51 disable_opsput_irq(irq);
54 static void end_opsput_irq(unsigned int irq)
56 enable_opsput_irq(irq);
59 static unsigned int startup_opsput_irq(unsigned int irq)
61 enable_opsput_irq(irq);
65 static void shutdown_opsput_irq(unsigned int irq)
70 outl(M32R_ICUCR_ILEVEL7, port);
73 static struct irq_chip opsput_irq_type =
76 .startup = startup_opsput_irq,
77 .shutdown = shutdown_opsput_irq,
78 .enable = enable_opsput_irq,
79 .disable = disable_opsput_irq,
80 .ack = mask_and_ack_opsput,
85 * Interrupt Control Unit of PLD on OPSPUT (Level 2)
87 #define irq2pldirq(x) ((x) - OPSPUT_PLD_IRQ_BASE)
88 #define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
89 (((x) - 1) * sizeof(unsigned short)))
92 unsigned short icucr; /* ICU Control Register */
95 static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];
97 static void disable_opsput_pld_irq(unsigned int irq)
99 unsigned long port, data;
102 pldirq = irq2pldirq(irq);
103 // disable_opsput_irq(M32R_IRQ_INT1);
104 port = pldirq2port(pldirq);
105 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
109 static void enable_opsput_pld_irq(unsigned int irq)
111 unsigned long port, data;
114 pldirq = irq2pldirq(irq);
115 // enable_opsput_irq(M32R_IRQ_INT1);
116 port = pldirq2port(pldirq);
117 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
121 static void mask_and_ack_opsput_pld(unsigned int irq)
123 disable_opsput_pld_irq(irq);
124 // mask_and_ack_opsput(M32R_IRQ_INT1);
127 static void end_opsput_pld_irq(unsigned int irq)
129 enable_opsput_pld_irq(irq);
130 end_opsput_irq(M32R_IRQ_INT1);
133 static unsigned int startup_opsput_pld_irq(unsigned int irq)
135 enable_opsput_pld_irq(irq);
139 static void shutdown_opsput_pld_irq(unsigned int irq)
144 pldirq = irq2pldirq(irq);
145 // shutdown_opsput_irq(M32R_IRQ_INT1);
146 port = pldirq2port(pldirq);
147 outw(PLD_ICUCR_ILEVEL7, port);
150 static struct irq_chip opsput_pld_irq_type =
152 .name = "OPSPUT-PLD-IRQ",
153 .startup = startup_opsput_pld_irq,
154 .shutdown = shutdown_opsput_pld_irq,
155 .enable = enable_opsput_pld_irq,
156 .disable = disable_opsput_pld_irq,
157 .ack = mask_and_ack_opsput_pld,
158 .end = end_opsput_pld_irq
162 * Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
164 #define irq2lanpldirq(x) ((x) - OPSPUT_LAN_PLD_IRQ_BASE)
165 #define lanpldirq2port(x) (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
166 (((x) - 1) * sizeof(unsigned short)))
168 static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];
170 static void disable_opsput_lanpld_irq(unsigned int irq)
172 unsigned long port, data;
175 pldirq = irq2lanpldirq(irq);
176 port = lanpldirq2port(pldirq);
177 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
181 static void enable_opsput_lanpld_irq(unsigned int irq)
183 unsigned long port, data;
186 pldirq = irq2lanpldirq(irq);
187 port = lanpldirq2port(pldirq);
188 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
192 static void mask_and_ack_opsput_lanpld(unsigned int irq)
194 disable_opsput_lanpld_irq(irq);
197 static void end_opsput_lanpld_irq(unsigned int irq)
199 enable_opsput_lanpld_irq(irq);
200 end_opsput_irq(M32R_IRQ_INT0);
203 static unsigned int startup_opsput_lanpld_irq(unsigned int irq)
205 enable_opsput_lanpld_irq(irq);
209 static void shutdown_opsput_lanpld_irq(unsigned int irq)
214 pldirq = irq2lanpldirq(irq);
215 port = lanpldirq2port(pldirq);
216 outw(PLD_ICUCR_ILEVEL7, port);
219 static struct irq_chip opsput_lanpld_irq_type =
221 .name = "OPSPUT-PLD-LAN-IRQ",
222 .startup = startup_opsput_lanpld_irq,
223 .shutdown = shutdown_opsput_lanpld_irq,
224 .enable = enable_opsput_lanpld_irq,
225 .disable = disable_opsput_lanpld_irq,
226 .ack = mask_and_ack_opsput_lanpld,
227 .end = end_opsput_lanpld_irq
231 * Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
233 #define irq2lcdpldirq(x) ((x) - OPSPUT_LCD_PLD_IRQ_BASE)
234 #define lcdpldirq2port(x) (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
235 (((x) - 1) * sizeof(unsigned short)))
237 static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];
239 static void disable_opsput_lcdpld_irq(unsigned int irq)
241 unsigned long port, data;
244 pldirq = irq2lcdpldirq(irq);
245 port = lcdpldirq2port(pldirq);
246 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
250 static void enable_opsput_lcdpld_irq(unsigned int irq)
252 unsigned long port, data;
255 pldirq = irq2lcdpldirq(irq);
256 port = lcdpldirq2port(pldirq);
257 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
261 static void mask_and_ack_opsput_lcdpld(unsigned int irq)
263 disable_opsput_lcdpld_irq(irq);
266 static void end_opsput_lcdpld_irq(unsigned int irq)
268 enable_opsput_lcdpld_irq(irq);
269 end_opsput_irq(M32R_IRQ_INT2);
272 static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
274 enable_opsput_lcdpld_irq(irq);
278 static void shutdown_opsput_lcdpld_irq(unsigned int irq)
283 pldirq = irq2lcdpldirq(irq);
284 port = lcdpldirq2port(pldirq);
285 outw(PLD_ICUCR_ILEVEL7, port);
288 static struct irq_chip opsput_lcdpld_irq_type =
290 "OPSPUT-PLD-LCD-IRQ",
291 startup_opsput_lcdpld_irq,
292 shutdown_opsput_lcdpld_irq,
293 enable_opsput_lcdpld_irq,
294 disable_opsput_lcdpld_irq,
295 mask_and_ack_opsput_lcdpld,
296 end_opsput_lcdpld_irq
299 void __init init_IRQ(void)
301 #if defined(CONFIG_SMC91X)
302 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
303 set_irq_chip(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type);
304 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
305 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
306 #endif /* CONFIG_SMC91X */
308 /* MFT2 : system timer */
309 set_irq_chip(M32R_IRQ_MFT2, &opsput_irq_type);
310 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
311 disable_opsput_irq(M32R_IRQ_MFT2);
314 set_irq_chip(M32R_IRQ_SIO0_R, &opsput_irq_type);
315 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
316 disable_opsput_irq(M32R_IRQ_SIO0_R);
319 set_irq_chip(M32R_IRQ_SIO0_S, &opsput_irq_type);
320 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
321 disable_opsput_irq(M32R_IRQ_SIO0_S);
324 set_irq_chip(M32R_IRQ_SIO1_R, &opsput_irq_type);
325 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
326 disable_opsput_irq(M32R_IRQ_SIO1_R);
329 set_irq_chip(M32R_IRQ_SIO1_S, &opsput_irq_type);
330 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
331 disable_opsput_irq(M32R_IRQ_SIO1_S);
334 set_irq_chip(M32R_IRQ_DMA1, &opsput_irq_type);
335 icu_data[M32R_IRQ_DMA1].icucr = 0;
336 disable_opsput_irq(M32R_IRQ_DMA1);
338 #ifdef CONFIG_SERIAL_M32R_PLDSIO
339 /* INT#1: SIO0 Receive on PLD */
340 set_irq_chip(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type);
341 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
342 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
344 /* INT#1: SIO0 Send on PLD */
345 set_irq_chip(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type);
346 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
347 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
348 #endif /* CONFIG_SERIAL_M32R_PLDSIO */
350 /* INT#1: CFC IREQ on PLD */
351 set_irq_chip(PLD_IRQ_CFIREQ, &opsput_pld_irq_type);
352 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
353 disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
355 /* INT#1: CFC Insert on PLD */
356 set_irq_chip(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type);
357 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
358 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
360 /* INT#1: CFC Eject on PLD */
361 set_irq_chip(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type);
362 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
363 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
366 * INT0# is used for LAN, DIO
369 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
370 enable_opsput_irq(M32R_IRQ_INT0);
373 * INT1# is used for UART, MMC, CF Controller in FPGA.
376 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
377 enable_opsput_irq(M32R_IRQ_INT1);
379 #if defined(CONFIG_USB)
380 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
382 set_irq_chip(OPSPUT_LCD_IRQ_USB_INT1, &opsput_lcdpld_irq_type);
383 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
384 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
387 * INT2# is used for BAT, USB, AUDIO
390 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
391 enable_opsput_irq(M32R_IRQ_INT2);
393 #if defined(CONFIG_VIDEO_M32R_AR)
395 * INT3# is used for AR
397 set_irq_chip(M32R_IRQ_INT3, &opsput_irq_type);
398 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
399 disable_opsput_irq(M32R_IRQ_INT3);
400 #endif /* CONFIG_VIDEO_M32R_AR */
403 #if defined(CONFIG_SMC91X)
405 #define LAN_IOSTART 0x300
406 #define LAN_IOEND 0x320
407 static struct resource smc91x_resources[] = {
409 .start = (LAN_IOSTART),
411 .flags = IORESOURCE_MEM,
414 .start = OPSPUT_LAN_IRQ_LAN,
415 .end = OPSPUT_LAN_IRQ_LAN,
416 .flags = IORESOURCE_IRQ,
420 static struct platform_device smc91x_device = {
423 .num_resources = ARRAY_SIZE(smc91x_resources),
424 .resource = smc91x_resources,
428 #if defined(CONFIG_FB_S1D13XXX)
430 #include <video/s1d13xxxfb.h>
431 #include <asm/s1d13806.h>
433 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
434 .initregs = s1d13xxxfb_initregs,
435 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
436 .platform_init_video = NULL,
438 .platform_suspend_video = NULL,
439 .platform_resume_video = NULL,
443 static struct resource s1d13xxxfb_resources[] = {
445 .start = 0x10600000UL,
447 .flags = IORESOURCE_MEM,
450 .start = 0x10400000UL,
452 .flags = IORESOURCE_MEM,
456 static struct platform_device s1d13xxxfb_device = {
457 .name = S1D_DEVICENAME,
460 .platform_data = &s1d13xxxfb_data,
462 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
463 .resource = s1d13xxxfb_resources,
467 static int __init platform_init(void)
469 #if defined(CONFIG_SMC91X)
470 platform_device_register(&smc91x_device);
472 #if defined(CONFIG_FB_S1D13XXX)
473 platform_device_register(&s1d13xxxfb_device);
477 arch_initcall(platform_init);