2 * linux/arch/m32r/platforms/usrv/setup.c
4 * Setup routines for MITSUBISHI uServer
6 * Copyright (c) 2001, 2002, 2003 Hiroyuki Kondo, Hirokazu Takata,
10 #include <linux/irq.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
14 #include <asm/system.h>
18 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
20 icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
22 static void disable_mappi_irq(unsigned int irq)
24 unsigned long port, data;
27 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
31 static void enable_mappi_irq(unsigned int irq)
33 unsigned long port, data;
36 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
40 static void mask_and_ack_mappi(unsigned int irq)
42 disable_mappi_irq(irq);
45 static void end_mappi_irq(unsigned int irq)
47 enable_mappi_irq(irq);
50 static unsigned int startup_mappi_irq(unsigned int irq)
52 enable_mappi_irq(irq);
56 static void shutdown_mappi_irq(unsigned int irq)
61 outl(M32R_ICUCR_ILEVEL7, port);
64 static struct irq_chip mappi_irq_type =
67 .startup = startup_mappi_irq,
68 .shutdown = shutdown_mappi_irq,
69 .enable = enable_mappi_irq,
70 .disable = disable_mappi_irq,
71 .ack = mask_and_ack_mappi,
76 * Interrupt Control Unit of PLD on M32700UT (Level 2)
78 #define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
79 #define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
80 (((x) - 1) * sizeof(unsigned short)))
83 unsigned short icucr; /* ICU Control Register */
86 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
88 static void disable_m32700ut_pld_irq(unsigned int irq)
90 unsigned long port, data;
93 pldirq = irq2pldirq(irq);
94 port = pldirq2port(pldirq);
95 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
99 static void enable_m32700ut_pld_irq(unsigned int irq)
101 unsigned long port, data;
104 pldirq = irq2pldirq(irq);
105 port = pldirq2port(pldirq);
106 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
110 static void mask_and_ack_m32700ut_pld(unsigned int irq)
112 disable_m32700ut_pld_irq(irq);
115 static void end_m32700ut_pld_irq(unsigned int irq)
117 enable_m32700ut_pld_irq(irq);
118 end_mappi_irq(M32R_IRQ_INT1);
121 static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
123 enable_m32700ut_pld_irq(irq);
127 static void shutdown_m32700ut_pld_irq(unsigned int irq)
132 pldirq = irq2pldirq(irq);
133 port = pldirq2port(pldirq);
134 outw(PLD_ICUCR_ILEVEL7, port);
137 static struct irq_chip m32700ut_pld_irq_type =
139 .name = "USRV-PLD-IRQ",
140 .startup = startup_m32700ut_pld_irq,
141 .shutdown = shutdown_m32700ut_pld_irq,
142 .enable = enable_m32700ut_pld_irq,
143 .disable = disable_m32700ut_pld_irq,
144 .ack = mask_and_ack_m32700ut_pld,
145 .end = end_m32700ut_pld_irq
148 void __init init_IRQ(void)
158 /* MFT2 : system timer */
159 set_irq_chip(M32R_IRQ_MFT2, &mappi_irq_type);
160 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
161 disable_mappi_irq(M32R_IRQ_MFT2);
163 #if defined(CONFIG_SERIAL_M32R_SIO)
164 /* SIO0_R : uart receive data */
165 set_irq_chip(M32R_IRQ_SIO0_R, &mappi_irq_type);
166 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
167 disable_mappi_irq(M32R_IRQ_SIO0_R);
169 /* SIO0_S : uart send data */
170 set_irq_chip(M32R_IRQ_SIO0_S, &mappi_irq_type);
171 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
172 disable_mappi_irq(M32R_IRQ_SIO0_S);
174 /* SIO1_R : uart receive data */
175 set_irq_chip(M32R_IRQ_SIO1_R, &mappi_irq_type);
176 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
177 disable_mappi_irq(M32R_IRQ_SIO1_R);
179 /* SIO1_S : uart send data */
180 set_irq_chip(M32R_IRQ_SIO1_S, &mappi_irq_type);
181 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
182 disable_mappi_irq(M32R_IRQ_SIO1_S);
183 #endif /* CONFIG_SERIAL_M32R_SIO */
185 /* INT#67-#71: CFC#0 IREQ on PLD */
186 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
187 set_irq_chip(PLD_IRQ_CF0 + i, &m32700ut_pld_irq_type);
188 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
189 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
190 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
193 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
194 /* INT#76: 16552D#0 IREQ on PLD */
195 set_irq_chip(PLD_IRQ_UART0, &m32700ut_pld_irq_type);
196 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
197 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
198 disable_m32700ut_pld_irq(PLD_IRQ_UART0);
200 /* INT#77: 16552D#1 IREQ on PLD */
201 set_irq_chip(PLD_IRQ_UART1, &m32700ut_pld_irq_type);
202 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
203 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
204 disable_m32700ut_pld_irq(PLD_IRQ_UART1);
205 #endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
207 #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
208 /* INT#80: AK4524 IREQ on PLD */
209 set_irq_chip(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type);
210 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
211 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
212 disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
213 #endif /* CONFIG_IDC_AK4524 || CONFIG_IDC_AK4524_MODULE */
216 * INT1# is used for UART, MMC, CF Controller in FPGA.
219 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD11;
220 enable_mappi_irq(M32R_IRQ_INT1);