1 /***************************************************************************/
4 * m527x.c -- platform support for ColdFire 527x based boards
6 * Sub-architcture dependent initialization code for the Freescale
7 * 5270/5271 and 5274/5275 CPUs.
9 * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
13 /***************************************************************************/
15 #include <linux/kernel.h>
16 #include <linux/param.h>
17 #include <linux/init.h>
19 #include <asm/machdep.h>
20 #include <asm/coldfire.h>
21 #include <asm/mcfsim.h>
22 #include <asm/mcfuart.h>
23 #include <asm/mcfclk.h>
25 /***************************************************************************/
27 DEFINE_CLK(pll, "pll.0", MCF_CLK);
28 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
29 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
30 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
31 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
32 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
33 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
34 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
35 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
36 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
37 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
38 DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
39 DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
41 struct clk *mcf_clks[] = {
58 /***************************************************************************/
60 static void __init m527x_qspi_init(void)
62 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
63 #if defined(CONFIG_M5271)
66 /* setup QSPS pins for QSPI with gpio CS control */
67 writeb(0x1f, MCFGPIO_PAR_QSPI);
68 /* and CS2 & CS3 as gpio */
69 par = readw(MCFGPIO_PAR_TIMER);
71 writew(par, MCFGPIO_PAR_TIMER);
72 #elif defined(CONFIG_M5275)
73 /* setup QSPS pins for QSPI with gpio CS control */
74 writew(0x003e, MCFGPIO_PAR_QSPI);
76 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
79 /***************************************************************************/
81 static void __init m527x_i2c_init(void)
83 #if IS_ENABLED(CONFIG_I2C_IMX)
84 #if defined(CONFIG_M5271)
87 /* setup Port FECI2C Pin Assignment Register for I2C */
88 /* set PAR_SCL to SCL and PAR_SDA to SDA */
89 par = readb(MCFGPIO_PAR_FECI2C);
91 writeb(par, MCFGPIO_PAR_FECI2C);
92 #elif defined(CONFIG_M5275)
95 /* setup Port FECI2C Pin Assignment Register for I2C */
96 /* set PAR_SCL to SCL and PAR_SDA to SDA */
97 par = readw(MCFGPIO_PAR_FECI2C);
99 writew(par, MCFGPIO_PAR_FECI2C);
101 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
104 /***************************************************************************/
106 static void __init m527x_uarts_init(void)
111 * External Pin Mask Setting & Enable External Pin for Interface
113 sepmask = readw(MCFGPIO_PAR_UART);
114 sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
115 writew(sepmask, MCFGPIO_PAR_UART);
118 /***************************************************************************/
120 static void __init m527x_fec_init(void)
124 /* Set multi-function pins to ethernet mode for fec0 */
125 #if defined(CONFIG_M5271)
126 v = readb(MCFGPIO_PAR_FECI2C);
127 writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
131 par = readw(MCFGPIO_PAR_FECI2C);
132 writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
133 v = readb(MCFGPIO_PAR_FEC0HL);
134 writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
136 /* Set multi-function pins to ethernet mode for fec1 */
137 par = readw(MCFGPIO_PAR_FECI2C);
138 writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
139 v = readb(MCFGPIO_PAR_FEC1HL);
140 writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
144 /***************************************************************************/
146 void __init config_BSP(char *commandp, int size)
148 mach_sched_init = hw_timer_init;
155 /***************************************************************************/