3 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap.h>
31 DECLARE_GLOBAL_DATA_PTR;
34 * Low Power Divider specifications
36 #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
37 #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
39 #define CLOCK_PLL_FVCO_MAX 540000000
40 #define CLOCK_PLL_FVCO_MIN 300000000
42 #define CLOCK_PLL_FSYS_MAX 266666666
43 #define CLOCK_PLL_FSYS_MIN 100000000
46 void clock_enter_limp(int lpdiv)
48 ccm_t *ccm = (ccm_t *)MMAP_CCM;
51 /* Check bounds of divider */
52 if (lpdiv < CLOCK_LPD_MIN)
53 lpdiv = CLOCK_LPD_MIN;
54 if (lpdiv > CLOCK_LPD_MAX)
55 lpdiv = CLOCK_LPD_MAX;
57 /* Round divider down to nearest power of two */
58 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
60 /* Apply the divider to the system clock */
61 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
63 /* Enable Limp Mode */
64 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
68 * brief Exit Limp mode
69 * warning The PLL should be set and locked prior to exiting Limp mode
71 void clock_exit_limp(void)
73 ccm_t *ccm = (ccm_t *)MMAP_CCM;
74 pll_t *pll = (pll_t *)MMAP_PLL;
77 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
79 /* Wait for the PLL to lock */
80 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
85 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
90 ccm_t *ccm = (ccm_t *)MMAP_CCM;
91 pll_t *pll = (pll_t *)MMAP_PLL;
92 int vco, temp, pcrvalue, pfdr;
95 pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
96 pfdr = pcrvalue >> 24;
99 bootmode = 0; /* Normal Mode */
102 bootmode = 3; /* Serial Mode */
107 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
108 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
110 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
111 pcrvalue |= 0x1E << 24;
112 out_be32(&pll->pcr, pcrvalue);
114 ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
115 CONFIG_SYS_INPUT_CLKSRC;
117 gd->arch.vco_clk = vco; /* Vco clock */
118 } else if (bootmode == 3) {
120 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
121 gd->arch.vco_clk = vco; /* Vco clock */
124 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
127 gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
129 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
130 gd->cpu_clk = vco / temp; /* cpu clock */
132 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
133 gd->arch.flb_clk = vco / temp; /* flexbus clock */
134 gd->bus_clk = gd->arch.flb_clk;
137 #ifdef CONFIG_SYS_I2C_FSL
138 gd->arch.i2c1_clk = gd->bus_clk;