3 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap.h>
31 DECLARE_GLOBAL_DATA_PTR;
34 * Low Power Divider specifications
36 #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
37 #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
39 #define CLOCK_PLL_FVCO_MAX 540000000
40 #define CLOCK_PLL_FVCO_MIN 300000000
42 #define CLOCK_PLL_FSYS_MAX 266666666
43 #define CLOCK_PLL_FSYS_MIN 100000000
46 void clock_enter_limp(int lpdiv)
48 ccm_t *ccm = (ccm_t *)MMAP_CCM;
51 /* Check bounds of divider */
52 if (lpdiv < CLOCK_LPD_MIN)
53 lpdiv = CLOCK_LPD_MIN;
54 if (lpdiv > CLOCK_LPD_MAX)
55 lpdiv = CLOCK_LPD_MAX;
57 /* Round divider down to nearest power of two */
58 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
60 /* Apply the divider to the system clock */
61 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
63 /* Enable Limp Mode */
64 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
68 * brief Exit Limp mode
69 * warning The PLL should be set and locked prior to exiting Limp mode
71 void clock_exit_limp(void)
73 ccm_t *ccm = (ccm_t *)MMAP_CCM;
74 pll_t *pll = (pll_t *)MMAP_PLL;
77 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
79 /* Wait for the PLL to lock */
80 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
85 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
90 ccm_t *ccm = (ccm_t *)MMAP_CCM;
91 pll_t *pll = (pll_t *)MMAP_PLL;
92 int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
93 int pllmult_pci[] = { 12, 6, 16, 8 };
94 int vco = 0, temp, fbtemp, pcrvalue;
101 #ifdef CONFIG_M54455EVB
102 u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
106 /* To determine PCI is present or not */
107 if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
108 ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
109 pPllmult = &pllmult_pci[0];
110 fbpll_mask = 3; /* 11b */
115 pPllmult = &pllmult_nopci[0];
116 fbpll_mask = 7; /* 111b */
123 #ifdef CONFIG_M54455EVB
124 bootmode = (in_8(cpld) & 0x03);
127 /* Temporary read from CCR- fixed fb issue, must be the same clock
128 as pci or input clock, causing cpld/fpga read inconsistancy */
129 fbtemp = pPllmult[ccm->ccr & fbpll_mask];
131 /* Break down into small pieces, code still in flex bus */
132 pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
134 pcrvalue |= PLL_PCR_OUTDIV3(temp);
136 out_be32(&pll->pcr, pcrvalue);
139 #ifdef CONFIG_M54451EVB
140 /* No external logic to read the bootmode, hard coded from built */
146 /* default value is 16 mul, set to 20 mul */
147 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
148 out_be32(&pll->pcr, pcrvalue);
149 while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
156 vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
158 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
159 /* invaild range, re-set in PCR */
160 int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
163 j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
164 for (i = j; i < 0xFF; i++) {
165 vco = i * CONFIG_SYS_INPUT_CLKSRC;
166 if (vco >= CLOCK_PLL_FVCO_MIN) {
168 if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
174 pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
175 fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
176 pcrvalue |= ((i << 24) | fbtemp);
178 out_be32(&pll->pcr, pcrvalue);
180 gd->vco_clk = vco; /* Vco clock */
181 } else if (bootmode == 2) {
183 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
184 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
186 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
187 pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
188 out_be32(&pll->pcr, pcrvalue);
189 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
191 gd->vco_clk = vco; /* Vco clock */
192 } else if (bootmode == 3) {
194 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
195 gd->vco_clk = vco; /* Vco clock */
198 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
201 gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
203 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
204 gd->cpu_clk = vco / temp; /* cpu clock */
206 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
207 gd->bus_clk = vco / temp; /* bus clock */
209 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
210 gd->flb_clk = vco / temp; /* FlexBus clock */
214 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
215 gd->pci_clk = vco / temp; /* PCI clock */
220 #ifdef CONFIG_FSL_I2C
221 gd->i2c1_clk = gd->bus_clk;