2 * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
8 #define CPU_NAME "COLDFIRE(m54xx)"
10 #define MCFINT_VECBASE 64
13 * Interrupt Controller Registers
15 #define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */
16 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
17 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
18 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
19 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
20 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
21 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
22 #define MCFINTC_IRLR 0x18 /* */
23 #define MCFINTC_IACKL 0x19 /* */
24 #define MCFINTC_ICR0 0x40 /* Base ICR register */
27 * Define system peripheral IRQ usage.
29 #define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
30 #define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */
33 * Generic GPIO support
35 #define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */
36 #define MCFGPIO_IRQ_MAX -1
37 #define MCFGPIO_IRQ_VECBASE -1
40 * Some PSC related definitions
42 #define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
43 #define MCF_PAR_SDA (0x0008)
44 #define MCF_PAR_SCL (0x0004)
45 #define MCF_PAR_PSC_TXD (0x04)
46 #define MCF_PAR_PSC_RXD (0x08)
47 #define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
48 #define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
49 #define MCF_PAR_PSC_CTS_GPIO (0x00)
50 #define MCF_PAR_PSC_CTS_BCLK (0x80)
51 #define MCF_PAR_PSC_CTS_CTS (0xC0)
52 #define MCF_PAR_PSC_RTS_GPIO (0x00)
53 #define MCF_PAR_PSC_RTS_FSYNC (0x20)
54 #define MCF_PAR_PSC_RTS_RTS (0x30)
55 #define MCF_PAR_PSC_CANRX (0x40)
57 #endif /* m54xxsim_h */